From nobody Wed Nov 5 09:28:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499429919485369.84645562917547; Fri, 7 Jul 2017 05:18:39 -0700 (PDT) Received: from localhost ([::1]:56153 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dTSDV-0006zj-8o for importer@patchew.org; Fri, 07 Jul 2017 08:18:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35695) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dTSCS-0006Od-Bt for qemu-devel@nongnu.org; Fri, 07 Jul 2017 08:17:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dTSCN-0004cN-Co for qemu-devel@nongnu.org; Fri, 07 Jul 2017 08:17:32 -0400 Received: from roura.ac.upc.edu ([147.83.33.10]:38188 helo=roura.ac.upc.es) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dTSCN-0004c7-09 for qemu-devel@nongnu.org; Fri, 07 Jul 2017 08:17:27 -0400 Received: from correu-2.ac.upc.es (correu-2.ac.upc.es [147.83.30.92]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v67CHMo1020993; Fri, 7 Jul 2017 14:17:22 +0200 Received: from localhost (63.red-83-51-187.dynamicip.rima-tde.net [83.51.187.63]) by correu-2.ac.upc.es (Postfix) with ESMTPSA id CC6866FD; Fri, 7 Jul 2017 14:17:16 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Fri, 7 Jul 2017 14:17:11 +0200 Message-Id: <149942983074.8972.4124917122042440113.stgit@frigg.lan> X-Mailer: git-send-email 2.13.2 In-Reply-To: <149942760788.8972.474351671751194003.stgit@frigg.lan> References: <149942760788.8972.474351671751194003.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v67CHMo1020993 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v12 09/27] target/i386: [tcg] Port to translate_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Peter Crosthwaite , "Emilio G. Cota" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Reviewed-by: Emilio G. Cota --- target/i386/translate.c | 72 +++++++++++++++++++++++++++++++------------= ---- 1 file changed, 48 insertions(+), 24 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index d39e65e5b0..18447b88b2 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -4419,15 +4419,17 @@ static void gen_sse(CPUX86State *env, DisasContext = *s, int b, =20 /* convert one instruction. s->base.is_jmp is set if the translation must be stopped. Return the next pc value */ -static target_ulong disas_insn(CPUX86State *env, DisasContext *s, - target_ulong pc_start) +static target_ulong disas_insn(DisasContextBase *dcbase, CPUState *cpu) { + DisasContext *s =3D container_of(dcbase, DisasContext, base); + CPUX86State *env =3D cpu->env_ptr; int b, prefixes; int shift; TCGMemOp ot, aflag, dflag; int modrm, reg, rm, mod, op, opreg, val; target_ulong next_eip, tval; int rex_w, rex_r; + target_ulong pc_start =3D s->base.pc_next; =20 s->pc_start =3D s->pc =3D pc_start; prefixes =3D 0; @@ -8474,10 +8476,51 @@ static BreakpointCheckType i386_tr_breakpoint_check( } } =20 +static target_ulong i386_tr_translate_insn(DisasContextBase *dcbase, + CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + target_ulong pc_next =3D disas_insn(&dc->base, cpu); + + if (dc->base.is_jmp) { + return pc_next; + } + + if (dc->tf || (dc->base.tb->flags & HF_INHIBIT_IRQ_MASK)) { + /* if single step mode, we generate only one instruction and + generate an exception */ + /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear + the flag and abort the translation to give the irqs a + chance to happen */ + gen_jmp_im(pc_next - dc->cs_base); + gen_eob(dc); + dc->base.is_jmp =3D DISAS_TOO_MANY; + } else if ((dc->base.tb->cflags & CF_USE_ICOUNT) + && ((dc->base.pc_next & TARGET_PAGE_MASK) + !=3D ((dc->base.pc_next + TARGET_MAX_INSN_SIZE - 1) + & TARGET_PAGE_MASK) + || (dc->base.pc_next & ~TARGET_PAGE_MASK) =3D=3D 0)) { + /* Do not cross the boundary of the pages in icount mode, + it can cause an exception. Do it only when boundary is + crossed by the first instruction in the block. + If current instruction already crossed the bound - it's ok, + because an exception hasn't stopped this code. + */ + gen_jmp_im(pc_next - dc->cs_base); + gen_eob(dc); + dc->base.is_jmp =3D DISAS_TOO_MANY; + } else if ((pc_next - dc->base.pc_first) >=3D (TARGET_PAGE_SIZE - 32))= { + gen_jmp_im(pc_next - dc->cs_base); + gen_eob(dc); + dc->base.is_jmp =3D DISAS_TOO_MANY; + } + + return pc_next; +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { - CPUX86State *env =3D cs->env_ptr; DisasContext dc1, *dc =3D &dc1; int num_insns; int max_insns; @@ -8537,39 +8580,20 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) gen_io_start(); } =20 - dc->base.pc_next =3D disas_insn(env, dc, dc->base.pc_next); + dc->base.pc_next =3D i386_tr_translate_insn(&dc->base, cs); /* stop translation if indicated */ if (dc->base.is_jmp) { break; } /* if single step mode, we generate only one instruction and generate an exception */ - /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear - the flag and abort the translation to give the irqs a - change to be happen */ - if (dc->tf || dc->base.singlestep_enabled || - (dc->base.tb->flags & HF_INHIBIT_IRQ_MASK)) { - gen_jmp_im(dc->base.pc_next - dc->cs_base); - gen_eob(dc); - break; - } - /* Do not cross the boundary of the pages in icount mode, - it can cause an exception. Do it only when boundary is - crossed by the first instruction in the block. - If current instruction already crossed the bound - it's ok, - because an exception hasn't stopped this code. - */ - if ((tb->cflags & CF_USE_ICOUNT) - && ((dc->base.pc_next & TARGET_PAGE_MASK) - !=3D ((dc->base.pc_next + TARGET_MAX_INSN_SIZE - 1) & TARG= ET_PAGE_MASK) - || (dc->base.pc_next & ~TARGET_PAGE_MASK) =3D=3D 0)) { + if (dc->base.singlestep_enabled) { gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); break; } /* if too long translation, stop generation too */ if (tcg_op_buf_full() || - (dc->base.pc_next - dc->base.pc_first) >=3D (TARGET_PAGE_SIZE = - 32) || num_insns >=3D max_insns) { gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc);