From nobody Wed Nov 5 07:32:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499274996348613.8442205494092; Wed, 5 Jul 2017 10:16:36 -0700 (PDT) Received: from localhost ([::1]:47276 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSnul-0004vZ-27 for importer@patchew.org; Wed, 05 Jul 2017 13:16:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41054) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSnsV-0003DK-GY for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:14:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dSnsQ-0002gM-Un for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:14:15 -0400 Received: from 11.mo3.mail-out.ovh.net ([87.98.184.158]:35252) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dSnsQ-0002di-OU for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:14:10 -0400 Received: from player158.ha.ovh.net (b6.ovh.net [213.186.33.56]) by mo3.mail-out.ovh.net (Postfix) with ESMTP id 57EFAFCC8B for ; Wed, 5 Jul 2017 19:14:03 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10652-153.w90-89.abo.wanadoo.fr [90.89.238.153]) (Authenticated sender: clg@kaod.org) by player158.ha.ovh.net (Postfix) with ESMTPSA id E73D862007D; Wed, 5 Jul 2017 19:13:56 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 5 Jul 2017 19:13:14 +0200 Message-Id: <1499274819-15607-2-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.5 In-Reply-To: <1499274819-15607-1-git-send-email-clg@kaod.org> References: <1499274819-15607-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2187342047442078694 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelkedrudeigddutdelucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 87.98.184.158 Subject: [Qemu-devel] [RFC PATCH 01/26] spapr: introduce the XIVE_EXPLOIT option in CAS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Alexander Graf , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" On POWER9, the Client Architecture Support (CAS) negotiation process determines whether the guest operates in XIVE Legacy compatibility (the former POWER8 interrupt model) or in XIVE exploitation mode (the newer POWER9 interrupt model). Bit 7 of Byte 23 of vector 5 is used for this purpose. Signed-off-by: C=C3=A9dric Le Goater --- hw/ppc/spapr.c | 13 +++++++------ include/hw/ppc/spapr_ovec.h | 1 + 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index d4d781876b27..27b12adc3582 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -910,7 +910,8 @@ static void spapr_dt_ov5_platform_support(void *fdt, in= t chosen) { PowerPCCPU *first_ppc_cpu =3D POWERPC_CPU(first_cpu); =20 - char val[2 * 3] =3D { + char val[2 * 4] =3D { + 23, 0x00, /* Xive mode: 0 =3D legacy (as in ISA 2.7), 1 =3D Exploi= tation */ 24, 0x00, /* Hash/Radix, filled in below. */ 25, 0x00, /* Hash options: Segment Tables =3D=3D no, GTSE =3D=3D n= o. */ 26, 0x40, /* Radix options: GTSE =3D=3D yes. */ @@ -918,19 +919,19 @@ static void spapr_dt_ov5_platform_support(void *fdt, = int chosen) =20 if (kvm_enabled()) { if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { - val[1] =3D 0x80; /* OV5_MMU_BOTH */ + val[3] =3D 0x80; /* OV5_MMU_BOTH */ } else if (kvmppc_has_cap_mmu_radix()) { - val[1] =3D 0x40; /* OV5_MMU_RADIX_300 */ + val[3] =3D 0x40; /* OV5_MMU_RADIX_300 */ } else { - val[1] =3D 0x00; /* Hash */ + val[3] =3D 0x00; /* Hash */ } } else { if (first_ppc_cpu->env.mmu_model & POWERPC_MMU_V3) { /* V3 MMU supports both hash and radix (with dynamic switching= ) */ - val[1] =3D 0xC0; + val[3] =3D 0xC0; } else { /* Otherwise we can only do hash */ - val[1] =3D 0x00; + val[3] =3D 0x00; } } _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", diff --git a/include/hw/ppc/spapr_ovec.h b/include/hw/ppc/spapr_ovec.h index f088833204de..0b464e22e75d 100644 --- a/include/hw/ppc/spapr_ovec.h +++ b/include/hw/ppc/spapr_ovec.h @@ -50,6 +50,7 @@ typedef struct sPAPROptionVector sPAPROptionVector; #define OV5_DRCONF_MEMORY OV_BIT(2, 2) #define OV5_FORM1_AFFINITY OV_BIT(5, 0) #define OV5_HP_EVT OV_BIT(6, 5) +#define OV5_XIVE_EXPLOIT OV_BIT(23, 7) =20 /* ISA 3.00 MMU features: */ #define OV5_MMU_BOTH OV_BIT(24, 0) /* Radix and hash */ --=20 2.7.5 From nobody Wed Nov 5 07:32:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499274972606565.701837453306; Wed, 5 Jul 2017 10:16:12 -0700 (PDT) Received: from localhost ([::1]:47274 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSnuL-0004Vm-Bn for importer@patchew.org; Wed, 05 Jul 2017 13:16:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41057) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSnsV-0003DP-IV for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:14:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dSnsR-0002gS-1n for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:14:15 -0400 Received: from 7.mo3.mail-out.ovh.net ([46.105.57.200]:57211) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dSnsQ-0002fk-R3 for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:14:10 -0400 Received: from player158.ha.ovh.net (b6.ovh.net [213.186.33.56]) by mo3.mail-out.ovh.net (Postfix) with ESMTP id 81075FCC9F for ; Wed, 5 Jul 2017 19:14:09 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10652-153.w90-89.abo.wanadoo.fr [90.89.238.153]) (Authenticated sender: clg@kaod.org) by player158.ha.ovh.net (Postfix) with ESMTPSA id 5351D62007C; Wed, 5 Jul 2017 19:14:03 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 5 Jul 2017 19:13:15 +0200 Message-Id: <1499274819-15607-3-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.5 In-Reply-To: <1499274819-15607-1-git-send-email-clg@kaod.org> References: <1499274819-15607-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2189030894523747302 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelkedrudeigddutdelucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.57.200 Subject: [Qemu-devel] [RFC PATCH 02/26] spapr: populate device tree depending on XIVE_EXPLOIT option X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Alexander Graf , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" When XIVE is supported, the device tree should be populated accordingly and the XIVE memory regions mapped to activate MMIOs. Depending on the design we choose, we could also allocate different ICS and ICP objects, or switch between objects. This needs to be discussed. Signed-off-by: C=C3=A9dric Le Goater --- hw/ppc/spapr.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 27b12adc3582..0256e7a537bf 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -778,6 +778,11 @@ static int spapr_dt_cas_updates(sPAPRMachineState *spa= pr, void *fdt, } } =20 + /* /interrupt controller */ + if (!spapr_ovec_test(ov5_updates, OV5_XIVE_EXPLOIT)) { + spapr_dt_xics(xics_max_server_number(), fdt, PHANDLE_XICP); + } + offset =3D fdt_path_offset(fdt, "/chosen"); if (offset < 0) { offset =3D fdt_add_subnode(fdt, 0, "chosen"); @@ -801,7 +806,7 @@ int spapr_h_cas_compose_response(sPAPRMachineState *spa= pr, =20 size -=3D sizeof(hdr); =20 - /* Create sceleton */ + /* Create skeleton */ fdt_skel =3D g_malloc0(size); _FDT((fdt_create(fdt_skel, size))); _FDT((fdt_begin_node(fdt_skel, ""))); @@ -1069,9 +1074,6 @@ static void *spapr_build_fdt(sPAPRMachineState *spapr, _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); =20 - /* /interrupt controller */ - spapr_dt_xics(xics_max_server_number(), fdt, PHANDLE_XICP); - ret =3D spapr_populate_memory(spapr, fdt); if (ret < 0) { error_report("couldn't setup memory nodes in fdt"); --=20 2.7.5 From nobody Wed Nov 5 07:32:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499275163879978.7812945020231; Wed, 5 Jul 2017 10:19:23 -0700 (PDT) Received: from localhost ([::1]:47286 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSnxP-0007fz-Id for importer@patchew.org; Wed, 05 Jul 2017 13:19:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41088) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSnsb-0003Hn-Ok for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:14:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dSnsX-0002it-8L for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:14:21 -0400 Received: from 15.mo3.mail-out.ovh.net ([87.98.150.177]:54414) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dSnsX-0002iD-1U for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:14:17 -0400 Received: from player158.ha.ovh.net (b6.ovh.net [213.186.33.56]) by mo3.mail-out.ovh.net (Postfix) with ESMTP id A8F54FB645 for ; Wed, 5 Jul 2017 19:14:15 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10652-153.w90-89.abo.wanadoo.fr [90.89.238.153]) (Authenticated sender: clg@kaod.org) by player158.ha.ovh.net (Postfix) with ESMTPSA id 7D71362007D; Wed, 5 Jul 2017 19:14:09 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 5 Jul 2017 19:13:16 +0200 Message-Id: <1499274819-15607-4-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.5 In-Reply-To: <1499274819-15607-1-git-send-email-clg@kaod.org> References: <1499274819-15607-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2190719745774029798 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelkedrudeigddutdelucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 87.98.150.177 Subject: [Qemu-devel] [RFC PATCH 03/26] target/ppc/POWER9: add POWERPC_EXCP_POWER9 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Alexander Graf , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Prepare ground for the new exception model XIVE of POWER9. Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/cpu-qom.h | 2 ++ target/ppc/excp_helper.c | 9 ++++++--- target/ppc/translate.c | 3 ++- target/ppc/translate_init.c | 2 +- 4 files changed, 11 insertions(+), 5 deletions(-) diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index d0cf6ca2a971..d7b78cf3f71c 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -132,6 +132,8 @@ enum powerpc_excp_t { POWERPC_EXCP_POWER7, /* POWER8 exception model */ POWERPC_EXCP_POWER8, + /* POWER9 exception model */ + POWERPC_EXCP_POWER9, }; =20 /*************************************************************************= ****/ diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 3a9f0861e773..dc7dff36a580 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -148,9 +148,11 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int e= xcp_model, int excp) */ #if defined(TARGET_PPC64) if (excp_model =3D=3D POWERPC_EXCP_POWER7 || - excp_model =3D=3D POWERPC_EXCP_POWER8) { + excp_model =3D=3D POWERPC_EXCP_POWER8 || + excp_model =3D=3D POWERPC_EXCP_POWER9) { lpes0 =3D !!(env->spr[SPR_LPCR] & LPCR_LPES0); - if (excp_model =3D=3D POWERPC_EXCP_POWER8) { + if (excp_model =3D=3D POWERPC_EXCP_POWER8 || + excp_model =3D=3D POWERPC_EXCP_POWER9) { ail =3D (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT; } else { ail =3D 0; @@ -651,7 +653,8 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int ex= cp_model, int excp) if (!(new_msr & MSR_HVB) && (env->spr[SPR_LPCR] & LPCR_ILE)) { new_msr |=3D (target_ulong)1 << MSR_LE; } - } else if (excp_model =3D=3D POWERPC_EXCP_POWER8) { + } else if (excp_model =3D=3D POWERPC_EXCP_POWER8 || + excp_model =3D=3D POWERPC_EXCP_POWER9) { if (new_msr & MSR_HVB) { if (env->spr[SPR_HID0] & HID0_HILE) { new_msr |=3D (target_ulong)1 << MSR_LE; diff --git a/target/ppc/translate.c b/target/ppc/translate.c index c0cd64d927c2..2d8c1b9e6836 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7064,7 +7064,8 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprint= f_function cpu_fprintf, =20 #if defined(TARGET_PPC64) if (env->excp_model =3D=3D POWERPC_EXCP_POWER7 || - env->excp_model =3D=3D POWERPC_EXCP_POWER8) { + env->excp_model =3D=3D POWERPC_EXCP_POWER8 || + env->excp_model =3D=3D POWERPC_EXCP_POWER9) { cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); } diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index 53aff5a7b734..b8c7b8150318 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -8962,7 +8962,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) pcc->sps =3D &POWER7_POWER8_sps; pcc->radix_page_info =3D &POWER9_radix_page_info; #endif - pcc->excp_model =3D POWERPC_EXCP_POWER8; + pcc->excp_model =3D POWERPC_EXCP_POWER9; pcc->bus_model =3D PPC_FLAGS_INPUT_POWER7; pcc->bfd_mach =3D bfd_mach_ppc64; pcc->flags =3D POWERPC_FLAG_VRE | POWERPC_FLAG_SE | --=20 2.7.5 From nobody Wed Nov 5 07:32:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499275127361705.4921356536597; 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Wed, 5 Jul 2017 19:14:15 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 5 Jul 2017 19:13:17 +0200 Message-Id: <1499274819-15607-5-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.5 In-Reply-To: <1499274819-15607-1-git-send-email-clg@kaod.org> References: <1499274819-15607-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2192408594587814886 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelkedrudeigddutdelucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.75.36 Subject: [Qemu-devel] [RFC PATCH 04/26] ppc/xive: introduce a skeleton for the XIVE interrupt controller model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Alexander Graf , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Let's provide an empty shell for the XIVE controller model with a couple of attributes for the IRQ number allocator. The latter is largely inspired by OPAL which allocates IPI IRQ numbers from the bottom of the IRQ number space and allocates the HW IRQ numbers from the top. The number of IPIs is simply deduced from the max number of CPUs the guest supports and we provision a arbitrary number of HW irqs. The XIVE object is kept private because it will hold internal tables which do not need to be exposed to sPAPR. Signed-off-by: C=C3=A9dric Le Goater --- default-configs/ppc64-softmmu.mak | 1 + hw/intc/Makefile.objs | 1 + hw/intc/xive-internal.h | 28 ++++++++++++ hw/intc/xive.c | 94 +++++++++++++++++++++++++++++++++++= ++++ include/hw/ppc/xive.h | 27 +++++++++++ 5 files changed, 151 insertions(+) create mode 100644 hw/intc/xive-internal.h create mode 100644 hw/intc/xive.c create mode 100644 include/hw/ppc/xive.h diff --git a/default-configs/ppc64-softmmu.mak b/default-configs/ppc64-soft= mmu.mak index 46c95993217d..1179c07e6e9f 100644 --- a/default-configs/ppc64-softmmu.mak +++ b/default-configs/ppc64-softmmu.mak @@ -56,6 +56,7 @@ CONFIG_SM501=3Dy CONFIG_XICS=3D$(CONFIG_PSERIES) CONFIG_XICS_SPAPR=3D$(CONFIG_PSERIES) CONFIG_XICS_KVM=3D$(and $(CONFIG_PSERIES),$(CONFIG_KVM)) +CONFIG_XIVE=3D$(CONFIG_PSERIES) # For PReP CONFIG_SERIAL_ISA=3Dy CONFIG_MC146818RTC=3Dy diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs index 78426a7dafcd..28b83456bfcc 100644 --- a/hw/intc/Makefile.objs +++ b/hw/intc/Makefile.objs @@ -35,6 +35,7 @@ obj-$(CONFIG_SH4) +=3D sh_intc.o obj-$(CONFIG_XICS) +=3D xics.o obj-$(CONFIG_XICS_SPAPR) +=3D xics_spapr.o obj-$(CONFIG_XICS_KVM) +=3D xics_kvm.o +obj-$(CONFIG_XIVE) +=3D xive.o obj-$(CONFIG_POWERNV) +=3D xics_pnv.o obj-$(CONFIG_ALLWINNER_A10_PIC) +=3D allwinner-a10-pic.o obj-$(CONFIG_S390_FLIC) +=3D s390_flic.o diff --git a/hw/intc/xive-internal.h b/hw/intc/xive-internal.h new file mode 100644 index 000000000000..155c2dcd6066 --- /dev/null +++ b/hw/intc/xive-internal.h @@ -0,0 +1,28 @@ +/* + * Copyright 2016,2017 IBM Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#ifndef _INTC_XIVE_INTERNAL_H +#define _INTC_XIVE_INTERNAL_H + +#include + +struct XIVE { + SysBusDevice parent; + + /* Properties */ + uint32_t nr_targets; + + /* IRQ number allocator */ + uint32_t int_count; /* Number of interrupts: nr_targets + HW I= RQs */ + uint32_t int_base; /* Min index */ + uint32_t int_max; /* Max index */ + uint32_t int_hw_bot; /* Bottom index of HW IRQ allocator */ + uint32_t int_ipi_top; /* Highest IPI index handed out so far + 1= */ +}; + +#endif /* _INTC_XIVE_INTERNAL_H */ diff --git a/hw/intc/xive.c b/hw/intc/xive.c new file mode 100644 index 000000000000..5b4ea915d87c --- /dev/null +++ b/hw/intc/xive.c @@ -0,0 +1,94 @@ +/* + * QEMU PowerPC XIVE model + * + * Copyright (c) 2017, IBM Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "target/ppc/cpu.h" +#include "sysemu/cpus.h" +#include "sysemu/dma.h" +#include "monitor/monitor.h" +#include "hw/ppc/xive.h" + +#include "xive-internal.h" + +/* + * Main XIVE object + */ + +/* Let's provision some HW IRQ numbers. We could use a XIVE property + * also but it does not seem necessary for the moment. + */ +#define MAX_HW_IRQS_ENTRIES (8 * 1024) + +static void xive_init(Object *obj) +{ + ; +} + +static void xive_realize(DeviceState *dev, Error **errp) +{ + XIVE *x =3D XIVE(dev); + + if (!x->nr_targets) { + error_setg(errp, "Number of interrupt targets needs to be greater = 0"); + return; + } + + /* Initialize IRQ number allocator. Let's use a base number if we + * need to introduce a notion of blocks one day. + */ + x->int_base =3D 0; + x->int_count =3D x->nr_targets + MAX_HW_IRQS_ENTRIES; + x->int_max =3D x->int_base + x->int_count; + x->int_hw_bot =3D x->int_max; + x->int_ipi_top =3D x->int_base; + + /* Reserve some numbers as OPAL does ? */ + if (x->int_ipi_top < 0x10) { + x->int_ipi_top =3D 0x10; + } +} + +static Property xive_properties[] =3D { + DEFINE_PROP_UINT32("nr-targets", XIVE, nr_targets, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void xive_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D xive_realize; + dc->props =3D xive_properties; + dc->desc =3D "XIVE"; +} + +static const TypeInfo xive_info =3D { + .name =3D TYPE_XIVE, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_init =3D xive_init, + .instance_size =3D sizeof(XIVE), + .class_init =3D xive_class_init, +}; + +static void xive_register_types(void) +{ + type_register_static(&xive_info); +} + +type_init(xive_register_types) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h new file mode 100644 index 000000000000..863f5a9c6b5f --- /dev/null +++ b/include/hw/ppc/xive.h @@ -0,0 +1,27 @@ +/* + * QEMU PowerPC XIVE model + * + * Copyright (c) 2017, IBM Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef PPC_XIVE_H +#define PPC_XIVE_H + +typedef struct XIVE XIVE; + +#define TYPE_XIVE "xive" +#define XIVE(obj) OBJECT_CHECK(XIVE, (obj), TYPE_XIVE) + +#endif /* PPC_XIVE_H */ --=20 2.7.5 From nobody Wed Nov 5 07:32:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499274993103566.8106607958412; Wed, 5 Jul 2017 10:16:33 -0700 (PDT) Received: from localhost ([::1]:47275 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSnuh-0004rx-Af for importer@patchew.org; Wed, 05 Jul 2017 13:16:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41176) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSnsn-0003Qo-UG for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:14:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dSnsj-0002o8-AN for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:14:33 -0400 Received: from 20.mo3.mail-out.ovh.net ([178.33.47.94]:36669) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dSnsj-0002no-0D for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:14:29 -0400 Received: from player158.ha.ovh.net (b6.ovh.net [213.186.33.56]) by mo3.mail-out.ovh.net (Postfix) with ESMTP id 0878CFCA42 for ; Wed, 5 Jul 2017 19:14:28 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10652-153.w90-89.abo.wanadoo.fr [90.89.238.153]) (Authenticated sender: clg@kaod.org) by player158.ha.ovh.net (Postfix) with ESMTPSA id D1CEB62007D; Wed, 5 Jul 2017 19:14:21 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 5 Jul 2017 19:13:18 +0200 Message-Id: <1499274819-15607-6-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.5 In-Reply-To: <1499274819-15607-1-git-send-email-clg@kaod.org> References: <1499274819-15607-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2194097446474845158 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelkedrudeigddutdelucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 178.33.47.94 Subject: [Qemu-devel] [RFC PATCH 05/26] ppc/xive: define XIVE internal tables X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Alexander Graf , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The XIVE interrupt controller of the POWER9 uses a set of tables to redirect exception from event sources to CPU threads. Among which we choose to model : - the State Bit Entries (SBE), also known as Event State Buffer (ESB). This is a two bit state machine for each event source which is used to trigger events. The bits are named "P" (pending) and "Q" (queued) and can be controlled by MMIO. - the Interrupt Virtualization Entry (IVE) table, also known as Event Assignment Structure (EAS). This table is indexed by the IRQ number and is looked up to find the Event Queue associated with a triggered event. - the Event Queue Descriptor (EQD) table, also known as Event Notification Descriptor (END). The EQD contains fields that specify the Event Queue on which event data is posted (and later pulled by the OS) and also a target (or VPD) to notify. An additional table was not modeled but we might need to to support the H_INT_SET_OS_REPORTING_LINE hcall: - the Virtual Processor Descriptor (VPD) table, also known as Notification Virtual Target (NVT). The XIVE object is expanded with the tables described above. The size of each table depends on the number of provisioned IRQ and the maximum number of CPUs in the system. The indexing is very basic and might need to be improved for the EQs. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive-internal.h | 95 +++++++++++++++++++++++++++++++++++++++++++++= ++++ hw/intc/xive.c | 72 +++++++++++++++++++++++++++++++++++++ 2 files changed, 167 insertions(+) diff --git a/hw/intc/xive-internal.h b/hw/intc/xive-internal.h index 155c2dcd6066..8e755aa88a14 100644 --- a/hw/intc/xive-internal.h +++ b/hw/intc/xive-internal.h @@ -11,6 +11,89 @@ =20 #include =20 +/* Utilities to manipulate these (originaly from OPAL) */ +#define MASK_TO_LSH(m) (__builtin_ffsl(m) - 1) +#define GETFIELD(m, v) (((v) & (m)) >> MASK_TO_LSH(m)) +#define SETFIELD(m, v, val) \ + (((v) & ~(m)) | ((((typeof(v))(val)) << MASK_TO_LSH(m)) & (m))) + +#define PPC_BIT(bit) (0x8000000000000000UL >> (bit)) +#define PPC_BIT32(bit) (0x80000000UL >> (bit)) +#define PPC_BIT8(bit) (0x80UL >> (bit)) +#define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs)) +#define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \ + PPC_BIT32(bs)) + +/* IVE/EAS + * + * One per interrupt source. Targets that interrupt to a given EQ + * and provides the corresponding logical interrupt number (EQ data) + * + * We also map this structure to the escalation descriptor inside + * an EQ, though in that case the valid and masked bits are not used. + */ +typedef struct XiveIVE { + /* Use a single 64-bit definition to make it easier to + * perform atomic updates + */ + uint64_t w; +#define IVE_VALID PPC_BIT(0) +#define IVE_EQ_BLOCK PPC_BITMASK(4, 7) /* Destination EQ block# = */ +#define IVE_EQ_INDEX PPC_BITMASK(8, 31) /* Destination EQ index */ +#define IVE_MASKED PPC_BIT(32) /* Masked */ +#define IVE_EQ_DATA PPC_BITMASK(33, 63) /* Data written to the EQ= */ +} XiveIVE; + +/* EQ */ +typedef struct XiveEQ { + uint32_t w0; +#define EQ_W0_VALID PPC_BIT32(0) +#define EQ_W0_ENQUEUE PPC_BIT32(1) +#define EQ_W0_UCOND_NOTIFY PPC_BIT32(2) +#define EQ_W0_BACKLOG PPC_BIT32(3) +#define EQ_W0_PRECL_ESC_CTL PPC_BIT32(4) +#define EQ_W0_ESCALATE_CTL PPC_BIT32(5) +#define EQ_W0_END_OF_INTR PPC_BIT32(6) +#define EQ_W0_QSIZE PPC_BITMASK32(12, 15) +#define EQ_W0_SW0 PPC_BIT32(16) +#define EQ_W0_FIRMWARE EQ_W0_SW0 /* Owned by FW */ +#define EQ_QSIZE_4K 0 +#define EQ_QSIZE_64K 4 +#define EQ_W0_HWDEP PPC_BITMASK32(24, 31) + uint32_t w1; +#define EQ_W1_ESn PPC_BITMASK32(0, 1) +#define EQ_W1_ESn_P PPC_BIT32(0) +#define EQ_W1_ESn_Q PPC_BIT32(1) +#define EQ_W1_ESe PPC_BITMASK32(2, 3) +#define EQ_W1_ESe_P PPC_BIT32(2) +#define EQ_W1_ESe_Q PPC_BIT32(3) +#define EQ_W1_GENERATION PPC_BIT32(9) +#define EQ_W1_PAGE_OFF PPC_BITMASK32(10, 31) + uint32_t w2; +#define EQ_W2_MIGRATION_REG PPC_BITMASK32(0, 3) +#define EQ_W2_OP_DESC_HI PPC_BITMASK32(4, 31) + uint32_t w3; +#define EQ_W3_OP_DESC_LO PPC_BITMASK32(0, 31) + uint32_t w4; +#define EQ_W4_ESC_EQ_BLOCK PPC_BITMASK32(4, 7) +#define EQ_W4_ESC_EQ_INDEX PPC_BITMASK32(8, 31) + uint32_t w5; +#define EQ_W5_ESC_EQ_DATA PPC_BITMASK32(1, 31) + uint32_t w6; +#define EQ_W6_FORMAT_BIT PPC_BIT32(8) +#define EQ_W6_NVT_BLOCK PPC_BITMASK32(9, 12) +#define EQ_W6_NVT_INDEX PPC_BITMASK32(13, 31) + uint32_t w7; +#define EQ_W7_F0_IGNORE PPC_BIT32(0) +#define EQ_W7_F0_BLK_GROUPING PPC_BIT32(1) +#define EQ_W7_F0_PRIORITY PPC_BITMASK32(8, 15) +#define EQ_W7_F1_WAKEZ PPC_BIT32(0) +#define EQ_W7_F1_LOG_SERVER_ID PPC_BITMASK32(1, 31) +} XiveEQ; + +#define XIVE_EQ_PRIORITY_COUNT 8 +#define XIVE_PRIORITY_MAX (XIVE_EQ_PRIORITY_COUNT - 1) + struct XIVE { SysBusDevice parent; =20 @@ -23,6 +106,18 @@ struct XIVE { uint32_t int_max; /* Max index */ uint32_t int_hw_bot; /* Bottom index of HW IRQ allocator */ uint32_t int_ipi_top; /* Highest IPI index handed out so far + 1= */ + + /* XIVE internal tables */ + void *sbe; + XiveIVE *ivt; + XiveEQ *eqdt; }; =20 +void xive_reset(void *dev); +XiveIVE *xive_get_ive(XIVE *x, uint32_t isn); +XiveEQ *xive_get_eq(XIVE *x, uint32_t idx); + +bool xive_eq_for_target(XIVE *x, uint32_t target, uint8_t prio, + uint32_t *out_eq_idx); + #endif /* _INTC_XIVE_INTERNAL_H */ diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 5b4ea915d87c..5b14d8155317 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -35,6 +35,27 @@ */ #define MAX_HW_IRQS_ENTRIES (8 * 1024) =20 + +void xive_reset(void *dev) +{ + XIVE *x =3D XIVE(dev); + int i; + + /* SBEs are initialized to 0b01 which corresponds to "ints off" */ + memset(x->sbe, 0x55, x->int_count / 4); + + /* Clear and mask all valid IVEs */ + for (i =3D x->int_base; i < x->int_max; i++) { + XiveIVE *ive =3D &x->ivt[i]; + if (ive->w & IVE_VALID) { + ive->w =3D IVE_VALID | IVE_MASKED; + } + } + + /* clear all EQs */ + memset(x->eqdt, 0, x->nr_targets * XIVE_EQ_PRIORITY_COUNT * sizeof(Xiv= eEQ)); +} + static void xive_init(Object *obj) { ; @@ -62,6 +83,19 @@ static void xive_realize(DeviceState *dev, Error **errp) if (x->int_ipi_top < 0x10) { x->int_ipi_top =3D 0x10; } + + /* Allocate SBEs (State Bit Entry). 2 bits, so 4 entries per byte */ + x->sbe =3D g_malloc0(x->int_count / 4); + + /* Allocate the IVT (Interrupt Virtualization Table) */ + x->ivt =3D g_malloc0(x->int_count * sizeof(XiveIVE)); + + /* Allocate the EQDT (Event Queue Descriptor Table), 8 priorities + * for each thread in the system */ + x->eqdt =3D g_malloc0(x->nr_targets * XIVE_EQ_PRIORITY_COUNT * + sizeof(XiveEQ)); + + qemu_register_reset(xive_reset, dev); } =20 static Property xive_properties[] =3D { @@ -92,3 +126,41 @@ static void xive_register_types(void) } =20 type_init(xive_register_types) + +XiveIVE *xive_get_ive(XIVE *x, uint32_t lisn) +{ + uint32_t idx =3D lisn; + + if (idx < x->int_base || idx >=3D x->int_max) { + return NULL; + } + + return &x->ivt[idx]; +} + +XiveEQ *xive_get_eq(XIVE *x, uint32_t idx) +{ + if (idx >=3D x->nr_targets * XIVE_EQ_PRIORITY_COUNT) { + return NULL; + } + + return &x->eqdt[idx]; +} + +/* TODO: improve EQ indexing. This is very simple and relies on the + * fact that target (CPU) numbers start at 0 and are contiguous. It + * should be OK for sPAPR. + */ +bool xive_eq_for_target(XIVE *x, uint32_t target, uint8_t priority, + uint32_t *out_eq_idx) +{ + if (priority > XIVE_PRIORITY_MAX || target >=3D x->nr_targets) { + return false; + } + + if (out_eq_idx) { + *out_eq_idx =3D target + priority; + } + + return true; +} --=20 2.7.5 From nobody Wed Nov 5 07:32:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499275180336590.3917092411286; Wed, 5 Jul 2017 10:19:40 -0700 (PDT) Received: from localhost ([::1]:47288 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSnxi-0007ui-1E for importer@patchew.org; Wed, 05 Jul 2017 13:19:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41208) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSnst-0003WI-V3 for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:14:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dSnsp-0002qf-Bf for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:14:39 -0400 Received: from 11.mo3.mail-out.ovh.net ([87.98.184.158]:54951) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dSnsp-0002qI-4p for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:14:35 -0400 Received: from player158.ha.ovh.net (b6.ovh.net [213.186.33.56]) by mo3.mail-out.ovh.net (Postfix) with ESMTP id 3172BFCBEC for ; Wed, 5 Jul 2017 19:14:34 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10652-153.w90-89.abo.wanadoo.fr [90.89.238.153]) (Authenticated sender: clg@kaod.org) by player158.ha.ovh.net (Postfix) with ESMTPSA id 06A6762006C; Wed, 5 Jul 2017 19:14:28 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 5 Jul 2017 19:13:19 +0200 Message-Id: <1499274819-15607-7-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.5 In-Reply-To: <1499274819-15607-1-git-send-email-clg@kaod.org> References: <1499274819-15607-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2196067770624543718 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelkedrudeigddutdelucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 87.98.184.158 Subject: [Qemu-devel] [RFC PATCH 06/26] ppc/xive: introduce a XIVE interrupt source model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Alexander Graf , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This is very similar to the current ICS_SIMPLE model in XICS. We try to reuse the ICS model because the sPAPR machine is tied to the XICSFabric interface and should be using a common framework to switch from one controller model to another: XICS <-> XIVE. The next patch will introduce the MMIO handlers to interact with XIVE interrupt sources. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 110 ++++++++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/ppc/xive.h | 12 ++++++ 2 files changed, 122 insertions(+) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 5b14d8155317..9ff14c0da595 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -26,6 +26,115 @@ =20 #include "xive-internal.h" =20 +static void xive_icp_irq(XiveICSState *xs, int lisn) +{ + +} + +/* + * XIVE Interrupt Source + */ +static void xive_ics_set_irq_msi(XiveICSState *xs, int srcno, int val) +{ + if (val) { + xive_icp_irq(xs, srcno + ICS_BASE(xs)->offset); + } +} + +static void xive_ics_set_irq_lsi(XiveICSState *xs, int srcno, int val) +{ + ICSIRQState *irq =3D &ICS_BASE(xs)->irqs[srcno]; + + if (val) { + irq->status |=3D XICS_STATUS_ASSERTED; + } else { + irq->status &=3D ~XICS_STATUS_ASSERTED; + } + + if (irq->status & XICS_STATUS_ASSERTED + && !(irq->status & XICS_STATUS_SENT)) { + irq->status |=3D XICS_STATUS_SENT; + xive_icp_irq(xs, srcno + ICS_BASE(xs)->offset); + } +} + +static void xive_ics_set_irq(void *opaque, int srcno, int val) +{ + XiveICSState *xs =3D ICS_XIVE(opaque); + ICSIRQState *irq =3D &ICS_BASE(xs)->irqs[srcno]; + + if (irq->flags & XICS_FLAGS_IRQ_LSI) { + xive_ics_set_irq_lsi(xs, srcno, val); + } else { + xive_ics_set_irq_msi(xs, srcno, val); + } +} + +static void xive_ics_reset(void *dev) +{ + ICSState *ics =3D ICS_BASE(dev); + int i; + uint8_t flags[ics->nr_irqs]; + + for (i =3D 0; i < ics->nr_irqs; i++) { + flags[i] =3D ics->irqs[i].flags; + } + + memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs); + + for (i =3D 0; i < ics->nr_irqs; i++) { + ics->irqs[i].flags =3D flags[i]; + } +} + +static void xive_ics_realize(ICSState *ics, Error **errp) +{ + XiveICSState *xs =3D ICS_XIVE(ics); + Object *obj; + Error *err =3D NULL; + + obj =3D object_property_get_link(OBJECT(xs), "xive", &err); + if (!obj) { + error_setg(errp, "%s: required link 'xive' not found: %s", + __func__, error_get_pretty(err)); + return; + } + xs->xive =3D XIVE(obj); + + if (!ics->nr_irqs) { + error_setg(errp, "Number of interrupts needs to be greater 0"); + return; + } + + ics->irqs =3D g_malloc0(ics->nr_irqs * sizeof(ICSIRQState)); + ics->qirqs =3D qemu_allocate_irqs(xive_ics_set_irq, xs, ics->nr_irqs); + + qemu_register_reset(xive_ics_reset, xs); +} + +static Property xive_ics_properties[] =3D { + DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0), + DEFINE_PROP_UINT32("irq-base", ICSState, offset, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void xive_ics_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ICSStateClass *isc =3D ICS_BASE_CLASS(klass); + + isc->realize =3D xive_ics_realize; + + dc->props =3D xive_ics_properties; +} + +static const TypeInfo xive_ics_info =3D { + .name =3D TYPE_ICS_XIVE, + .parent =3D TYPE_ICS_BASE, + .instance_size =3D sizeof(XiveICSState), + .class_init =3D xive_ics_class_init, +}; + /* * Main XIVE object */ @@ -123,6 +232,7 @@ static const TypeInfo xive_info =3D { static void xive_register_types(void) { type_register_static(&xive_info); + type_register_static(&xive_ics_info); } =20 type_init(xive_register_types) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 863f5a9c6b5f..544cc6e0c796 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -19,9 +19,21 @@ #ifndef PPC_XIVE_H #define PPC_XIVE_H =20 +#include "hw/ppc/xics.h" + typedef struct XIVE XIVE; +typedef struct XiveICSState XiveICSState; =20 #define TYPE_XIVE "xive" #define XIVE(obj) OBJECT_CHECK(XIVE, (obj), TYPE_XIVE) =20 +#define TYPE_ICS_XIVE "xive-source" +#define ICS_XIVE(obj) OBJECT_CHECK(XiveICSState, (obj), TYPE_ICS_XIVE) + +struct XiveICSState { + ICSState parent_obj; + + XIVE *xive; +}; + #endif /* PPC_XIVE_H */ --=20 2.7.5 From nobody Wed Nov 5 07:32:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 149927517690592.43551755578528; Wed, 5 Jul 2017 10:19:36 -0700 (PDT) Received: from localhost ([::1]:47287 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSnxd-0007qM-Hg for importer@patchew.org; Wed, 05 Jul 2017 13:19:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41267) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSnt0-0003bt-Dp for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:14:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dSnsw-0002u2-76 for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:14:46 -0400 Received: from 18.mo3.mail-out.ovh.net ([87.98.172.162]:55537) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dSnsv-0002tA-Tx for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:14:42 -0400 Received: from player158.ha.ovh.net (b6.ovh.net [213.186.33.56]) by mo3.mail-out.ovh.net (Postfix) with ESMTP id 5FFDFFCD11 for ; Wed, 5 Jul 2017 19:14:40 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10652-153.w90-89.abo.wanadoo.fr [90.89.238.153]) (Authenticated sender: clg@kaod.org) by player158.ha.ovh.net (Postfix) with ESMTPSA id 2FB9862006C; Wed, 5 Jul 2017 19:14:34 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 5 Jul 2017 19:13:20 +0200 Message-Id: <1499274819-15607-8-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.5 In-Reply-To: <1499274819-15607-1-git-send-email-clg@kaod.org> References: <1499274819-15607-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2197756620706974694 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelkedrudeigddutdelucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 87.98.172.162 Subject: [Qemu-devel] [RFC PATCH 07/26] ppc/xive: add MMIO handlers to the XIVE interrupt source X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Alexander Graf , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Each interrupt source is associated with a 2-bit state machine called an Event State Buffer (ESB). It is controlled by MMIO to trigger events. See code for more details on the states. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 230 ++++++++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/ppc/xive.h | 3 + 2 files changed, 233 insertions(+) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 9ff14c0da595..816031b8ac81 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -32,6 +32,226 @@ static void xive_icp_irq(XiveICSState *xs, int lisn) } =20 /* + * "magic" Event State Buffer (ESB) MMIO offsets. + * + * Each interrupt source has a 2-bit state machine called ESB + * which can be controlled by MMIO. It's made of 2 bits, P and + * Q. P indicates that an interrupt is pending (has been sent + * to a queue and is waiting for an EOI). Q indicates that the + * interrupt has been triggered while pending. + * + * This acts as a coalescing mechanism in order to guarantee + * that a given interrupt only occurs at most once in a queue. + * + * When doing an EOI, the Q bit will indicate if the interrupt + * needs to be re-triggered. + * + * The following offsets into the ESB MMIO allow to read or + * manipulate the PQ bits. They must be used with an 8-bytes + * load instruction. They all return the previous state of the + * interrupt (atomically). + * + * Additionally, some ESB pages support doing an EOI via a + * store at 0 and some ESBs support doing a trigger via a + * separate trigger page. + */ +#define XIVE_ESB_GET 0x800 +#define XIVE_ESB_SET_PQ_00 0xc00 +#define XIVE_ESB_SET_PQ_01 0xd00 +#define XIVE_ESB_SET_PQ_10 0xe00 +#define XIVE_ESB_SET_PQ_11 0xf00 + +#define XIVE_ESB_VAL_P 0x2 +#define XIVE_ESB_VAL_Q 0x1 + +#define XIVE_ESB_RESET 0x0 +#define XIVE_ESB_PENDING 0x2 +#define XIVE_ESB_QUEUED 0x3 +#define XIVE_ESB_OFF 0x1 + +static uint8_t xive_pq_get(XIVE *x, uint32_t lisn) +{ + uint32_t idx =3D lisn; + uint32_t byte =3D idx / 4; + uint32_t bit =3D (idx % 4) * 2; + uint8_t* pqs =3D (uint8_t *) x->sbe; + + return (pqs[byte] >> bit) & 0x3; +} + +static void xive_pq_set(XIVE *x, uint32_t lisn, uint8_t pq) +{ + uint32_t idx =3D lisn; + uint32_t byte =3D idx / 4; + uint32_t bit =3D (idx % 4) * 2; + uint8_t* pqs =3D (uint8_t *) x->sbe; + + pqs[byte] &=3D ~(0x3 << bit); + pqs[byte] |=3D (pq & 0x3) << bit; +} + +static bool xive_pq_eoi(XIVE *x, uint32_t lisn) +{ + uint8_t old_pq =3D xive_pq_get(x, lisn); + + switch (old_pq) { + case XIVE_ESB_RESET: + xive_pq_set(x, lisn, XIVE_ESB_RESET); + return false; + case XIVE_ESB_PENDING: + xive_pq_set(x, lisn, XIVE_ESB_RESET); + return false; + case XIVE_ESB_QUEUED: + xive_pq_set(x, lisn, XIVE_ESB_PENDING); + return true; + case XIVE_ESB_OFF: + xive_pq_set(x, lisn, XIVE_ESB_OFF); + return false; + default: + g_assert_not_reached(); + } +} + +static bool xive_pq_trigger(XIVE *x, uint32_t lisn) +{ + uint8_t old_pq =3D xive_pq_get(x, lisn); + + switch (old_pq) { + case XIVE_ESB_RESET: + xive_pq_set(x, lisn, XIVE_ESB_PENDING); + return true; + case XIVE_ESB_PENDING: + xive_pq_set(x, lisn, XIVE_ESB_QUEUED); + return true; + case XIVE_ESB_QUEUED: + xive_pq_set(x, lisn, XIVE_ESB_QUEUED); + return true; + case XIVE_ESB_OFF: + xive_pq_set(x, lisn, XIVE_ESB_OFF); + return false; + default: + g_assert_not_reached(); + } +} + +/* + * XIVE Interrupt Source MMIOs + */ +static void xive_ics_eoi(XiveICSState *xs, uint32_t srcno) +{ + ICSIRQState *irq =3D &ICS_BASE(xs)->irqs[srcno]; + + if (irq->flags & XICS_FLAGS_IRQ_LSI) { + irq->status &=3D ~XICS_STATUS_SENT; + } +} + +/* TODO: handle second page */ +static uint64_t xive_esb_read(void *opaque, hwaddr addr, unsigned size) +{ + XiveICSState *xs =3D ICS_XIVE(opaque); + XIVE *x =3D xs->xive; + uint32_t offset =3D addr & 0xF00; + uint32_t srcno =3D addr >> xs->esb_shift; + uint32_t lisn =3D srcno + ICS_BASE(xs)->offset; + XiveIVE *ive; + uint64_t ret =3D -1; + + ive =3D xive_get_ive(x, lisn); + if (!ive || !(ive->w & IVE_VALID)) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid LISN %d\n", lisn); + goto out; + } + + if (srcno >=3D ICS_BASE(xs)->nr_irqs) { + qemu_log_mask(LOG_GUEST_ERROR, + "XIVE: invalid IRQ number: %d/%d lisn: %d\n", + srcno, ICS_BASE(xs)->nr_irqs, lisn); + goto out; + } + + switch (offset) { + case 0: + xive_ics_eoi(xs, srcno); + + /* return TRUE or FALSE depending on PQ value */ + ret =3D xive_pq_eoi(x, lisn); + break; + + case XIVE_ESB_GET: + ret =3D xive_pq_get(x, lisn); + break; + + case XIVE_ESB_SET_PQ_00: + case XIVE_ESB_SET_PQ_01: + case XIVE_ESB_SET_PQ_10: + case XIVE_ESB_SET_PQ_11: + ret =3D xive_pq_get(x, lisn); + xive_pq_set(x, lisn, (offset >> 8) & 0x3); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB addr %d\n", offs= et); + } + +out: + return ret; +} + +static void xive_esb_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size) +{ + XiveICSState *xs =3D ICS_XIVE(opaque); + XIVE *x =3D xs->xive; + uint32_t offset =3D addr & 0xF00; + uint32_t srcno =3D addr >> xs->esb_shift; + uint32_t lisn =3D srcno + ICS_BASE(xs)->offset; + XiveIVE *ive; + bool notify =3D false; + + ive =3D xive_get_ive(x, lisn); + if (!ive || !(ive->w & IVE_VALID)) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid LISN %d\n", lisn); + return; + } + + if (srcno >=3D ICS_BASE(xs)->nr_irqs) { + qemu_log_mask(LOG_GUEST_ERROR, + "XIVE: invalid IRQ number: %d/%d lisn: %d\n", + srcno, ICS_BASE(xs)->nr_irqs, lisn); + return; + } + + switch (offset) { + case 0: + /* TODO: should we trigger even if the IVE is masked ? */ + notify =3D xive_pq_trigger(x, lisn); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid ESB write addr %d\n", + offset); + return; + } + + if (notify && !(ive->w & IVE_MASKED)) { + qemu_irq_pulse(ICS_BASE(xs)->qirqs[srcno]); + } +} + +static const MemoryRegionOps xive_esb_ops =3D { + .read =3D xive_esb_read, + .write =3D xive_esb_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .valid =3D { + .min_access_size =3D 8, + .max_access_size =3D 8, + }, + .impl =3D { + .min_access_size =3D 8, + .max_access_size =3D 8, + }, +}; + +/* * XIVE Interrupt Source */ static void xive_ics_set_irq_msi(XiveICSState *xs, int srcno, int val) @@ -106,15 +326,25 @@ static void xive_ics_realize(ICSState *ics, Error **e= rrp) return; } =20 + if (!xs->esb_shift) { + error_setg(errp, "ESB page size needs to be greater 0"); + return; + } + ics->irqs =3D g_malloc0(ics->nr_irqs * sizeof(ICSIRQState)); ics->qirqs =3D qemu_allocate_irqs(xive_ics_set_irq, xs, ics->nr_irqs); =20 + memory_region_init_io(&xs->esb_iomem, OBJECT(xs), &xive_esb_ops, xs, + "xive.esb", + (1ull << xs->esb_shift) * ICS_BASE(xs)->nr_irqs); + qemu_register_reset(xive_ics_reset, xs); } =20 static Property xive_ics_properties[] =3D { DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0), DEFINE_PROP_UINT32("irq-base", ICSState, offset, 0), + DEFINE_PROP_UINT32("shift", XiveICSState, esb_shift, 0), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 544cc6e0c796..5303d96f5f59 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -33,6 +33,9 @@ typedef struct XiveICSState XiveICSState; struct XiveICSState { ICSState parent_obj; =20 + uint32_t esb_shift; + MemoryRegion esb_iomem; + XIVE *xive; }; =20 --=20 2.7.5 From nobody Wed Nov 5 07:32:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499275353679231.3904361686249; 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Wed, 5 Jul 2017 19:14:40 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 5 Jul 2017 19:13:21 +0200 Message-Id: <1499274819-15607-9-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.5 In-Reply-To: <1499274819-15607-1-git-send-email-clg@kaod.org> References: <1499274819-15607-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2199445469917711334 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelkedrudeigddutdelucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 87.98.184.158 Subject: [Qemu-devel] [RFC PATCH 08/26] ppc/xive: add flags to the XIVE interrupt source X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Alexander Graf , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" These flags define some characteristics of the source : - XIVE_SRC_H_INT_ESB the Event State Buffer are controlled with a specific hcall H_INT_ESB - XIVE_SRC_LSI LSI or MSI source - XIVE_SRC_TRIGGER the full function page supports trigger - XIVE_SRC_STORE_EOI EOI can with a store. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 1 + include/hw/ppc/xive.h | 9 +++++++++ 2 files changed, 10 insertions(+) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 816031b8ac81..8f8bb8b787bd 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -345,6 +345,7 @@ static Property xive_ics_properties[] =3D { DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0), DEFINE_PROP_UINT32("irq-base", ICSState, offset, 0), DEFINE_PROP_UINT32("shift", XiveICSState, esb_shift, 0), + DEFINE_PROP_UINT64("flags", XiveICSState, flags, 0), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 5303d96f5f59..1178300c9df3 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -30,9 +30,18 @@ typedef struct XiveICSState XiveICSState; #define TYPE_ICS_XIVE "xive-source" #define ICS_XIVE(obj) OBJECT_CHECK(XiveICSState, (obj), TYPE_ICS_XIVE) =20 +/* + * XIVE Interrupt source flags + */ +#define XIVE_SRC_H_INT_ESB (1ull << (63 - 60)) +#define XIVE_SRC_LSI (1ull << (63 - 61)) +#define XIVE_SRC_TRIGGER (1ull << (63 - 62)) +#define XIVE_SRC_STORE_EOI (1ull << (63 - 63)) + struct XiveICSState { ICSState parent_obj; =20 + uint64_t flags; uint32_t esb_shift; MemoryRegion esb_iomem; =20 --=20 2.7.5 From nobody Wed Nov 5 07:32:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499275322497782.360744434748; Wed, 5 Jul 2017 10:22:02 -0700 (PDT) Received: from localhost ([::1]:47307 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSnzx-0001P3-KU for importer@patchew.org; Wed, 05 Jul 2017 13:21:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41377) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSntC-0003md-D0 for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:14:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dSnt8-0002zy-Ds for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:14:58 -0400 Received: from 17.mo3.mail-out.ovh.net ([87.98.178.58]:56930) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dSnt8-0002zF-3g for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:14:54 -0400 Received: from player158.ha.ovh.net (b6.ovh.net [213.186.33.56]) by mo3.mail-out.ovh.net (Postfix) with ESMTP id C4F2EFCC94 for ; Wed, 5 Jul 2017 19:14:52 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10652-153.w90-89.abo.wanadoo.fr [90.89.238.153]) (Authenticated sender: clg@kaod.org) by player158.ha.ovh.net (Postfix) with ESMTPSA id 83C9462007C; Wed, 5 Jul 2017 19:14:46 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 5 Jul 2017 19:13:22 +0200 Message-Id: <1499274819-15607-10-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.5 In-Reply-To: <1499274819-15607-1-git-send-email-clg@kaod.org> References: <1499274819-15607-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2201134321940138982 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelkedrudeigddutdelucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 87.98.178.58 Subject: [Qemu-devel] [RFC PATCH 09/26] ppc/xive: add an overall memory region for the ESBs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Alexander Graf , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Each source adds its own ESB mempry region to the overall ESB memory region of the controller. It will be mapped in the CPU address space when XIVE is activated. The default mapping address for the ESB memory region is the same one used on baremetal. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive-internal.h | 5 +++++ hw/intc/xive.c | 44 +++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 48 insertions(+), 1 deletion(-) diff --git a/hw/intc/xive-internal.h b/hw/intc/xive-internal.h index 8e755aa88a14..c06be823aad0 100644 --- a/hw/intc/xive-internal.h +++ b/hw/intc/xive-internal.h @@ -98,6 +98,7 @@ struct XIVE { SysBusDevice parent; =20 /* Properties */ + uint32_t chip_id; uint32_t nr_targets; =20 /* IRQ number allocator */ @@ -111,6 +112,10 @@ struct XIVE { void *sbe; XiveIVE *ivt; XiveEQ *eqdt; + + /* ESB and TIMA memory location */ + hwaddr vc_base; + MemoryRegion esb_iomem; }; =20 void xive_reset(void *dev); diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 8f8bb8b787bd..a1cb87a07b76 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -312,6 +312,7 @@ static void xive_ics_realize(ICSState *ics, Error **err= p) XiveICSState *xs =3D ICS_XIVE(ics); Object *obj; Error *err =3D NULL; + XIVE *x; =20 obj =3D object_property_get_link(OBJECT(xs), "xive", &err); if (!obj) { @@ -319,7 +320,7 @@ static void xive_ics_realize(ICSState *ics, Error **err= p) __func__, error_get_pretty(err)); return; } - xs->xive =3D XIVE(obj); + x =3D xs->xive =3D XIVE(obj); =20 if (!ics->nr_irqs) { error_setg(errp, "Number of interrupts needs to be greater 0"); @@ -338,6 +339,11 @@ static void xive_ics_realize(ICSState *ics, Error **er= rp) "xive.esb", (1ull << xs->esb_shift) * ICS_BASE(xs)->nr_irqs); =20 + /* Install the ESB memory region in the overall one */ + memory_region_add_subregion(&x->esb_iomem, + ICS_BASE(xs)->offset * (1 << xs->esb_shift= ), + &xs->esb_iomem); + qemu_register_reset(xive_ics_reset, xs); } =20 @@ -375,6 +381,32 @@ static const TypeInfo xive_ics_info =3D { */ #define MAX_HW_IRQS_ENTRIES (8 * 1024) =20 +/* VC BAR contains set translations for the ESBs and the EQs. */ +#define VC_BAR_DEFAULT 0x10000000000ull +#define VC_BAR_SIZE 0x08000000000ull + +#define P9_MMIO_BASE 0x006000000000000ull +#define P9_CHIP_BASE(id) (P9_MMIO_BASE | (0x40000000000ull * (uint64_t) (i= d))) + +static uint64_t xive_esb_default_read(void *p, hwaddr offset, unsigned siz= e) +{ + qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n", + __func__, offset, size); + return 0; +} + +static void xive_esb_default_write(void *opaque, hwaddr offset, uint64_t v= alue, + unsigned size) +{ + qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]= \n", + __func__, offset, value, size); +} + +static const MemoryRegionOps xive_esb_default_ops =3D { + .read =3D xive_esb_default_read, + .write =3D xive_esb_default_write, + .endianness =3D DEVICE_BIG_ENDIAN, +}; =20 void xive_reset(void *dev) { @@ -435,10 +467,20 @@ static void xive_realize(DeviceState *dev, Error **er= rp) x->eqdt =3D g_malloc0(x->nr_targets * XIVE_EQ_PRIORITY_COUNT * sizeof(XiveEQ)); =20 + /* VC BAR. That's the full window but we will only map the + * subregions in use. */ + x->vc_base =3D (hwaddr)(P9_CHIP_BASE(x->chip_id) | VC_BAR_DEFAULT); + + /* install default memory region handlers to log bogus access */ + memory_region_init_io(&x->esb_iomem, NULL, &xive_esb_default_ops, + NULL, "xive.esb", VC_BAR_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &x->esb_iomem); + qemu_register_reset(xive_reset, dev); } =20 static Property xive_properties[] =3D { + DEFINE_PROP_UINT32("chip-id", XIVE, chip_id, 0), DEFINE_PROP_UINT32("nr-targets", XIVE, nr_targets, 0), DEFINE_PROP_END_OF_LIST(), }; --=20 2.7.5 From nobody Wed Nov 5 07:32:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499275371286162.33962826071922; Wed, 5 Jul 2017 10:22:51 -0700 (PDT) Received: from localhost ([::1]:47310 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSo0m-00026l-2w for importer@patchew.org; Wed, 05 Jul 2017 13:22:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41448) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSntI-0003sN-6m for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:15:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dSntE-00034R-6q for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:15:04 -0400 Received: from 13.mo3.mail-out.ovh.net ([188.165.33.202]:48817) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dSntE-00033d-0W for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:15:00 -0400 Received: from player158.ha.ovh.net (b6.ovh.net [213.186.33.56]) by mo3.mail-out.ovh.net (Postfix) with ESMTP id E38F9FCD77 for ; Wed, 5 Jul 2017 19:14:58 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10652-153.w90-89.abo.wanadoo.fr [90.89.238.153]) (Authenticated sender: clg@kaod.org) by player158.ha.ovh.net (Postfix) with ESMTPSA id B833362006C; Wed, 5 Jul 2017 19:14:52 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 5 Jul 2017 19:13:23 +0200 Message-Id: <1499274819-15607-11-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.5 In-Reply-To: <1499274819-15607-1-git-send-email-clg@kaod.org> References: <1499274819-15607-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2202823170303822822 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelkedrudeigddutdelucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 188.165.33.202 Subject: [Qemu-devel] [RFC PATCH 10/26] ppc/xive: record interrupt source MMIO address for hcalls X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Alexander Graf , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The address of the MMIO page through which the Event State Buffer is controlled is returned to the guest by the H_INT_GET_SOURCE_INFO hcall. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 3 +++ include/hw/ppc/xive.h | 1 + 2 files changed, 4 insertions(+) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index a1cb87a07b76..0db97fd33981 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -344,6 +344,9 @@ static void xive_ics_realize(ICSState *ics, Error **err= p) ICS_BASE(xs)->offset * (1 << xs->esb_shift= ), &xs->esb_iomem); =20 + /* Record base address which is needed by the hcalls */ + xs->esb_base =3D x->vc_base + ICS_BASE(xs)->offset * (1 << xs->esb_shi= ft); + qemu_register_reset(xive_ics_reset, xs); } =20 diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 1178300c9df3..b06bc861b845 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -43,6 +43,7 @@ struct XiveICSState { =20 uint64_t flags; uint32_t esb_shift; + hwaddr esb_base; MemoryRegion esb_iomem; =20 XIVE *xive; --=20 2.7.5 From nobody Wed Nov 5 07:32:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499275514163420.2528916272653; Wed, 5 Jul 2017 10:25:14 -0700 (PDT) Received: from localhost ([::1]:47324 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSo35-0004np-RJ for importer@patchew.org; Wed, 05 Jul 2017 13:25:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41517) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSntO-00040a-IZ for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:15:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dSntK-00038Z-Is for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:15:10 -0400 Received: from 3.mo3.mail-out.ovh.net ([46.105.44.175]:44957) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dSntK-00037D-DX for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:15:06 -0400 Received: from player158.ha.ovh.net (b6.ovh.net [213.186.33.56]) by mo3.mail-out.ovh.net (Postfix) with ESMTP id 18295FCCB1 for ; Wed, 5 Jul 2017 19:15:05 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10652-153.w90-89.abo.wanadoo.fr [90.89.238.153]) (Authenticated sender: clg@kaod.org) by player158.ha.ovh.net (Postfix) with ESMTPSA id E1EE362006C; Wed, 5 Jul 2017 19:14:58 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 5 Jul 2017 19:13:24 +0200 Message-Id: <1499274819-15607-12-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.5 In-Reply-To: <1499274819-15607-1-git-send-email-clg@kaod.org> References: <1499274819-15607-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2204793492944882662 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelkedrudeigddutdelucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.44.175 Subject: [Qemu-devel] [RFC PATCH 11/26] ppc/xics: introduce a print_info() handler to the ICS and ICP objects X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Alexander Graf , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This handler will be used to customize the ouput of the XIVE interrupt source and presenter objects. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xics.c | 36 ++++++++++++++++++++++++------------ include/hw/ppc/xics.h | 2 ++ 2 files changed, 26 insertions(+), 12 deletions(-) diff --git a/hw/intc/xics.c b/hw/intc/xics.c index faa5c631f655..7837c2022b4a 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -40,18 +40,26 @@ =20 void icp_pic_print_info(ICPState *icp, Monitor *mon) { + ICPStateClass *k =3D ICP_GET_CLASS(icp); int cpu_index =3D icp->cs ? icp->cs->cpu_index : -1; =20 if (!icp->output) { return; } - monitor_printf(mon, "CPU %d XIRR=3D%08x (%p) PP=3D%02x MFRR=3D%02x\n", - cpu_index, icp->xirr, icp->xirr_owner, - icp->pending_priority, icp->mfrr); + + monitor_printf(mon, "CPU %d ", cpu_index); + if (k->print_info) { + k->print_info(icp, mon); + } else { + monitor_printf(mon, "XIRR=3D%08x (%p) PP=3D%02x MFRR=3D%02x\n", + icp->xirr, icp->xirr_owner, + icp->pending_priority, icp->mfrr); + } } =20 void ics_pic_print_info(ICSState *ics, Monitor *mon) { + ICSStateClass *k =3D ICS_BASE_GET_CLASS(ics); uint32_t i; =20 monitor_printf(mon, "ICS %4x..%4x %p\n", @@ -61,17 +69,21 @@ void ics_pic_print_info(ICSState *ics, Monitor *mon) return; } =20 - for (i =3D 0; i < ics->nr_irqs; i++) { - ICSIRQState *irq =3D ics->irqs + i; + if (k->print_info) { + k->print_info(ics, mon); + } else { + for (i =3D 0; i < ics->nr_irqs; i++) { + ICSIRQState *irq =3D ics->irqs + i; =20 - if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) { - continue; + if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) { + continue; + } + monitor_printf(mon, " %4x %s %02x %02x\n", + ics->offset + i, + (irq->flags & XICS_FLAGS_IRQ_LSI) ? + "LSI" : "MSI", + irq->priority, irq->status); } - monitor_printf(mon, " %4x %s %02x %02x\n", - ics->offset + i, - (irq->flags & XICS_FLAGS_IRQ_LSI) ? - "LSI" : "MSI", - irq->priority, irq->status); } } =20 diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h index 28d248abad61..902f3bfd0e33 100644 --- a/include/hw/ppc/xics.h +++ b/include/hw/ppc/xics.h @@ -69,6 +69,7 @@ struct ICPStateClass { void (*pre_save)(ICPState *icp); int (*post_load)(ICPState *icp, int version_id); void (*reset)(ICPState *icp); + void (*print_info)(ICPState *icp, Monitor *mon); }; =20 struct ICPState { @@ -119,6 +120,7 @@ struct ICSStateClass { void (*reject)(ICSState *s, uint32_t irq); void (*resend)(ICSState *s); void (*eoi)(ICSState *s, uint32_t irq); + void (*print_info)(ICSState *s, Monitor *mon); }; =20 struct ICSState { --=20 2.7.5 From nobody Wed Nov 5 07:32:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 149927533876471.43150913628222; Wed, 5 Jul 2017 10:22:18 -0700 (PDT) Received: from localhost ([::1]:47308 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSo0F-0001fl-Tj for importer@patchew.org; Wed, 05 Jul 2017 13:22:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41562) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSntU-00047r-I8 for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:15:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dSntQ-0003Ek-Hd for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:15:16 -0400 Received: from 7.mo3.mail-out.ovh.net ([46.105.57.200]:42470) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dSntQ-0003EG-Ag for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:15:12 -0400 Received: from player158.ha.ovh.net (b6.ovh.net [213.186.33.56]) by mo3.mail-out.ovh.net (Postfix) with ESMTP id 411CCFCC3E for ; Wed, 5 Jul 2017 19:15:11 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10652-153.w90-89.abo.wanadoo.fr [90.89.238.153]) (Authenticated sender: clg@kaod.org) by player158.ha.ovh.net (Postfix) with ESMTPSA id 178FD62006C; Wed, 5 Jul 2017 19:15:05 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 5 Jul 2017 19:13:25 +0200 Message-Id: <1499274819-15607-13-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.5 In-Reply-To: <1499274819-15607-1-git-send-email-clg@kaod.org> References: <1499274819-15607-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2206482345289812966 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelkedrudeigdduuddtucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.57.200 Subject: [Qemu-devel] [RFC PATCH 12/26] ppc/xive: add a print_info() handler for the interrupt source X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Alexander Graf , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This is much like the default one but we expose the PQ bits also. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 0db97fd33981..db808e0cbe3d 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -290,6 +290,25 @@ static void xive_ics_set_irq(void *opaque, int srcno, = int val) } } =20 +static void xive_ics_print_info(ICSState *ics, Monitor *mon) +{ + XiveICSState *xs =3D ICS_XIVE(ics); + int i; + + for (i =3D 0; i < ics->nr_irqs; i++) { + ICSIRQState *irq =3D ics->irqs + i; + + if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) { + continue; + } + monitor_printf(mon, " %4x %s pq=3D%02x status=3D%02x\n", + ics->offset + i, + (irq->flags & XICS_FLAGS_IRQ_LSI) ? "LSI" : "MSI", + xive_pq_get(xs->xive, ics->offset + i), + irq->status); + } +} + static void xive_ics_reset(void *dev) { ICSState *ics =3D ICS_BASE(dev); @@ -364,6 +383,7 @@ static void xive_ics_class_init(ObjectClass *klass, voi= d *data) ICSStateClass *isc =3D ICS_BASE_CLASS(klass); =20 isc->realize =3D xive_ics_realize; + isc->print_info =3D xive_ics_print_info; =20 dc->props =3D xive_ics_properties; } --=20 2.7.5 From nobody Wed Nov 5 07:32:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499275487618969.5721037138154; Wed, 5 Jul 2017 10:24:47 -0700 (PDT) Received: from localhost ([::1]:47323 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSo2f-0004Pk-61 for importer@patchew.org; Wed, 05 Jul 2017 13:24:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41616) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSnta-0004DU-PL for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:15:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dSntW-0003Hb-Nv for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:15:22 -0400 Received: from 14.mo3.mail-out.ovh.net ([188.165.43.98]:48672) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dSntW-0003Gy-EP for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:15:18 -0400 Received: from player158.ha.ovh.net (b6.ovh.net [213.186.33.56]) by mo3.mail-out.ovh.net (Postfix) with ESMTP id 6BE24FA9BB for ; Wed, 5 Jul 2017 19:15:17 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10652-153.w90-89.abo.wanadoo.fr [90.89.238.153]) (Authenticated sender: clg@kaod.org) by player158.ha.ovh.net (Postfix) with ESMTPSA id 4192162007E; Wed, 5 Jul 2017 19:15:11 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 5 Jul 2017 19:13:26 +0200 Message-Id: <1499274819-15607-14-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.5 In-Reply-To: <1499274819-15607-1-git-send-email-clg@kaod.org> References: <1499274819-15607-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2208171194221366246 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelkedrudeigdduuddtucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 188.165.43.98 Subject: [Qemu-devel] [RFC PATCH 13/26] ppc/xive: introduce a XIVE interrupt presenter model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Alexander Graf , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Just like the interrupt source model, we try to reuse the ICP model because the sPAPR machine is tied to the XICSFabric interface and should be using a common framework to switch from one controller model to another: XICS <-> XIVE. The XIVE interrupt presenter exposes a set of Thread Interrupt Management Areas, also called rings, one per different level of privilege (four in all). We only expose the OS ring for the sPAPR support for the moment. This area is used to handle priority management and interrupt acknowledgment among other things. The next patch will introduce the MMIO handlers to interact with the TIMA, OS only. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive-internal.h | 84 +++++++++++++++++++++++++++++++++++++++++++++= ++++ hw/intc/xive.c | 43 +++++++++++++++++++++++++ include/hw/ppc/xive.h | 14 +++++++++ 3 files changed, 141 insertions(+) diff --git a/hw/intc/xive-internal.h b/hw/intc/xive-internal.h index c06be823aad0..ba5e648a5258 100644 --- a/hw/intc/xive-internal.h +++ b/hw/intc/xive-internal.h @@ -24,6 +24,90 @@ #define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \ PPC_BIT32(bs)) =20 +/* + * Thread Management (aka "TM") registers + */ + +/* TM register offsets */ +#define TM_QW0_USER 0x000 /* All rings */ +#define TM_QW1_OS 0x010 /* Ring 0..2 */ +#define TM_QW2_HV_POOL 0x020 /* Ring 0..1 */ +#define TM_QW3_HV_PHYS 0x030 /* Ring 0..1 */ + +/* Byte offsets inside a QW QW0 QW1 QW2 QW3 */ +#define TM_NSR 0x0 /* + + - + */ +#define TM_CPPR 0x1 /* - + - + */ +#define TM_IPB 0x2 /* - + + + */ +#define TM_LSMFB 0x3 /* - + + + */ +#define TM_ACK_CNT 0x4 /* - + - - */ +#define TM_INC 0x5 /* - + - + */ +#define TM_AGE 0x6 /* - + - + */ +#define TM_PIPR 0x7 /* - + - + */ + +#define TM_WORD0 0x0 +#define TM_WORD1 0x4 + +/* + * QW word 2 contains the valid bit at the top and other fields + * depending on the QW. + */ +#define TM_WORD2 0x8 +#define TM_QW0W2_VU PPC_BIT32(0) +#define TM_QW0W2_LOGIC_SERV PPC_BITMASK32(1, 31) /* XX 2,31 ? */ +#define TM_QW1W2_VO PPC_BIT32(0) +#define TM_QW1W2_OS_CAM PPC_BITMASK32(8, 31) +#define TM_QW2W2_VP PPC_BIT32(0) +#define TM_QW2W2_POOL_CAM PPC_BITMASK32(8, 31) +#define TM_QW3W2_VT PPC_BIT32(0) +#define TM_QW3W2_LP PPC_BIT32(6) +#define TM_QW3W2_LE PPC_BIT32(7) +#define TM_QW3W2_T PPC_BIT32(31) + +/* + * In addition to normal loads to "peek" and writes (only when invalid) + * using 4 and 8 bytes accesses, the above registers support these + * "special" byte operations: + * + * - Byte load from QW0[NSR] - User level NSR (EBB) + * - Byte store to QW0[NSR] - User level NSR (EBB) + * - Byte load/store to QW1[CPPR] and QW3[CPPR] - CPPR access + * - Byte load from QW3[TM_WORD2] - Read VT||00000||LP||LE on thrd 0 + * otherwise VT||0000000 + * - Byte store to QW3[TM_WORD2] - Set VT bit (and LP/LE if present) + * + * Then we have all these "special" CI ops at these offset that trigger + * all sorts of side effects: + */ +#define TM_SPC_ACK_EBB 0x800 /* Load8 ack EBB to reg*/ +#define TM_SPC_ACK_OS_REG 0x810 /* Load16 ack OS irq to reg */ +#define TM_SPC_PUSH_USR_CTX 0x808 /* Store32 Push/Validate user cont= ext */ +#define TM_SPC_PULL_USR_CTX 0x808 /* Load32 Pull/Invalidate user + * context */ +#define TM_SPC_SET_OS_PENDING 0x812 /* Store8 Set OS irq pending bit */ +#define TM_SPC_PULL_OS_CTX 0x818 /* Load32/Load64 Pull/Invalidate OS + * context to reg */ +#define TM_SPC_PULL_POOL_CTX 0x828 /* Load32/Load64 Pull/Invalidate P= ool + * context to reg*/ +#define TM_SPC_ACK_HV_REG 0x830 /* Load16 ack HV irq to reg */ +#define TM_SPC_PULL_USR_CTX_OL 0xc08 /* Store8 Pull/Inval usr ctx to odd + * line */ +#define TM_SPC_ACK_OS_EL 0xc10 /* Store8 ack OS irq to even line = */ +#define TM_SPC_ACK_HV_POOL_EL 0xc20 /* Store8 ack HV evt pool to even + * line */ +#define TM_SPC_ACK_HV_EL 0xc30 /* Store8 ack HV irq to even line = */ +/* XXX more... */ + +/* NSR fields for the various QW ack types */ +#define TM_QW0_NSR_EB PPC_BIT8(0) +#define TM_QW1_NSR_EO PPC_BIT8(0) +#define TM_QW3_NSR_HE PPC_BITMASK8(0, 1) +#define TM_QW3_NSR_HE_NONE 0 +#define TM_QW3_NSR_HE_POOL 1 +#define TM_QW3_NSR_HE_PHYS 2 +#define TM_QW3_NSR_HE_LSI 3 +#define TM_QW3_NSR_I PPC_BIT8(2) +#define TM_QW3_NSR_GRP_LVL PPC_BIT8(3, 7) + /* IVE/EAS * * One per interrupt source. Targets that interrupt to a given EQ diff --git a/hw/intc/xive.c b/hw/intc/xive.c index db808e0cbe3d..c08a4f8efb58 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -26,6 +26,48 @@ =20 #include "xive-internal.h" =20 +static void xive_icp_reset(ICPState *icp) +{ + XiveICPState *xicp =3D XIVE_ICP(icp); + + memset(xicp->tima, 0, sizeof(xicp->tima)); +} + +static void xive_icp_print_info(ICPState *icp, Monitor *mon) +{ + XiveICPState *xicp =3D XIVE_ICP(icp); + + monitor_printf(mon, " CPPR=3D%02x IPB=3D%02x PIPR=3D%02x NSR=3D%02x\n", + xicp->tima_os[TM_CPPR], xicp->tima_os[TM_IPB], + xicp->tima_os[TM_PIPR], xicp->tima_os[TM_NSR]); +} + +static void xive_icp_init(Object *obj) +{ + XiveICPState *xicp =3D XIVE_ICP(obj); + + xicp->tima_os =3D &xicp->tima[TM_QW1_OS]; +} + +static void xive_icp_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ICPStateClass *icpc =3D ICP_CLASS(klass); + + dc->desc =3D "PowerNV Xive ICP"; + icpc->reset =3D xive_icp_reset; + icpc->print_info =3D xive_icp_print_info; +} + +static const TypeInfo xive_icp_info =3D { + .name =3D TYPE_XIVE_ICP, + .parent =3D TYPE_ICP, + .instance_size =3D sizeof(XiveICPState), + .instance_init =3D xive_icp_init, + .class_init =3D xive_icp_class_init, + .class_size =3D sizeof(ICPStateClass), +}; + static void xive_icp_irq(XiveICSState *xs, int lisn) { =20 @@ -529,6 +571,7 @@ static void xive_register_types(void) { type_register_static(&xive_info); type_register_static(&xive_ics_info); + type_register_static(&xive_icp_info); } =20 type_init(xive_register_types) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index b06bc861b845..f87df8107dd9 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -23,6 +23,7 @@ =20 typedef struct XIVE XIVE; typedef struct XiveICSState XiveICSState; +typedef struct XiveICPState XiveICPState; =20 #define TYPE_XIVE "xive" #define XIVE(obj) OBJECT_CHECK(XIVE, (obj), TYPE_XIVE) @@ -38,6 +39,9 @@ typedef struct XiveICSState XiveICSState; #define XIVE_SRC_TRIGGER (1ull << (63 - 62)) #define XIVE_SRC_STORE_EOI (1ull << (63 - 63)) =20 +#define TYPE_XIVE_ICP "xive-icp" +#define XIVE_ICP(obj) OBJECT_CHECK(XiveICPState, (obj), TYPE_XIVE_ICP) + struct XiveICSState { ICSState parent_obj; =20 @@ -49,4 +53,14 @@ struct XiveICSState { XIVE *xive; }; =20 +/* Number of Thread Management Interrupt Areas */ +#define XIVE_TM_RING_COUNT 4 + +struct XiveICPState { + ICPState parent_obj; + + uint8_t tima[XIVE_TM_RING_COUNT * 0x10]; + uint8_t *tima_os; +}; + #endif /* PPC_XIVE_H */ --=20 2.7.5 From nobody Wed Nov 5 07:32:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499275640627510.89902054652885; Wed, 5 Jul 2017 10:27:20 -0700 (PDT) Received: from localhost ([::1]:47341 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSo54-0006Zp-3M for importer@patchew.org; Wed, 05 Jul 2017 13:27:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41672) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSnth-0004K2-9f for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:15:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dSntd-0003LK-56 for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:15:29 -0400 Received: from 6.mo3.mail-out.ovh.net ([188.165.43.173]:38992) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dSntc-0003KT-Rv for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:15:25 -0400 Received: from player158.ha.ovh.net (b6.ovh.net [213.186.33.56]) by mo3.mail-out.ovh.net (Postfix) with ESMTP id 93C0BFCADA for ; Wed, 5 Jul 2017 19:15:23 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10652-153.w90-89.abo.wanadoo.fr [90.89.238.153]) (Authenticated sender: clg@kaod.org) by player158.ha.ovh.net (Postfix) with ESMTPSA id 6B28662007E; Wed, 5 Jul 2017 19:15:17 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 5 Jul 2017 19:13:27 +0200 Message-Id: <1499274819-15607-15-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.5 In-Reply-To: <1499274819-15607-1-git-send-email-clg@kaod.org> References: <1499274819-15607-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2209860044219976678 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelkedrudeigdduuddtucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 188.165.43.173 Subject: [Qemu-devel] [RFC PATCH 14/26] ppc/xive: add MMIO handlers to the XIVE interrupt presenter model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Alexander Graf , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The Thread Interrupt Management Area for the OS is mostly used to acknowledge interrupts and set the CPPR of the CPU. The TIMA is mapped at the same address for each CPU. 'current_cpu' is used to retrieve the targeted interrupt presenter object. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive-internal.h | 4 ++ hw/intc/xive.c | 187 ++++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 191 insertions(+) diff --git a/hw/intc/xive-internal.h b/hw/intc/xive-internal.h index ba5e648a5258..5e8b78a1ea6a 100644 --- a/hw/intc/xive-internal.h +++ b/hw/intc/xive-internal.h @@ -200,6 +200,10 @@ struct XIVE { /* ESB and TIMA memory location */ hwaddr vc_base; MemoryRegion esb_iomem; + + uint32_t tm_shift; + hwaddr tm_base; + MemoryRegion tm_iomem; }; =20 void xive_reset(void *dev); diff --git a/hw/intc/xive.c b/hw/intc/xive.c index c08a4f8efb58..82b2f0dcda0b 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -26,6 +26,180 @@ =20 #include "xive-internal.h" =20 +static uint8_t priority_to_ipb(uint8_t priority) +{ + return priority < XIVE_EQ_PRIORITY_COUNT ? 1 << (7 - priority) : 0; +} + +static uint64_t xive_icp_accept(XiveICPState *xicp) +{ + ICPState *icp =3D ICP(xicp); + uint8_t nsr =3D xicp->tima_os[TM_NSR]; + + qemu_irq_lower(icp->output); + + if (xicp->tima_os[TM_NSR] & TM_QW1_NSR_EO) { + uint8_t cppr =3D xicp->tima_os[TM_PIPR]; + + xicp->tima_os[TM_CPPR] =3D cppr; + + /* Reset the pending buffer bit */ + xicp->tima_os[TM_IPB] &=3D ~priority_to_ipb(cppr); + + /* Drop Exception bit for OS */ + xicp->tima_os[TM_NSR] &=3D ~TM_QW1_NSR_EO; + } + + return (nsr << 8) | xicp->tima_os[TM_CPPR]; +} + +static void xive_icp_set_cppr(XiveICPState *xicp, uint8_t cppr) +{ + if (cppr > XIVE_PRIORITY_MAX) { + cppr =3D 0xff; + } + + xicp->tima_os[TM_CPPR] =3D cppr; +} + +/* + * Thread Interrupt Management Area MMIO + */ +static uint64_t xive_tm_read_special(XiveICPState *icp, hwaddr offset, + unsigned size) +{ + uint64_t ret =3D -1; + + if (offset =3D=3D TM_SPC_ACK_OS_REG && size =3D=3D 2) { + ret =3D xive_icp_accept(icp); + } else { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid TIMA read @%" + HWADDR_PRIx" size %d\n", offset, size); + } + + return ret; +} + +static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size) +{ + PowerPCCPU *cpu =3D POWERPC_CPU(current_cpu); + XiveICPState *icp =3D XIVE_ICP(cpu->intc); + uint64_t ret =3D -1; + int i; + + if (offset >=3D TM_SPC_ACK_EBB) { + return xive_tm_read_special(icp, offset, size); + } + + if (offset & TM_QW1_OS) { + switch (size) { + case 1: + case 2: + case 4: + case 8: + if (QEMU_IS_ALIGNED(offset, size)) { + ret =3D 0; + for (i =3D 0; i < size; i++) { + ret |=3D icp->tima[offset + i] << (8 * i); + } + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "XIVE: invalid TIMA read alignment @%" + HWADDR_PRIx" size %d\n", offset, size); + } + break; + default: + g_assert_not_reached(); + } + } else { + qemu_log_mask(LOG_UNIMP, "XIVE: does handle non-OS TIMA ring @%" + HWADDR_PRIx"\n", offset); + } + + return ret; +} + +static bool xive_tm_is_readonly(uint8_t index) +{ + /* Let's be optimistic and prepare ground for HV mode support */ + switch (index) { + case TM_QW1_OS + TM_CPPR: + return false; + default: + return true; + } +} + +static void xive_tm_write_special(XiveICPState *xicp, hwaddr offset, + uint64_t value, unsigned size) +{ + if (offset =3D=3D TM_SPC_SET_OS_PENDING && size =3D=3D 1) { + xicp->tima_os[TM_IPB] |=3D priority_to_ipb(value & 0xff); + } else { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid TIMA write @%" + HWADDR_PRIx" size %d\n", offset, size); + } + + /* TODO: support TM_SPC_ACK_OS_EL */ +} + +static void xive_tm_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + PowerPCCPU *cpu =3D POWERPC_CPU(current_cpu); + XiveICPState *icp =3D XIVE_ICP(cpu->intc); + int i; + + if (offset >=3D TM_SPC_ACK_EBB) { + xive_tm_write_special(icp, offset, value, size); + return; + } + + if (offset & TM_QW1_OS) { + switch (size) { + case 1: + if (offset =3D=3D TM_QW1_OS + TM_CPPR) { + xive_icp_set_cppr(icp, value & 0xff); + } + break; + case 4: + case 8: + if (QEMU_IS_ALIGNED(offset, size)) { + for (i =3D 0; i < size; i++) { + if (!xive_tm_is_readonly(offset + i)) { + icp->tima[offset + i] =3D (value >> (8 * i)) & 0xf= f; + } + } + } else { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid TIMA write @= %" + HWADDR_PRIx" size %d\n", offset, size); + } + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid TIMA write @%" + HWADDR_PRIx" size %d\n", offset, size); + } + } else { + qemu_log_mask(LOG_UNIMP, "XIVE: does handle non-OS TIMA ring @%" + HWADDR_PRIx"\n", offset); + } +} + + +static const MemoryRegionOps xive_tm_ops =3D { + .read =3D xive_tm_read, + .write =3D xive_tm_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 8, + }, + .impl =3D { + .min_access_size =3D 1, + .max_access_size =3D 8, + }, +}; + static void xive_icp_reset(ICPState *icp) { XiveICPState *xicp =3D XIVE_ICP(icp); @@ -453,6 +627,11 @@ static const TypeInfo xive_ics_info =3D { #define P9_MMIO_BASE 0x006000000000000ull #define P9_CHIP_BASE(id) (P9_MMIO_BASE | (0x40000000000ull * (uint64_t) (i= d))) =20 +/* Thread Interrupt Management Area MMIO */ +#define TM_BAR_DEFAULT 0x30203180000ull +#define TM_SHIFT 16 +#define TM_BAR_SIZE (XIVE_TM_RING_COUNT * (1 << TM_SHIFT)) + static uint64_t xive_esb_default_read(void *p, hwaddr offset, unsigned siz= e) { qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n", @@ -541,6 +720,14 @@ static void xive_realize(DeviceState *dev, Error **err= p) NULL, "xive.esb", VC_BAR_SIZE); sysbus_init_mmio(SYS_BUS_DEVICE(dev), &x->esb_iomem); =20 + /* TM BAR. Same address for each chip */ + x->tm_base =3D (P9_MMIO_BASE | TM_BAR_DEFAULT); + x->tm_shift =3D TM_SHIFT; + + memory_region_init_io(&x->tm_iomem, OBJECT(x), &xive_tm_ops, x, + "xive.tm", TM_BAR_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &x->tm_iomem); + qemu_register_reset(xive_reset, dev); } =20 --=20 2.7.5 From nobody Wed Nov 5 07:32:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499275684494907.1568450099782; Wed, 5 Jul 2017 10:28:04 -0700 (PDT) Received: from localhost ([::1]:47344 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSo5p-0007Fu-UL for importer@patchew.org; Wed, 05 Jul 2017 13:28:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41751) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSntm-0004Os-Vx for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:15:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dSnti-0003So-VG for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:15:34 -0400 Received: from 14.mo3.mail-out.ovh.net ([188.165.43.98]:52678) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dSnti-0003QS-Pb for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:15:30 -0400 Received: from player158.ha.ovh.net (b6.ovh.net [213.186.33.56]) by mo3.mail-out.ovh.net (Postfix) with ESMTP id BFBD5FCC5C for ; Wed, 5 Jul 2017 19:15:29 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10652-153.w90-89.abo.wanadoo.fr [90.89.238.153]) (Authenticated sender: clg@kaod.org) by player158.ha.ovh.net (Postfix) with ESMTPSA id 947B062007E; Wed, 5 Jul 2017 19:15:23 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 5 Jul 2017 19:13:28 +0200 Message-Id: <1499274819-15607-16-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.5 In-Reply-To: <1499274819-15607-1-git-send-email-clg@kaod.org> References: <1499274819-15607-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2211548895279942630 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelkedrudeigdduuddtucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 188.165.43.98 Subject: [Qemu-devel] [RFC PATCH 15/26] ppc/xive: push EQ data in OS event queues X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Alexander Graf , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" If a triggered event is let through, the event queue data defined in the associated IVE is pushed in the in-memory event queue of the OS. The latter is a memory ring buffer defined by the OS with H_INT_SET_QUEUE_CONFIG hcall. Then, an interrupt presenter is located and notified. See next patch. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 94 insertions(+) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 82b2f0dcda0b..c3c1e9c9db2d 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -242,9 +242,103 @@ static const TypeInfo xive_icp_info =3D { .class_size =3D sizeof(ICPStateClass), }; =20 +static XiveICPState *xive_icp_get(XICSFabric *xi, int server) +{ + XICSFabricClass *xic =3D XICS_FABRIC_GET_CLASS(xi); + ICPState *icp =3D xic->icp_get(xi, server); + + return XIVE_ICP(icp); +} + +static void xive_eq_push(XiveEQ *eq, uint32_t data) +{ + uint64_t qaddr_base =3D (((uint64_t)(eq->w2 & 0x0fffffff)) << 32) | eq= ->w3; + uint32_t qsize =3D GETFIELD(EQ_W0_QSIZE, eq->w0); + uint32_t qindex =3D GETFIELD(EQ_W1_PAGE_OFF, eq->w1); + uint32_t qgen =3D GETFIELD(EQ_W1_GENERATION, eq->w1); + + uint64_t qaddr =3D qaddr_base + (qindex << 2); + uint32_t qdata =3D cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); + uint32_t qentries =3D 1 << (qsize + 10); + + if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdat= a))) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to write EQ data @0x%" + HWADDR_PRIx "\n", __func__, qaddr); + return; + } + + qindex =3D (qindex + 1) % qentries; + if (qindex =3D=3D 0) { + qgen ^=3D 1; + eq->w1 =3D SETFIELD(EQ_W1_GENERATION, eq->w1, qgen); + } + eq->w1 =3D SETFIELD(EQ_W1_PAGE_OFF, eq->w1, qindex); +} + static void xive_icp_irq(XiveICSState *xs, int lisn) { + XIVE *x =3D xs->xive; + XiveICPState *xicp; + XiveIVE *ive; + XiveEQ *eq; + uint32_t eq_idx; + uint32_t priority; + uint32_t target; + + ive =3D xive_get_ive(x, lisn); + if (!ive || !(ive->w & IVE_VALID)) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid LISN %d\n", lisn); + return; + } =20 + if (ive->w & IVE_MASKED) { + return; + } + + /* Find our XiveEQ */ + eq_idx =3D GETFIELD(IVE_EQ_INDEX, ive->w); + eq =3D xive_get_eq(x, eq_idx); + if (!eq) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No EQ for LISN %d\n", lisn); + return; + } + + if (eq->w0 & EQ_W0_ENQUEUE) { + xive_eq_push(eq, GETFIELD(IVE_EQ_DATA, ive->w)); + } else { + qemu_log_mask(LOG_UNIMP, "XIVE: !ENQUEUE not implemented\n"); + } + + if (!(eq->w0 & EQ_W0_UCOND_NOTIFY)) { + qemu_log_mask(LOG_UNIMP, "XIVE: !UCOND_NOTIFY not implemented\n"); + } + + target =3D GETFIELD(EQ_W6_NVT_INDEX, eq->w6); + + /* use the XICSFabric (machine) to get the ICP */ + xicp =3D xive_icp_get(ICS_BASE(xs)->xics, target); + if (!xicp) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No ICP for target %d\n", tar= get); + return; + } + + if (GETFIELD(EQ_W6_FORMAT_BIT, eq->w6) =3D=3D 0) { + priority =3D GETFIELD(EQ_W7_F0_PRIORITY, eq->w7); + + /* The EQ is masked. Can this happen ? */ + if (priority =3D=3D 0xff) { + return; + } + + /* Update the IPB (Interrupt Pending Buffer) with the priority + * of the new notification and inform the ICP, which will + * decide to raise the exception, or not, depending on its + * current CPPR value. + */ + xicp->tima_os[TM_IPB] |=3D priority_to_ipb(priority); + } else { + qemu_log_mask(LOG_UNIMP, "XIVE: w7 format1 not implemented\n"); + } } =20 /* --=20 2.7.5 From nobody Wed Nov 5 07:32:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499275532091357.68273130907676; Wed, 5 Jul 2017 10:25:32 -0700 (PDT) Received: from localhost ([::1]:47330 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSo3O-00055q-Tw for importer@patchew.org; Wed, 05 Jul 2017 13:25:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41830) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSntt-0004T2-Aa for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:15:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dSntp-0003gA-73 for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:15:41 -0400 Received: from 3.mo3.mail-out.ovh.net ([46.105.44.175]:48795) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dSntp-0003dl-04 for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:15:37 -0400 Received: from player158.ha.ovh.net (b6.ovh.net [213.186.33.56]) by mo3.mail-out.ovh.net (Postfix) with ESMTP id E7572FCD11 for ; Wed, 5 Jul 2017 19:15:35 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10652-153.w90-89.abo.wanadoo.fr [90.89.238.153]) (Authenticated sender: clg@kaod.org) by player158.ha.ovh.net (Postfix) with ESMTPSA id BE06C62007C; Wed, 5 Jul 2017 19:15:29 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 5 Jul 2017 19:13:29 +0200 Message-Id: <1499274819-15607-17-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.5 In-Reply-To: <1499274819-15607-1-git-send-email-clg@kaod.org> References: <1499274819-15607-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2213237745956850662 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelkedrudeigdduuddtucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.44.175 Subject: [Qemu-devel] [RFC PATCH 16/26] ppc/xive: notify CPU when interrupt priority is more privileged X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Alexander Graf , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index c3c1e9c9db2d..cda1fa18e44d 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -53,6 +53,21 @@ static uint64_t xive_icp_accept(XiveICPState *xicp) return (nsr << 8) | xicp->tima_os[TM_CPPR]; } =20 +static uint8_t ipb_to_pipr(uint8_t ibp) +{ + return ibp ? clz32((uint32_t)ibp << 24) : 0xff; +} + +static void xive_icp_notify(XiveICPState *xicp) +{ + xicp->tima_os[TM_PIPR] =3D ipb_to_pipr(xicp->tima_os[TM_IPB]); + + if (xicp->tima_os[TM_PIPR] < xicp->tima_os[TM_CPPR]) { + xicp->tima_os[TM_NSR] |=3D TM_QW1_NSR_EO; + qemu_irq_raise(ICP(xicp)->output); + } +} + static void xive_icp_set_cppr(XiveICPState *xicp, uint8_t cppr) { if (cppr > XIVE_PRIORITY_MAX) { @@ -60,6 +75,10 @@ static void xive_icp_set_cppr(XiveICPState *xicp, uint8_= t cppr) } =20 xicp->tima_os[TM_CPPR] =3D cppr; + + /* CPPR has changed, inform the ICP which might raise an + * exception */ + xive_icp_notify(xicp); } =20 /* @@ -339,6 +358,8 @@ static void xive_icp_irq(XiveICSState *xs, int lisn) } else { qemu_log_mask(LOG_UNIMP, "XIVE: w7 format1 not implemented\n"); } + + xive_icp_notify(xicp); } =20 /* --=20 2.7.5 From nobody Wed Nov 5 07:32:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499275854186397.4615559968024; Wed, 5 Jul 2017 10:30:54 -0700 (PDT) Received: from localhost ([::1]:47366 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSo8X-0001o6-Np for importer@patchew.org; Wed, 05 Jul 2017 13:30:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41885) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSnu0-0004ZC-8j for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:15:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dSntv-0003qd-Mn for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:15:48 -0400 Received: from 13.mo3.mail-out.ovh.net ([188.165.33.202]:40792) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dSntv-0003pD-9b for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:15:43 -0400 Received: from player158.ha.ovh.net (b6.ovh.net [213.186.33.56]) by mo3.mail-out.ovh.net (Postfix) with ESMTP id 20651FCCD6 for ; Wed, 5 Jul 2017 19:15:42 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10652-153.w90-89.abo.wanadoo.fr [90.89.238.153]) (Authenticated sender: clg@kaod.org) by player158.ha.ovh.net (Postfix) with ESMTPSA id E791F620081; Wed, 5 Jul 2017 19:15:35 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 5 Jul 2017 19:13:30 +0200 Message-Id: <1499274819-15607-18-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.5 In-Reply-To: <1499274819-15607-1-git-send-email-clg@kaod.org> References: <1499274819-15607-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2215208067909913574 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelkedrudeigdduuddtucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 188.165.33.202 Subject: [Qemu-devel] [RFC PATCH 17/26] ppc/xive: add hcalls support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Alexander Graf , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" A set of Hypervisor's call are used to configure the interrupt sources and the event/notification queues of the guest: H_INT_GET_SOURCE_INFO H_INT_SET_SOURCE_CONFIG H_INT_GET_SOURCE_CONFIG H_INT_GET_QUEUE_INFO H_INT_SET_QUEUE_CONFIG H_INT_GET_QUEUE_CONFIG H_INT_RESET H_INT_ESB Calls that still need to be addressed : H_INT_SET_OS_REPORTING_LINE H_INT_GET_OS_REPORTING_LINE H_INT_SYNC See below for the documentation on each hcall. Signed-off-by: C=C3=A9dric Le Goater --- default-configs/ppc64-softmmu.mak | 1 + hw/intc/Makefile.objs | 1 + hw/intc/xive_spapr.c | 745 ++++++++++++++++++++++++++++++++++= ++++ include/hw/ppc/spapr.h | 17 +- include/hw/ppc/xive.h | 4 + 5 files changed, 767 insertions(+), 1 deletion(-) create mode 100644 hw/intc/xive_spapr.c diff --git a/default-configs/ppc64-softmmu.mak b/default-configs/ppc64-soft= mmu.mak index 1179c07e6e9f..3888168adf95 100644 --- a/default-configs/ppc64-softmmu.mak +++ b/default-configs/ppc64-softmmu.mak @@ -57,6 +57,7 @@ CONFIG_XICS=3D$(CONFIG_PSERIES) CONFIG_XICS_SPAPR=3D$(CONFIG_PSERIES) CONFIG_XICS_KVM=3D$(and $(CONFIG_PSERIES),$(CONFIG_KVM)) CONFIG_XIVE=3D$(CONFIG_PSERIES) +CONFIG_XIVE_SPAPR=3D$(CONFIG_PSERIES) # For PReP CONFIG_SERIAL_ISA=3Dy CONFIG_MC146818RTC=3Dy diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs index 28b83456bfcc..31b4fae2d1a8 100644 --- a/hw/intc/Makefile.objs +++ b/hw/intc/Makefile.objs @@ -36,6 +36,7 @@ obj-$(CONFIG_XICS) +=3D xics.o obj-$(CONFIG_XICS_SPAPR) +=3D xics_spapr.o obj-$(CONFIG_XICS_KVM) +=3D xics_kvm.o obj-$(CONFIG_XIVE) +=3D xive.o +obj-$(CONFIG_XIVE_SPAPR) +=3D xive_spapr.o obj-$(CONFIG_POWERNV) +=3D xics_pnv.o obj-$(CONFIG_ALLWINNER_A10_PIC) +=3D allwinner-a10-pic.o obj-$(CONFIG_S390_FLIC) +=3D s390_flic.o diff --git a/hw/intc/xive_spapr.c b/hw/intc/xive_spapr.c new file mode 100644 index 000000000000..b634d1f28f10 --- /dev/null +++ b/hw/intc/xive_spapr.c @@ -0,0 +1,745 @@ +/* + * QEMU PowerPC XIVE model for pSeries + * + * Copyright (c) 2017, IBM Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "cpu.h" +#include "hw/ppc/spapr.h" +#include "hw/ppc/xive.h" +#include "hw/ppc/fdt.h" +#include "monitor/monitor.h" + +#include "xive-internal.h" + +static XiveICSState *xive_ics_find(sPAPRMachineState *spapr, uint32_t lisn) +{ + XICSFabricClass *xic =3D XICS_FABRIC_GET_CLASS(spapr); + ICSState *ics =3D xic->ics_get(XICS_FABRIC(spapr), lisn); + + return ICS_XIVE(ics); +} + +static bool priority_is_valid(int priority) +{ + return priority >=3D 0 && priority < 8; +} + +/* + * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical + * real address of the MMIO page through which the Event State Buffer + * entry associated with the value of the "lisn" parameter is managed. + * + * Parameters: + * Input + * - "flags" + * Bits 0-63 reserved + * - "lisn" is per "interrupts", "interrupt-map", or + * "ibm,xive-lisn-ranges" properties, or as returned by the + * ibm,query-interrupt-source-number RTAS call, or as returned + * by the H_ALLOCATE_VAS_WINDOW hcall + * + * Output + * - R4: "flags" + * Bits 0-59: Reserved + * Bit 60: H_INT_ESB must be used for Event State Buffer + * management + * Bit 61: 1 =3D=3D LSI 0 =3D=3D MSI + * Bit 62: the full function page supports trigger + * Bit 63: Store EOI Supported + * - R5: Logical Real address of full function Event State Buffer + * management page, -1 if ESB hcall flag is set to 1. + * - R6: Logical Real Address of trigger only Event State Buffer + * management page or -1. + * - R7: Power of 2 page size for the ESB management pages returned in + * R5 and R6. + */ +static target_ulong h_int_get_source_info(PowerPCCPU *cpu, + sPAPRMachineState *spapr, + target_ulong opcode, + target_ulong *args) +{ + target_ulong flags =3D args[0]; + target_ulong lisn =3D args[1]; + XiveICSState *xs; + uint32_t srcno; + uint64_t mmio_base; + ICSIRQState *irq; + + if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { + return H_FUNCTION; + } + + if (flags) { + return H_PARAMETER; + } + + xs =3D xive_ics_find(spapr, lisn); + if (!xs) { + return H_P2; + } + + srcno =3D lisn - ICS_BASE(xs)->offset; + mmio_base =3D (uint64_t)xs->esb_base + (1ull << xs->esb_shift) * srcno; + irq =3D &ICS_BASE(xs)->irqs[srcno]; + + args[0] =3D 0; + if (irq->flags & XICS_FLAGS_IRQ_LSI) { + args[0] |=3D XIVE_SRC_LSI; + } + if (xs->flags & XIVE_SRC_TRIGGER) { + args[0] |=3D XIVE_SRC_TRIGGER; + } + + /* never used in QEMU */ + if (xs->flags & XIVE_SRC_H_INT_ESB) { + args[1] =3D -1; + } else { + args[1] =3D mmio_base; + if (xs->flags & XIVE_SRC_TRIGGER) { + args[2] =3D -1; /* No specific trigger page */ + } else { + args[2] =3D -1; /* TODO: support for specific trigger page */ + } + } + + args[3] =3D xs->esb_shift; + + return H_SUCCESS; +} + +/* + * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical + * Interrupt Source to a target. The Logical Interrupt Source is + * designated with the "lisn" parameter and the target is designated + * with the "target" and "priority" parameters. Upon return from the + * hcall(), no additional interrupts will be directed to the old EQ. + * The old EQ should be investigated for interrupts that occurred + * prior to or during the hcall(). + * + * Parameters: + * Input: + * - "flags" + * Bits 0-61: Reserved + * Bit 62: set the "eisn" in the EA + * Bit 63: masks the interrupt source in the hardware interrupt + * control structure. An interrupt masked by this mechanism will + * be dropped, but it's source state bits will still be + * set. There is no race-free way of unmasking and restoring the + * source. Thus this should only be used in interrupts that are + * also masked at the source, and only in cases where the + * interrupt is not meant to be used for a large amount of time + * because no valid target exists for it for example + * - "lisn" is per "interrupts", "interrupt-map", or + * "ibm,xive-lisn-ranges" properties, or as returned by the + * ibm,query-interrupt-source-number RTAS call, or as returned by + * the H_ALLOCATE_VAS_WINDOW hcall + * - "target" is per "ibm,ppc-interrupt-server#s" or + * "ibm,ppc-interrupt-gserver#s" + * - "priority" is a valid priority not in + * "ibm,plat-res-int-priorities" + * - "eisn" is the guest EISN associated with the "lisn" + * + * Output: + * - None + */ + +#define XIVE_SRC_SET_EISN (1ull << (63 - 62)) +#define XIVE_SRC_MASK (1ull << (63 - 63)) + +static target_ulong h_int_set_source_config(PowerPCCPU *cpu, + sPAPRMachineState *spapr, + target_ulong opcode, + target_ulong *args) +{ + XiveIVE *ive; + uint64_t new_ive; + target_ulong flags =3D args[0]; + target_ulong lisn =3D args[1]; + target_ulong target =3D args[2]; + target_ulong priority =3D args[3]; + target_ulong eisn =3D args[4]; + uint32_t eq_idx; + + if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { + return H_FUNCTION; + } + + if (flags & ~(XIVE_SRC_SET_EISN | XIVE_SRC_MASK)) { + return H_PARAMETER; + } + + ive =3D xive_get_ive(spapr->xive, lisn); + if (!ive || !(ive->w & IVE_VALID)) { + return H_P2; + } + new_ive =3D ive->w; + + /* Let's handle 0xff priority as if the interrupt was masked */ + if (priority =3D=3D 0xff || (flags & XIVE_SRC_MASK)) { + new_ive |=3D IVE_MASKED; + priority =3D 7; + } else { + new_ive =3D ive->w & ~IVE_MASKED; + } + + if (!priority_is_valid(priority)) { + return H_P4; + } + + /* First find the EQ corresponding to the target */ + if (!xive_eq_for_target(spapr->xive, target, priority, &eq_idx)) { + return H_P3; + } + + /* And update */ + new_ive =3D SETFIELD(IVE_EQ_BLOCK, new_ive, 0ul); + new_ive =3D SETFIELD(IVE_EQ_INDEX, new_ive, eq_idx); + + if (flags & XIVE_SRC_SET_EISN) { + new_ive =3D SETFIELD(IVE_EQ_DATA, new_ive, eisn); + } + + ive->w =3D new_ive; + + return H_SUCCESS; +} + +/* + * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which + * target/priority pair is assigned to the specified Logical Interrupt + * Source. + * + * Parameters: + * Input: + * - "flags" + * Bits 0-63 Reserved + * - "lisn" is per "interrupts", "interrupt-map", or + * "ibm,xive-lisn-ranges" properties, or as returned by the + * ibm,query-interrupt-source-number RTAS call, or as + * returned by the H_ALLOCATE_VAS_WINDOW hcall + * + * Output: + * - R4: Target to which the specified Logical Interrupt Source is + * assigned + * - R5: Priority to which the specified Logical Interrupt Source is + * assigned + */ +static target_ulong h_int_get_source_config(PowerPCCPU *cpu, + sPAPRMachineState *spapr, + target_ulong opcode, + target_ulong *args) +{ + target_ulong flags =3D args[0]; + target_ulong lisn =3D args[1]; + XiveIVE *ive; + XiveEQ *eq; + uint32_t eq_idx; + + if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { + return H_FUNCTION; + } + + if (flags) { + return H_PARAMETER; + } + + ive =3D xive_get_ive(spapr->xive, lisn); + if (!ive || !(ive->w & IVE_VALID)) { + return H_P2; + } + + eq_idx =3D GETFIELD(IVE_EQ_INDEX, ive->w); + eq =3D xive_get_eq(spapr->xive, eq_idx); + if (!eq) { + return H_P2; + } + + if (ive->w & IVE_MASKED) { + args[1] =3D 0xff; + } else { + args[1] =3D GETFIELD(EQ_W7_F0_PRIORITY, eq->w7); + } + + args[0] =3D GETFIELD(EQ_W6_NVT_INDEX, eq->w6); + + return H_SUCCESS; +} + +/* + * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real + * address of the notification management page associated with the + * specified target and priority. + * + * Parameters: + * Input: + * - "flags" + * Bits 0-63 Reserved + * - "target" is per "ibm,ppc-interrupt-server#s" or + * "ibm,ppc-interrupt-gserver#s" + * - "priority" is a valid priority not in + * "ibm,plat-res-int-priorities" + * + * Output: + * - R4: Logical real address of notification page + * - R5: Power of 2 page size of the notification page + */ +static target_ulong h_int_get_queue_info(PowerPCCPU *cpu, + sPAPRMachineState *spapr, + target_ulong opcode, + target_ulong *args) +{ + target_ulong flags =3D args[0]; + target_ulong target =3D args[1]; + target_ulong priority =3D args[2]; + uint32_t eq_idx; + XiveEQ *eq; + + if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { + return H_FUNCTION; + } + + if (flags) { + return H_PARAMETER; + } + + if (!priority_is_valid(priority)) { + return H_P3; + } + + if (!xive_eq_for_target(spapr->xive, target, priority, &eq_idx)) { + return H_P2; + } + + eq =3D xive_get_eq(spapr->xive, eq_idx); + if (!eq) { + return H_PARAMETER; + } + + args[0] =3D -1; /* TODO: return ESn page */ + if (eq->w0 & EQ_W0_ENQUEUE) { + args[1] =3D GETFIELD(EQ_W0_QSIZE, eq->w0) + 12; + } else { + args[1] =3D 0; + } + + return H_SUCCESS; +} + +/* + * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for + * a given "target" and "priority". It is also used to set the + * notification config associated with the EQ. An EQ size of 0 is + * used to reset the EQ config for a given target and priority. If + * resetting the EQ config, the END associated with the given "target" + * and "priority" will be changed to disable queueing. + * + * Upon return from the hcall(), no additional interrupts will be + * directed to the old EQ (if one was set). The old EQ (if one was + * set) should be investigated for interrupts that occurred prior to + * or during the hcall(). + * + * Parameters: + * Input: + * - "flags" + * Bits 0-62: Reserved + * Bit 63: Unconditional Notify (n) per the XIVE spec + * - "target" is per "ibm,ppc-interrupt-server#s" or + * "ibm,ppc-interrupt-gserver#s" + * - "priority" is a valid priority not in + * "ibm,plat-res-int-priorities" + * - "eventQueue": The logical real address of the start of the EQ + * - "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes" + * + * Output: + * - None + */ + +#define XIVE_EQ_ALWAYS_NOTIFY (1ull << (63 - 63)) + +static target_ulong h_int_set_queue_config(PowerPCCPU *cpu, + sPAPRMachineState *spapr, + target_ulong opcode, + target_ulong *args) +{ + target_ulong flags =3D args[0]; + target_ulong target =3D args[1]; + target_ulong priority =3D args[2]; + target_ulong qpage =3D args[3]; + target_ulong qsize =3D args[4]; + uint32_t eq_idx; + XiveEQ *old_eq; + XiveEQ eq; + uint32_t qdata; + + if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { + return H_FUNCTION; + } + + if (flags & ~XIVE_EQ_ALWAYS_NOTIFY) { + return H_PARAMETER; + } + + if (!priority_is_valid(priority)) { + return H_P3; + } + + if (!xive_eq_for_target(spapr->xive, target, priority, &eq_idx)) { + return H_P2; + } + + old_eq =3D xive_get_eq(spapr->xive, eq_idx); + if (!old_eq) { + return H_HARDWARE; + } + + eq =3D *old_eq; + + /* Let's validate the EQ address with a read of first EQ entry */ + if (address_space_read(&address_space_memory, qpage, MEMTXATTRS_UNSPEC= IFIED, + (uint8_t *) &qdata, sizeof(qdata))) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to read EQ data @0x%" + HWADDR_PRIx "\n", __func__, qpage); + return H_P4; + } + + switch (qsize) { + case 12: + case 16: + case 21: + case 24: + eq.w3 =3D ((uint64_t)qpage) & 0xffffffff; + eq.w2 =3D (((uint64_t)qpage)) >> 32 & 0x0fffffff; + eq.w0 |=3D EQ_W0_ENQUEUE; + eq.w0 =3D SETFIELD(EQ_W0_QSIZE, eq.w0, qsize - 12); + break; + case 0: + eq.w2 =3D eq.w3 =3D 0; + eq.w0 &=3D ~EQ_W0_ENQUEUE; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid EQ size %"PRIx64"\n", + __func__, qsize); + return H_P5; + } + + /* Ensure the priority and target are correctly set (they will not + * be right after allocation + */ + eq.w6 =3D SETFIELD(EQ_W6_NVT_BLOCK, 0ul, 0ul) | + SETFIELD(EQ_W6_NVT_INDEX, 0ul, target); + eq.w7 =3D SETFIELD(EQ_W7_F0_PRIORITY, 0ul, priority); + + /* TODO: depends on notitification page (ESn) from H_INT_GET_QUEUE_INF= O */ + if (flags & XIVE_EQ_ALWAYS_NOTIFY) { + eq.w0 |=3D EQ_W0_UCOND_NOTIFY; + } + + eq.w1 =3D EQ_W1_GENERATION | SETFIELD(EQ_W1_PAGE_OFF, 0ul, 0ul); + eq.w0 |=3D EQ_W0_VALID; + + /* Update EQ */ + *old_eq =3D eq; + + return H_SUCCESS; +} + +/* + * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given + * target and priority. + * + * Parameters: + * Input: + * - "flags" + * Bits 0-63: Reserved + * - "target" is per "ibm,ppc-interrupt-server#s" or + * "ibm,ppc-interrupt-gserver#s" + * - "priority" is a valid priority not in + * "ibm,plat-res-int-priorities" + * + * Output: + * - R4: "flags": + * Bits 0-62: Reserved + * Bit 63: The value of Unconditional Notify (n) per the XIVE spec * + * - R5: The logical real address of the start of the EQ + * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes" + */ +static target_ulong h_int_get_queue_config(PowerPCCPU *cpu, + sPAPRMachineState *spapr, + target_ulong opcode, + target_ulong *args) +{ + target_ulong flags =3D args[0]; + target_ulong target =3D args[1]; + target_ulong priority =3D args[2]; + uint32_t eq_idx; + XiveEQ *eq; + + if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { + return H_FUNCTION; + } + + if (flags) { + return H_PARAMETER; + } + + if (!priority_is_valid(priority)) { + return H_P3; + } + + if (!xive_eq_for_target(spapr->xive, target, priority, &eq_idx)) { + return H_P2; + } + + eq =3D xive_get_eq(spapr->xive, eq_idx); + if (!eq) { + return H_HARDWARE; + } + + if (eq->w0 & EQ_W0_UCOND_NOTIFY) { + args[0] =3D XIVE_EQ_ALWAYS_NOTIFY; + } else { + args[0] =3D 0; + } + + if (eq->w0 & EQ_W0_ENQUEUE) { + args[1] =3D + (((uint64_t)(eq->w2 & 0x0fffffff)) << 32) | eq->w3; + args[2] =3D GETFIELD(EQ_W0_QSIZE, eq->w0) + 12; + } else { + args[1] =3D 0; + args[2] =3D 0; + } + + return H_SUCCESS; +} + +/* + * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the + * reporting cache line pair for the input "target". The reporting + * cache lines will contain the OS interrupt context when the OS + * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS + * interrupt. The reporting cache lines can be reset by inputting -1 + * in "reportingLine". Issuing the CI store byte without reporting + * cache lines registered will result in the data not being accessible + * to the OS. + * + * Parameters: + * Input: + * - "flags" + * Bits 0-63: Reserved + * - "target" is per "ibm,ppc-interrupt-server#s" or + * "ibm,ppc-interrupt-gserver#s" + * - "reportingLine": The logical real address of the reporting cache + * line pair + * + * Output: + * - None + */ +static target_ulong h_int_set_os_reporting_line(PowerPCCPU *cpu, + sPAPRMachineState *spapr, + target_ulong opcode, + target_ulong *args) +{ + if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { + return H_FUNCTION; + } + + /* TODO: H_INT_SET_OS_REPORTING_LINE */ + return H_FUNCTION; +} + +/* + * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical + * real address of the reporting cache line pair set for the input + * "target". If no reporting cache line pair has been set, -1 is + * returned. + * + * Parameters: + * Input: + * - "flags" + * Bits 0-63: Reserved + * - "target" is per "ibm,ppc-interrupt-server#s" or + * "ibm,ppc-interrupt-gserver#s" + * - "reportingLine": The logical real address of the reporting cache + * line pair + * + * Output: + * - R4: The logical real address of the reporting line if set, else -1 + */ +static target_ulong h_int_get_os_reporting_line(PowerPCCPU *cpu, + sPAPRMachineState *spapr, + target_ulong opcode, + target_ulong *args) +{ + if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { + return H_FUNCTION; + } + + /* TODO: H_INT_GET_OS_REPORTING_LINE */ + return H_FUNCTION; +} + +/* + * The H_INT_ESB hcall() is used to issue a load or store to the ESB + * page for the input "lisn". This hcall is only supported for LISNs + * that have the ESB hcall flag set to 1 when returned from hcall() + * H_INT_GET_SOURCE_INFO. + * + * Parameters: + * Input: + * - "flags" + * Bits 0-62: Reserved + * bit 63: Store: Store=3D1, store operation, else load operation + * - "lisn" is per "interrupts", "interrupt-map", or + * "ibm,xive-lisn-ranges" properties, or as returned by the + * ibm,query-interrupt-source-number RTAS call, or as + * returned by the H_ALLOCATE_VAS_WINDOW hcall + * - "esbOffset" is the offset into the ESB page for the load or store ope= ration + * - "storeData" is the data to write for a store operation + * + * Output: + * - R4: R4: The value of the load if load operation, else -1 + */ + +#define XIVE_ESB_STORE (1ull << (63 - 63)) + +static target_ulong h_int_esb(PowerPCCPU *cpu, + sPAPRMachineState *spapr, + target_ulong opcode, + target_ulong *args) +{ + target_ulong flags =3D args[0]; + target_ulong lisn =3D args[1]; + target_ulong offset =3D args[2]; + target_ulong data =3D args[3]; + XiveICSState *xs; + uint32_t srcno; + uint64_t esb_base; + + if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { + return H_FUNCTION; + } + + if (flags & ~XIVE_ESB_STORE) { + return H_PARAMETER; + } + + xs =3D xive_ics_find(spapr, lisn); + if (!xs) { + return H_P2; + } + + if (offset > (1ull << xs->esb_shift)) { + return H_P3; + } + + srcno =3D lisn - ICS_BASE(xs)->offset; + esb_base =3D (uint64_t)xs->esb_base + (1ull << xs->esb_shift) * srcno; + esb_base +=3D offset; + + if (dma_memory_rw(&address_space_memory, esb_base, &data, 8, + (flags & XIVE_ESB_STORE))) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to rw data @0x%" + HWADDR_PRIx "\n", __func__, esb_base); + return H_HARDWARE; + } + args[0] =3D (flags & XIVE_ESB_STORE) ? -1 : data; + return H_SUCCESS; +} + +/* + * The H_INT_SYNC hcall() is used to issue syncs. Is this IPI sync + * and HW sync? Need the OS teams to let us know what syncs need to + * be provided. + * + * Parameters: + * Input: + * - "flags" + * Bits 0-63: Reserved + * + * Output: + * - None + */ +static target_ulong h_int_sync(PowerPCCPU *cpu, + sPAPRMachineState *spapr, + target_ulong opcode, + target_ulong *args) +{ + target_ulong flags =3D args[0]; + + if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { + return H_FUNCTION; + } + + if (flags) { + return H_PARAMETER; + } + + /* TODO: H_INT_SYNC, I have no idea what needs to be done */ + return H_FUNCTION; +} + +/* + * The H_INT_RESET hcall() is used to reset all of the partition's + * interrupt exploitation structures to their initial state. This + * means losing all previously set interrupt state set via + * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG. + * + * Parameters: + * Input: + * - "flags" + * Bits 0-63: Reserved + * + * Output: + * - None + */ +static target_ulong h_int_reset(PowerPCCPU *cpu, + sPAPRMachineState *spapr, + target_ulong opcode, + target_ulong *args) +{ + target_ulong flags =3D args[0]; + + if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { + return H_FUNCTION; + } + + if (flags) { + return H_PARAMETER; + } + + xive_reset(spapr->xive); + return H_SUCCESS; +} + +void xive_spapr_init(sPAPRMachineState *spapr) +{ + spapr_register_hypercall(H_INT_GET_SOURCE_INFO, h_int_get_source_info); + spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG, h_int_set_source_con= fig); + spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG, h_int_get_source_con= fig); + spapr_register_hypercall(H_INT_GET_QUEUE_INFO, h_int_get_queue_info); + spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG, h_int_set_queue_confi= g); + spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG, h_int_get_queue_confi= g); + spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE, + h_int_set_os_reporting_line); + spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE, + h_int_get_os_reporting_line); + spapr_register_hypercall(H_INT_ESB, h_int_esb); + spapr_register_hypercall(H_INT_SYNC, h_int_sync); + spapr_register_hypercall(H_INT_RESET, h_int_reset); +} diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index a66bbac35242..dd69c084baa6 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -13,6 +13,7 @@ struct sPAPRPHBState; struct sPAPRNVRAM; typedef struct sPAPREventLogEntry sPAPREventLogEntry; typedef struct sPAPREventSource sPAPREventSource; +typedef struct XIVE XIVE; =20 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL #define SPAPR_ENTRY_POINT 0x100 @@ -115,6 +116,7 @@ struct sPAPRMachineState { MemoryHotplugState hotplug_memory; =20 const char *icp_type; + XIVE *xive; }; =20 #define H_SUCCESS 0 @@ -371,7 +373,20 @@ struct sPAPRMachineState { #define H_INVALIDATE_PID 0x378 #define H_REGISTER_PROC_TBL 0x37C #define H_SIGNAL_SYS_RESET 0x380 -#define MAX_HCALL_OPCODE H_SIGNAL_SYS_RESET + +#define H_INT_GET_SOURCE_INFO 0x3A8 +#define H_INT_SET_SOURCE_CONFIG 0x3AC +#define H_INT_GET_SOURCE_CONFIG 0x3B0 +#define H_INT_GET_QUEUE_INFO 0x3B4 +#define H_INT_SET_QUEUE_CONFIG 0x3B8 +#define H_INT_GET_QUEUE_CONFIG 0x3BC +#define H_INT_SET_OS_REPORTING_LINE 0x3C0 +#define H_INT_GET_OS_REPORTING_LINE 0x3C4 +#define H_INT_ESB 0x3C8 +#define H_INT_SYNC 0x3CC +#define H_INT_RESET 0x3D0 + +#define MAX_HCALL_OPCODE H_INT_RESET =20 /* The hcalls above are standardized in PAPR and implemented by pHyp * as well. diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index f87df8107dd9..af48d62cc776 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -63,4 +63,8 @@ struct XiveICPState { uint8_t *tima_os; }; =20 +typedef struct sPAPRMachineState sPAPRMachineState; + +void xive_spapr_init(sPAPRMachineState *spapr); + #endif /* PPC_XIVE_H */ --=20 2.7.5 From nobody Wed Nov 5 07:32:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499275559965792.3689436971802; Wed, 5 Jul 2017 10:25:59 -0700 (PDT) Received: from localhost ([::1]:47332 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSo3q-0005XH-NI for importer@patchew.org; Wed, 05 Jul 2017 13:25:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41943) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSnu5-0004ey-Lh for qemu-devel@nongnu.org; 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charset="utf-8" As for XICS, the XIVE interface for the guest is described in the device tree under the interrupt controller node. A couple of new properties are specific to XIVE : - "reg" contains the base address and size of the thread interrupt managnement areas (TIMA) for the user level for the OS level. Only the OS level is taken into account. - "ibm,xive-eq-sizes" the size of the event queues. - "ibm,xive-lisn-ranges" the interrupt numbers ranges assigned to the guest. These are allocated using a simple bitmap. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive_spapr.c | 36 ++++++++++++++++++++++++++++++++++++ include/hw/ppc/xive.h | 1 + 2 files changed, 37 insertions(+) diff --git a/hw/intc/xive_spapr.c b/hw/intc/xive_spapr.c index b634d1f28f10..64282cb4bfab 100644 --- a/hw/intc/xive_spapr.c +++ b/hw/intc/xive_spapr.c @@ -743,3 +743,39 @@ void xive_spapr_init(sPAPRMachineState *spapr) spapr_register_hypercall(H_INT_SYNC, h_int_sync); spapr_register_hypercall(H_INT_RESET, h_int_reset); } + +void xive_spapr_populate(XIVE *x, void *fdt) +{ + int node; + uint64_t timas[2 * 2]; + uint32_t lisn_ranges[] =3D { + cpu_to_be32(x->int_ipi_top - x->int_base - x->nr_targets), /* sta= rt */ + cpu_to_be32(x->nr_targets), /* count */ + }; + uint32_t eq_sizes[] =3D { + cpu_to_be32(12), /* 4K */ + cpu_to_be32(16), /* 64K */ + cpu_to_be32(21), /* 2M */ + cpu_to_be32(24), /* 16M */ + }; + int i; + + /* Thread Interrupt Management Areas : User and OS */ + for (i =3D 0; i < 2; i++) { + timas[i * 2] =3D cpu_to_be64(x->tm_base + i * (1 << x->tm_shift)); + timas[i * 2 + 1] =3D cpu_to_be64(1 << x->tm_shift); + } + + _FDT(node =3D fdt_add_subnode(fdt, 0, "interrupt-controller")); + + _FDT(fdt_setprop_string(fdt, node, "name", "interrupt-controller")); + _FDT(fdt_setprop_string(fdt, node, "device_type", "power-ivpe")); + _FDT(fdt_setprop(fdt, node, "reg", timas, sizeof(timas))); + + _FDT(fdt_setprop_string(fdt, node, "compatible", "ibm,power-ivpe")); + _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2)); + _FDT(fdt_setprop(fdt, node, "ibm,xive-eq-sizes", eq_sizes, + sizeof(eq_sizes))); + _FDT(fdt_setprop(fdt, node, "ibm,xive-lisn-ranges", lisn_ranges, + sizeof(lisn_ranges))); +} diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index af48d62cc776..288116aeb8f4 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -66,5 +66,6 @@ struct XiveICPState { typedef struct sPAPRMachineState sPAPRMachineState; =20 void xive_spapr_init(sPAPRMachineState *spapr); +void xive_spapr_populate(XIVE *x, void *fdt); =20 #endif /* PPC_XIVE_H */ --=20 2.7.5 From nobody Wed Nov 5 07:32:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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Wed, 05 Jul 2017 13:15:55 -0400 Received: from player158.ha.ovh.net (b6.ovh.net [213.186.33.56]) by mo3.mail-out.ovh.net (Postfix) with ESMTP id 74150FCD3B for ; Wed, 5 Jul 2017 19:15:54 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10652-153.w90-89.abo.wanadoo.fr [90.89.238.153]) (Authenticated sender: clg@kaod.org) by player158.ha.ovh.net (Postfix) with ESMTPSA id 4A8FA62006C; Wed, 5 Jul 2017 19:15:48 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 5 Jul 2017 19:13:32 +0200 Message-Id: <1499274819-15607-20-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.5 In-Reply-To: <1499274819-15607-1-git-send-email-clg@kaod.org> References: <1499274819-15607-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2218585766631214054 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelkedrudeigdduuddtucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 178.33.47.94 Subject: [Qemu-devel] [RFC PATCH 19/26] ppc/xive: introduce a helper to map the XIVE memory regions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Alexander Graf , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" It will be used when the guest chooses the XIVE exploitation mode in CAS. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 11 +++++++++++ include/hw/ppc/xive.h | 2 ++ 2 files changed, 13 insertions(+) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index cda1fa18e44d..895dd2b2f61b 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -915,3 +915,14 @@ bool xive_eq_for_target(XIVE *x, uint32_t target, uint= 8_t priority, =20 return true; } + +void xive_mmio_map(XIVE *x) +{ + /* ESBs */ + sysbus_mmio_map(SYS_BUS_DEVICE(x), 0, x->vc_base); + + /* Thread Management Interrupt Areas */ + /* TODO: Only map the OS TIMA for the moment. Mapping the whole + * region needs some rework in the handlers */ + sysbus_mmio_map(SYS_BUS_DEVICE(x), 1, x->tm_base + (1 << x->tm_shift)); +} diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 288116aeb8f4..560f6ab66f73 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -68,4 +68,6 @@ typedef struct sPAPRMachineState sPAPRMachineState; void xive_spapr_init(sPAPRMachineState *spapr); void xive_spapr_populate(XIVE *x, void *fdt); =20 +void xive_mmio_map(XIVE *x); + #endif /* PPC_XIVE_H */ --=20 2.7.5 From nobody Wed Nov 5 07:32:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499276143906433.7115715720606; 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Wed, 5 Jul 2017 19:15:54 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 5 Jul 2017 19:13:33 +0200 Message-Id: <1499274819-15607-21-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.5 In-Reply-To: <1499274819-15607-1-git-send-email-clg@kaod.org> References: <1499274819-15607-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2220274619180944358 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelkedrudeigdduuddtucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 188.165.43.173 Subject: [Qemu-devel] [RFC PATCH 20/26] ppc/xive: introduce a helper to create XIVE interrupt source objects X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Alexander Graf , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 21 +++++++++++++++++++++ include/hw/ppc/xive.h | 4 ++++ 2 files changed, 25 insertions(+) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 895dd2b2f61b..bec123649ebd 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -726,6 +726,27 @@ static const TypeInfo xive_ics_info =3D { .class_init =3D xive_ics_class_init, }; =20 +void xive_ics_create(XiveICSState *xs, XIVE *x, uint32_t offset, + uint32_t nr_irqs, uint32_t shift, + uint32_t flags, Error **errp) +{ + Error *error =3D NULL; + + object_property_add_const_link(OBJECT(xs), "xive", OBJECT(x), + &error_fatal); + object_property_add_const_link(OBJECT(xs), "xics", + OBJECT(qdev_get_machine()), &error_fata= l); + object_property_set_int(OBJECT(xs), shift, "shift", &error_fatal); + object_property_set_int(OBJECT(xs), flags, "flags", &error_fatal); + object_property_set_int(OBJECT(xs), offset, "irq-base", &error_fatal); + object_property_set_int(OBJECT(xs), nr_irqs, "nr-irqs", &error_fatal); + object_property_set_bool(OBJECT(xs), true, "realized", &error); + if (error) { + error_propagate(errp, error); + return; + } +} + /* * Main XIVE object */ diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 560f6ab66f73..a1c7797658ba 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -70,4 +70,8 @@ void xive_spapr_populate(XIVE *x, void *fdt); =20 void xive_mmio_map(XIVE *x); =20 +void xive_ics_create(XiveICSState *xs, XIVE *x, uint32_t offset, + uint32_t nr_irqs, uint32_t shift, uint32_t flags, + Error **errp); + #endif /* PPC_XIVE_H */ --=20 2.7.5 From nobody Wed Nov 5 07:32:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499276215647850.9367957850117; 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Wed, 5 Jul 2017 19:16:00 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 5 Jul 2017 19:13:34 +0200 Message-Id: <1499274819-15607-22-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.5 In-Reply-To: <1499274819-15607-1-git-send-email-clg@kaod.org> References: <1499274819-15607-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2221963468931173350 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelkedrudeigdduuddtucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 87.98.184.158 Subject: [Qemu-devel] [RFC PATCH 21/26] ppc/xive: introduce routines to allocate IRQ numbers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Alexander Graf , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The IRQ number allocator is inspired by OPAL which allocates IPI IRQ numbers from the bottom of the IRQ number space and allocates the HW IRQ numbers from the top. So, this might be slightly overkill for our need. Needs to be discussed. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/ppc/xive.h | 1 + 2 files changed, 54 insertions(+) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index bec123649ebd..42eefbe7fd65 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -748,6 +748,59 @@ void xive_ics_create(XiveICSState *xs, XIVE *x, uint32= _t offset, } =20 /* + * IRQ number allocators + */ +uint32_t xive_alloc_hw_irqs(XIVE *x, uint32_t count, uint32_t align) +{ + uint32_t base; + int i; + + base =3D x->int_hw_bot - count; + base &=3D ~(align - 1); + if (base < x->int_ipi_top) { + qemu_log_mask(LOG_GUEST_ERROR, + "XIVE: HW alloc request for %d interrupts " + "aligned to %d failed\n", + count, align); + return -1; + } + + x->int_hw_bot =3D base; + + for (i =3D 0; i < count; i++) { + XiveIVE *ive =3D xive_get_ive(x, base + i); + + ive->w =3D IVE_VALID | IVE_MASKED; + } + return base; +} + +static uint32_t xive_alloc_ipi_irqs(XIVE *x, uint32_t count, uint32_t alig= n) +{ + uint32_t base; + int i; + + base =3D x->int_ipi_top + (align - 1); + base &=3D ~(align - 1); + if (base >=3D x->int_hw_bot) { + qemu_log_mask(LOG_GUEST_ERROR, + "IPI alloc request for %d interrupts aligned to %d " + "failed\n", + count, align); + return -1; + } + + x->int_ipi_top =3D base + count; + + for (i =3D 0; i < count; i++) { + XiveIVE *ive =3D xive_get_ive(x, base + i); + + ive->w =3D IVE_VALID | IVE_MASKED; + } + return base; +} + +/* * Main XIVE object */ =20 diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index a1c7797658ba..3c1cd96ea4d0 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -69,6 +69,7 @@ void xive_spapr_init(sPAPRMachineState *spapr); void xive_spapr_populate(XIVE *x, void *fdt); =20 void xive_mmio_map(XIVE *x); +uint32_t xive_alloc_hw_irqs(XIVE *x, uint32_t count, uint32_t align); =20 void xive_ics_create(XiveICSState *xs, XIVE *x, uint32_t offset, uint32_t nr_irqs, uint32_t shift, uint32_t flags, --=20 2.7.5 From nobody Wed Nov 5 07:32:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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Wed, 05 Jul 2017 13:16:14 -0400 Received: from player158.ha.ovh.net (b6.ovh.net [213.186.33.56]) by mo3.mail-out.ovh.net (Postfix) with ESMTP id F1ACAFCD9C for ; Wed, 5 Jul 2017 19:16:12 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10652-153.w90-89.abo.wanadoo.fr [90.89.238.153]) (Authenticated sender: clg@kaod.org) by player158.ha.ovh.net (Postfix) with ESMTPSA id C66D862007E; Wed, 5 Jul 2017 19:16:06 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 5 Jul 2017 19:13:35 +0200 Message-Id: <1499274819-15607-23-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.5 In-Reply-To: <1499274819-15607-1-git-send-email-clg@kaod.org> References: <1499274819-15607-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2223652316227013606 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelkedrudeigdduuddtucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 87.98.150.177 Subject: [Qemu-devel] [RFC PATCH 22/26] ppc/xive: create an XIVE interrupt source to handle IPIs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Alexander Graf , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Isolate the IPIs in their own interrupt source. This is not strictly needed for sPAPR, but it might useful for PowerNV. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive-internal.h | 2 ++ hw/intc/xive.c | 24 +++++++++++++++++++++++- 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/hw/intc/xive-internal.h b/hw/intc/xive-internal.h index 5e8b78a1ea6a..f37e07f00038 100644 --- a/hw/intc/xive-internal.h +++ b/hw/intc/xive-internal.h @@ -204,6 +204,8 @@ struct XIVE { uint32_t tm_shift; hwaddr tm_base; MemoryRegion tm_iomem; + + XiveICSState ipi_xs; }; =20 void xive_reset(void *dev); diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 42eefbe7fd65..257b324e1d32 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -821,6 +821,9 @@ static uint32_t xive_alloc_ipi_irqs(XIVE *x, uint32_t c= ount, uint32_t align) #define TM_SHIFT 16 #define TM_BAR_SIZE (XIVE_TM_RING_COUNT * (1 << TM_SHIFT)) =20 +/* One 64k page. OPAL has two */ +#define IPI_ESB_SHIFT (16) + static uint64_t xive_esb_default_read(void *p, hwaddr offset, unsigned siz= e) { qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n", @@ -863,12 +866,18 @@ void xive_reset(void *dev) =20 static void xive_init(Object *obj) { - ; + XIVE *x =3D XIVE(obj); + + object_initialize(&x->ipi_xs, sizeof(x->ipi_xs), TYPE_ICS_XIVE); + object_property_add_child(obj, "ipis", OBJECT(&x->ipi_xs), NULL); } =20 static void xive_realize(DeviceState *dev, Error **errp) { + Error *error =3D NULL; XIVE *x =3D XIVE(dev); + uint32_t ipi_base; + int i; =20 if (!x->nr_targets) { error_setg(errp, "Number of interrupt targets needs to be greater = 0"); @@ -917,6 +926,19 @@ static void xive_realize(DeviceState *dev, Error **err= p) "xive.tm", TM_BAR_SIZE); sysbus_init_mmio(SYS_BUS_DEVICE(dev), &x->tm_iomem); =20 + /* IPI source */ + ipi_base =3D xive_alloc_ipi_irqs(x, x->nr_targets, 1); + + xive_ics_create(&x->ipi_xs, x, ipi_base, x->nr_targets, + IPI_ESB_SHIFT, XIVE_SRC_TRIGGER, &error); + if (error) { + error_propagate(errp, error); + return; + } + + for (i =3D 0; i < ICS_BASE(&x->ipi_xs)->nr_irqs; i++) { + ics_set_irq_type(ICS_BASE(&x->ipi_xs), i, false); + } qemu_register_reset(xive_reset, dev); } =20 --=20 2.7.5 From nobody Wed Nov 5 07:32:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499276284726683.9466358961388; Wed, 5 Jul 2017 10:38:04 -0700 (PDT) Received: from localhost ([::1]:47398 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSoFW-0007Yl-5Y for importer@patchew.org; Wed, 05 Jul 2017 13:38:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42260) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSnua-00056K-Ee for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:16:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dSnuW-0004JQ-E4 for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:16:24 -0400 Received: from 5.mo3.mail-out.ovh.net ([87.98.178.36]:59183) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dSnuW-0004IQ-7P for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:16:20 -0400 Received: from player158.ha.ovh.net (b6.ovh.net [213.186.33.56]) by mo3.mail-out.ovh.net (Postfix) with ESMTP id 26EEAFCE22 for ; Wed, 5 Jul 2017 19:16:19 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10652-153.w90-89.abo.wanadoo.fr [90.89.238.153]) (Authenticated sender: clg@kaod.org) by player158.ha.ovh.net (Postfix) with ESMTPSA id EF9DC62007C; Wed, 5 Jul 2017 19:16:12 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 5 Jul 2017 19:13:36 +0200 Message-Id: <1499274819-15607-24-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.5 In-Reply-To: <1499274819-15607-1-git-send-email-clg@kaod.org> References: <1499274819-15607-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2225622641534602214 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelkedrudeigdduuddtucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 87.98.178.36 Subject: [Qemu-devel] [RFC PATCH 23/26] spapr: add a XIVE object to the sPAPR machine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Alexander Graf , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Let's create the XIVE object whether it used or not by the machine. CAS will decide which model will be used for the interrupt controller. Signed-off-by: C=C3=A9dric Le Goater --- hw/ppc/spapr.c | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 0256e7a537bf..45527b4c5eca 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -54,6 +54,7 @@ #include "hw/ppc/spapr_vio.h" #include "hw/pci-host/spapr.h" #include "hw/ppc/xics.h" +#include "hw/ppc/xive.h" #include "hw/pci/msi.h" =20 #include "hw/pci/pci.h" @@ -204,6 +205,38 @@ static void xics_system_init(MachineState *machine, in= t nr_irqs, Error **errp) } } =20 +static XIVE *spapr_xive_create(sPAPRMachineState *spapr, int nr_servers, + Error **errp) +{ + Error *local_err =3D NULL; + Object *obj; + + /* TODO: We don't have KVM support yet so check irqchip=3Doff here */ + if (kvm_enabled() && machine_kernel_irqchip_required(MACHINE(spapr))) { + error_prepend(errp, "kernel_irqchip requested but unavailable"); + return NULL; + } + + obj =3D object_new(TYPE_XIVE); + object_property_add_child(OBJECT(spapr), "xive", obj, &error_abort); + object_property_set_int(obj, nr_servers, "nr-targets", &local_err); + if (local_err) { + goto error; + } + object_property_set_bool(obj, true, "realized", &local_err); + if (local_err) { + goto error; + } + + /* Install hcalls */ + xive_spapr_init(spapr); + + return XIVE(obj); +error: + error_propagate(errp, local_err); + return NULL; +} + static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, int smt_threads) { @@ -2192,6 +2225,14 @@ static void ppc_spapr_init(MachineState *machine) /* Set up Interrupt Controller before we create the VCPUs */ xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal); =20 + /* Set up XIVE. CAS will choose whether the guest runs in XICS + * (legacy mode) or XIVE Exploitation mode + * + * TODO: if XIVE creation fails, force the use of XICS legacy + */ + spapr->xive =3D spapr_xive_create(spapr, xics_max_server_number(), + &error_fatal); + /* Set up containers for ibm,client-set-architecture negotiated option= s */ spapr->ov5 =3D spapr_ovec_new(); spapr->ov5_cas =3D spapr_ovec_new(); --=20 2.7.5 From nobody Wed Nov 5 07:32:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499276353947358.7387582269423; Wed, 5 Jul 2017 10:39:13 -0700 (PDT) Received: from localhost ([::1]:47401 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSoGc-0008CP-VH for importer@patchew.org; Wed, 05 Jul 2017 13:39:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42337) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSnug-0005Co-Rx for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:16:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dSnuc-0004Og-Or for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:16:30 -0400 Received: from 2.mo3.mail-out.ovh.net ([46.105.75.36]:34496) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dSnuc-0004NT-GJ for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:16:26 -0400 Received: from player158.ha.ovh.net (b6.ovh.net [213.186.33.56]) by mo3.mail-out.ovh.net (Postfix) with ESMTP id 50A4AFCD9C for ; Wed, 5 Jul 2017 19:16:25 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10652-153.w90-89.abo.wanadoo.fr [90.89.238.153]) (Authenticated sender: clg@kaod.org) by player158.ha.ovh.net (Postfix) with ESMTPSA id 247BE62007C; Wed, 5 Jul 2017 19:16:19 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 5 Jul 2017 19:13:37 +0200 Message-Id: <1499274819-15607-25-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.5 In-Reply-To: <1499274819-15607-1-git-send-email-clg@kaod.org> References: <1499274819-15607-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2227311491243150310 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelkedrudeigdduuddtucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.75.36 Subject: [Qemu-devel] [RFC PATCH 24/26] spapr: include the XIVE interrupt source for IPIs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Alexander Graf , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive_spapr.c | 10 ++++++++++ hw/ppc/spapr.c | 11 ++++++++++- include/hw/ppc/xive.h | 1 + 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/hw/intc/xive_spapr.c b/hw/intc/xive_spapr.c index 64282cb4bfab..eb8a5c081e51 100644 --- a/hw/intc/xive_spapr.c +++ b/hw/intc/xive_spapr.c @@ -26,6 +26,16 @@ =20 #include "xive-internal.h" =20 +/* + * Used by the XICSFabric ics_get handler in sPAPR + */ +ICSState *xive_ics_get(XIVE *x, uint32_t lisn) +{ + ICSState *ics =3D ICS_BASE(&x->ipi_xs); + + return ics_valid_irq(ics, lisn) ? ics : NULL; +} + static XiveICSState *xive_ics_find(sPAPRMachineState *spapr, uint32_t lisn) { XICSFabricClass *xic =3D XICS_FABRIC_GET_CLASS(spapr); diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 45527b4c5eca..816661f4c9ad 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -3361,7 +3361,16 @@ static ICSState *spapr_ics_get(XICSFabric *dev, int = irq) { sPAPRMachineState *spapr =3D SPAPR_MACHINE(dev); =20 - return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; + if (ics_valid_irq(spapr->ics, irq)) { + return spapr->ics; + } + + /* If needed, check the XIVE IPI source also */ + if (spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { + return xive_ics_get(spapr->xive, irq); + } + + return NULL; } =20 static void spapr_ics_resend(XICSFabric *dev) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 3c1cd96ea4d0..dc5309264422 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -74,5 +74,6 @@ uint32_t xive_alloc_hw_irqs(XIVE *x, uint32_t count, uint= 32_t align); void xive_ics_create(XiveICSState *xs, XIVE *x, uint32_t offset, uint32_t nr_irqs, uint32_t shift, uint32_t flags, Error **errp); +ICSState *xive_ics_get(XIVE *x, uint32_t lisn); =20 #endif /* PPC_XIVE_H */ --=20 2.7.5 From nobody Wed Nov 5 07:32:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499276485202464.08891851236297; Wed, 5 Jul 2017 10:41:25 -0700 (PDT) Received: from localhost ([::1]:47413 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSoIi-0002DF-P9 for importer@patchew.org; Wed, 05 Jul 2017 13:41:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42430) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSnum-0005HH-N0 for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:16:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dSnui-0004US-NE for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:16:36 -0400 Received: from 20.mo3.mail-out.ovh.net ([178.33.47.94]:41814) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dSnui-0004Td-Gs for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:16:32 -0400 Received: from player158.ha.ovh.net (b6.ovh.net [213.186.33.56]) by mo3.mail-out.ovh.net (Postfix) with ESMTP id 77FCEFCDB3 for ; Wed, 5 Jul 2017 19:16:31 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10652-153.w90-89.abo.wanadoo.fr [90.89.238.153]) (Authenticated sender: clg@kaod.org) by player158.ha.ovh.net (Postfix) with ESMTPSA id 4E5F962007C; Wed, 5 Jul 2017 19:16:25 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 5 Jul 2017 19:13:38 +0200 Message-Id: <1499274819-15607-26-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.5 In-Reply-To: <1499274819-15607-1-git-send-email-clg@kaod.org> References: <1499274819-15607-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2229000344041065446 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelkedrudeigdduuddtucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 178.33.47.94 Subject: [Qemu-devel] [RFC PATCH 25/26] spapr: print the XIVE interrupt source for IPIs in the monitor X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Alexander Graf , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive_spapr.c | 5 +++++ hw/ppc/spapr.c | 4 ++++ include/hw/ppc/xive.h | 1 + 3 files changed, 10 insertions(+) diff --git a/hw/intc/xive_spapr.c b/hw/intc/xive_spapr.c index eb8a5c081e51..4f689f8b97c0 100644 --- a/hw/intc/xive_spapr.c +++ b/hw/intc/xive_spapr.c @@ -36,6 +36,11 @@ ICSState *xive_ics_get(XIVE *x, uint32_t lisn) return ics_valid_irq(ics, lisn) ? ics : NULL; } =20 +void xive_ics_pic_print_info(XIVE *x, Monitor *mon) +{ + ics_pic_print_info(ICS_BASE(&x->ipi_xs), mon); +} + static XiveICSState *xive_ics_find(sPAPRMachineState *spapr, uint32_t lisn) { XICSFabricClass *xic =3D XICS_FABRIC_GET_CLASS(spapr); diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 816661f4c9ad..ca3a6bc2ea16 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -3399,6 +3399,10 @@ static void spapr_pic_print_info(InterruptStatsProvi= der *obj, icp_pic_print_info(ICP(cpu->intc), mon); } =20 + if (spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { + xive_ics_pic_print_info(spapr->xive, mon); + } + ics_pic_print_info(spapr->ics, mon); } =20 diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index dc5309264422..ee9b32d8c884 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -75,5 +75,6 @@ void xive_ics_create(XiveICSState *xs, XIVE *x, uint32_t = offset, uint32_t nr_irqs, uint32_t shift, uint32_t flags, Error **errp); ICSState *xive_ics_get(XIVE *x, uint32_t lisn); +void xive_ics_pic_print_info(XIVE *x, Monitor *mon); =20 #endif /* PPC_XIVE_H */ --=20 2.7.5 From nobody Wed Nov 5 07:32:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499275897562629.1674216482521; Wed, 5 Jul 2017 10:31:37 -0700 (PDT) Received: from localhost ([::1]:47367 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSo9H-0002Oo-5z for importer@patchew.org; Wed, 05 Jul 2017 13:31:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42493) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSnut-0005Mu-6D for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:16:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dSnup-0004aR-1a for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:16:43 -0400 Received: from 10.mo3.mail-out.ovh.net ([87.98.165.232]:46710) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dSnuo-0004ZB-QR for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:16:38 -0400 Received: from player158.ha.ovh.net (b6.ovh.net [213.186.33.56]) by mo3.mail-out.ovh.net (Postfix) with ESMTP id A14CBFCE2E for ; Wed, 5 Jul 2017 19:16:37 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10652-153.w90-89.abo.wanadoo.fr [90.89.238.153]) (Authenticated sender: clg@kaod.org) by player158.ha.ovh.net (Postfix) with ESMTPSA id 782D362007D; Wed, 5 Jul 2017 19:16:31 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 5 Jul 2017 19:13:39 +0200 Message-Id: <1499274819-15607-27-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.5 In-Reply-To: <1499274819-15607-1-git-send-email-clg@kaod.org> References: <1499274819-15607-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2230689192301399014 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelkedrudeigdduuddtucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 87.98.165.232 Subject: [Qemu-devel] [RFC PATCH 26/26] spapr: force XIVE exploitation mode for POWER9 (HACK) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Alexander Graf , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The CAS negotiation process determines the interrupt controller model to use in the guest but currently, the sPAPR machine make uses of the controller very early in the initialization sequence. The interrupt source is used to allocate IRQ numbers and populate the device tree and the interrupt presenter objects are created along with the CPU. One solution would be use a bitmap to allocate these IRQ numbers and then instantiate the interrupt source object of the correct type with the bitmap as a constructor parameter. As for the interrupt presenter objects, we could allocated them later in the boot process. May be on demand, when a CPU is first notified. Signed-off-by: C=C3=A9dric Le Goater --- hw/ppc/spapr.c | 62 ++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 62 insertions(+) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index ca3a6bc2ea16..623fc776c886 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -237,6 +237,38 @@ error: return NULL; } =20 +static XiveICSState *spapr_xive_ics_create(XIVE *x, int nr_irqs, Error **e= rrp) +{ + Error *local_err =3D NULL; + int irq_base; + Object *obj; + + /* + * TODO: use an XICS_IRQ_BASE alignment to be in sync with XICS + * irq numbers. we should probably simplify the XIVE model or use + * a common allocator. a bitmap maybe ? + */ + irq_base =3D xive_alloc_hw_irqs(x, nr_irqs, XICS_IRQ_BASE); + if (irq_base < 0) { + error_setg(errp, "Failed to allocate %d irqs", nr_irqs); + return NULL; + } + + obj =3D object_new(TYPE_ICS_XIVE); + object_property_add_child(OBJECT(x), "hw", obj, NULL); + + xive_ics_create(ICS_XIVE(obj), x, irq_base, nr_irqs, 16 /* 64KB page *= /, + XIVE_SRC_TRIGGER, &local_err); + if (local_err) { + goto error; + } + return ICS_XIVE(obj); + +error: + error_propagate(errp, local_err); + return NULL; +} + static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, int smt_threads) { @@ -814,6 +846,11 @@ static int spapr_dt_cas_updates(sPAPRMachineState *spa= pr, void *fdt, /* /interrupt controller */ if (!spapr_ovec_test(ov5_updates, OV5_XIVE_EXPLOIT)) { spapr_dt_xics(xics_max_server_number(), fdt, PHANDLE_XICP); + } else { + xive_spapr_populate(spapr->xive, fdt); + + /* Install XIVE MMIOs */ + xive_mmio_map(spapr->xive); } =20 offset =3D fdt_path_offset(fdt, "/chosen"); @@ -963,6 +1000,13 @@ static void spapr_dt_ov5_platform_support(void *fdt, = int chosen) } else { val[3] =3D 0x00; /* Hash */ } + + /* TODO: introduce a kvmppc_has_cap_xive() ? Works with + * irqchip=3Doff for now + */ + if (first_ppc_cpu->env.excp_model & POWERPC_EXCP_POWER9) { + val[1] =3D 0x01; + } } else { if (first_ppc_cpu->env.mmu_model & POWERPC_MMU_V3) { /* V3 MMU supports both hash and radix (with dynamic switching= ) */ @@ -971,6 +1015,9 @@ static void spapr_dt_ov5_platform_support(void *fdt, i= nt chosen) /* Otherwise we can only do hash */ val[3] =3D 0x00; } + if (first_ppc_cpu->env.excp_model & POWERPC_EXCP_POWER9) { + val[1] =3D 0x01; + } } _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", val, sizeof(val))); @@ -2237,6 +2284,21 @@ static void ppc_spapr_init(MachineState *machine) spapr->ov5 =3D spapr_ovec_new(); spapr->ov5_cas =3D spapr_ovec_new(); =20 + /* TODO: force XIVE mode by default on POWER9. + * + * Switching from XICS to XIVE is badly broken. The ICP type is + * incorrect and the ICS is needed before the CAS negotiation to + * allocate irq numbers ... + */ + if (strstr(machine->cpu_model, "POWER9") || + !strcmp(machine->cpu_model, "host")) { + spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); + + spapr->icp_type =3D TYPE_XIVE_ICP; + spapr->ics =3D ICS_BASE( + spapr_xive_ics_create(spapr->xive, XICS_IRQS_SPAPR, &error_fat= al)); + } + if (smc->dr_lmb_enabled) { spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); spapr_validate_node_memory(machine, &error_fatal); --=20 2.7.5