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X-Received-From: 2a00:1450:400c:c09::243 Subject: [Qemu-devel] [PULL 41/42] target/i386: add the tcg_enabled() in target/i386/ X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yang Zhong Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yang Zhong Add the tcg_enabled() where the x86 target needs to disable TCG-specific code. Signed-off-by: Yang Zhong Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 4 +++- target/i386/cpu.h | 8 +++++++- target/i386/helper.c | 2 +- target/i386/machine.c | 10 +++++----- 4 files changed, 16 insertions(+), 8 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 642519a..c571772 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4040,8 +4040,10 @@ static void x86_cpu_common_class_init(ObjectClass *o= c, void *data) cc->class_by_name =3D x86_cpu_class_by_name; cc->parse_features =3D x86_cpu_parse_featurestr; cc->has_work =3D x86_cpu_has_work; +#ifdef CONFIG_TCG cc->do_interrupt =3D x86_cpu_do_interrupt; cc->cpu_exec_interrupt =3D x86_cpu_exec_interrupt; +#endif cc->dump_state =3D x86_cpu_dump_state; cc->get_crash_info =3D x86_cpu_get_crash_info; cc->set_pc =3D x86_cpu_set_pc; @@ -4070,7 +4072,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->gdb_core_xml_file =3D "i386-32bit.xml"; cc->gdb_num_core_regs =3D 41; #endif -#ifndef CONFIG_USER_ONLY +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) cc->debug_excp_handler =3D breakpoint_handler; #endif cc->cpu_exec_enter =3D x86_cpu_exec_enter; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 3495a91..7a228af 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -52,7 +52,9 @@ =20 #include "exec/cpu-defs.h" =20 +#ifdef CONFIG_TCG #include "fpu/softfloat.h" +#endif =20 #define R_EAX 0 #define R_ECX 1 @@ -1597,7 +1599,11 @@ uint32_t cpu_cc_compute_all(CPUX86State *env1, int o= p); =20 static inline uint32_t cpu_compute_eflags(CPUX86State *env) { - return env->eflags | cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MA= SK); + uint32_t eflags =3D env->eflags; + if (tcg_enabled()) { + eflags |=3D cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK); + } + return eflags; } =20 /* NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS diff --git a/target/i386/helper.c b/target/i386/helper.c index bcf9b22..f63eb3d 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -990,7 +990,7 @@ void cpu_report_tpr_access(CPUX86State *env, TPRAccess = access) env->tpr_access_type =3D access; =20 cpu_interrupt(cs, CPU_INTERRUPT_TPR); - } else { + } else if (tcg_enabled()) { cpu_restore_state(cs, cs->mem_io_pc); =20 apic_handle_tpr_access_report(cpu->apic_state, env->eip, access); diff --git a/target/i386/machine.c b/target/i386/machine.c index e0417fe..eab3372 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -281,16 +281,16 @@ static int cpu_post_load(void *opaque, int version_id) env->fptags[i] =3D (env->fptag_vmstate >> i) & 1; } if (tcg_enabled()) { + target_ulong dr7; update_fp_status(env); update_mxcsr_status(env); - } =20 - cpu_breakpoint_remove_all(cs, BP_CPU); - cpu_watchpoint_remove_all(cs, BP_CPU); - { + cpu_breakpoint_remove_all(cs, BP_CPU); + cpu_watchpoint_remove_all(cs, BP_CPU); + /* Indicate all breakpoints disabled, as they are, then let the helper re-enable them. */ - target_ulong dr7 =3D env->dr[7]; + dr7 =3D env->dr[7]; env->dr[7] =3D dr7 & ~(DR7_GLOBAL_BP_MASK | DR7_LOCAL_BP_MASK); cpu_x86_update_dr7(env, dr7); } --=20 1.8.3.1