From nobody Mon Feb 9 07:05:45 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499077708010802.4264816417162; Mon, 3 Jul 2017 03:28:28 -0700 (PDT) Received: from localhost ([::1]:33896 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dRyag-0005fa-Nx for importer@patchew.org; Mon, 03 Jul 2017 06:28:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58003) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dRyMA-0000M2-CI for qemu-devel@nongnu.org; Mon, 03 Jul 2017 06:13:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dRyM8-0001n0-O6 for qemu-devel@nongnu.org; Mon, 03 Jul 2017 06:13:26 -0400 Received: from mga01.intel.com ([192.55.52.88]:14583) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dRyM8-0001cL-DA for qemu-devel@nongnu.org; Mon, 03 Jul 2017 06:13:24 -0400 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 Jul 2017 03:13:24 -0700 Received: from yangzhon-virtual.bj.intel.com ([10.238.145.52]) by fmsmga005.fm.intel.com with ESMTP; 03 Jul 2017 03:13:22 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,302,1496127600"; d="scan'208";a="121724217" From: Yang Zhong To: pbonzini@redhat.com, rth@twiddle.net, thuth@redhat.com Date: Mon, 3 Jul 2017 18:12:21 +0800 Message-Id: <1499076743-15477-14-git-send-email-yang.zhong@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1499076743-15477-1-git-send-email-yang.zhong@intel.com> References: <1499076743-15477-1-git-send-email-yang.zhong@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.88 Subject: [Qemu-devel] [PATCH v2 13/15] tcg: add the CONFIG_TCG for header X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: yang.zhong@intel.com, anthony.xu@intel.com, qemu-devel@nongnu.org, a.rigo@virtualopensystems.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add the CONFIG_TCG for exec-all.h. Since function tlb_set_page_with_attrs() is defined in ./accel/tcg/cputlb.c, which will be disabled if tcg is disabl= ed. This function need be implemented in accel/stubs/tcg-stub.c for disable-tcg. Signed-off-by: Yang Zhong --- accel/stubs/tcg-stub.c | 6 +++++ include/exec/cputlb.h | 2 +- include/exec/exec-all.h | 53 ++++++++++++++++++++++++-----------------= ---- include/exec/helper-proto.h | 2 ++ 4 files changed, 37 insertions(+), 26 deletions(-) diff --git a/accel/stubs/tcg-stub.c b/accel/stubs/tcg-stub.c index a84a6e6..4e9f7fa 100644 --- a/accel/stubs/tcg-stub.c +++ b/accel/stubs/tcg-stub.c @@ -64,6 +64,12 @@ bool cpu_restore_state(CPUState *cpu, uintptr_t searched= _pc) return false; } =20 +void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, + hwaddr paddr, MemTxAttrs attrs, + int prot, int mmu_idx, target_ulong size) +{ +} + void dump_exec_info(FILE *f, fprintf_function cpu_fprintf) { } diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index 3f94178..cf296d9 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -19,7 +19,7 @@ #ifndef CPUTLB_H #define CPUTLB_H =20 -#if !defined(CONFIG_USER_ONLY) +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) /* cputlb.c */ void tlb_protect_code(ram_addr_t ram_addr); void tlb_unprotect_code(ram_addr_t ram_addr); diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 724ec73..446c924 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -82,6 +82,34 @@ void cpu_reloading_memory_map(void); * Note that with KVM only one address space is supported. */ void cpu_address_space_init(CPUState *cpu, AddressSpace *as, int asidx); +/** + * tlb_set_page_with_attrs: + * @cpu: CPU to add this TLB entry for + * @vaddr: virtual address of page to add entry for + * @paddr: physical address of the page + * @attrs: memory transaction attributes + * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits) + * @mmu_idx: MMU index to insert TLB entry for + * @size: size of the page in bytes + * + * Add an entry to this CPU's TLB (a mapping from virtual address + * @vaddr to physical address @paddr) with the specified memory + * transaction attributes. This is generally called by the target CPU + * specific code after it has been called through the tlb_fill() + * entry point and performed a successful page table walk to find + * the physical address and attributes for the virtual address + * which provoked the TLB miss. + * + * At most one entry for a given virtual address is permitted. Only a + * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only + * used by tlb_flush_page. + */ +void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, + hwaddr paddr, MemTxAttrs attrs, + int prot, int mmu_idx, target_ulong size); +#endif + +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) /* cputlb.c */ /** * tlb_flush_page: @@ -205,31 +233,6 @@ void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint1= 6_t idxmap); * depend on when the guests translation ends the TB. */ void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap); -/** - * tlb_set_page_with_attrs: - * @cpu: CPU to add this TLB entry for - * @vaddr: virtual address of page to add entry for - * @paddr: physical address of the page - * @attrs: memory transaction attributes - * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits) - * @mmu_idx: MMU index to insert TLB entry for - * @size: size of the page in bytes - * - * Add an entry to this CPU's TLB (a mapping from virtual address - * @vaddr to physical address @paddr) with the specified memory - * transaction attributes. This is generally called by the target CPU - * specific code after it has been called through the tlb_fill() - * entry point and performed a successful page table walk to find - * the physical address and attributes for the virtual address - * which provoked the TLB miss. - * - * At most one entry for a given virtual address is permitted. Only a - * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only - * used by tlb_flush_page. - */ -void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, - hwaddr paddr, MemTxAttrs attrs, - int prot, int mmu_idx, target_ulong size); /* tlb_set_page: * * This function is equivalent to calling tlb_set_page_with_attrs() diff --git a/include/exec/helper-proto.h b/include/exec/helper-proto.h index 954bef8..417c7b0 100644 --- a/include/exec/helper-proto.h +++ b/include/exec/helper-proto.h @@ -28,7 +28,9 @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), d= h_ctype(t3), \ =20 #include "helper.h" #include "trace/generated-helpers.h" +#ifdef CONFIG_TCG #include "tcg-runtime.h" +#endif =20 #undef DEF_HELPER_FLAGS_0 #undef DEF_HELPER_FLAGS_1 --=20 1.9.1