From nobody Tue May 7 12:40:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499057251601117.70945604097278; Sun, 2 Jul 2017 21:47:31 -0700 (PDT) Received: from localhost ([::1]:60302 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dRtGi-0000TW-BW for importer@patchew.org; Mon, 03 Jul 2017 00:47:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40558) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dRtFC-00080H-90 for qemu-devel@nongnu.org; Mon, 03 Jul 2017 00:45:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dRtF9-0007u1-Ul for qemu-devel@nongnu.org; Mon, 03 Jul 2017 00:45:54 -0400 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:34440) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dRtF9-0007rD-JH; Mon, 03 Jul 2017 00:45:51 -0400 Received: by mail-pg0-x244.google.com with SMTP id j186so21797733pge.1; Sun, 02 Jul 2017 21:45:51 -0700 (PDT) Received: from localhost.localdomain ([124.123.70.3]) by smtp.gmail.com with ESMTPSA id v70sm9324145pfi.110.2017.07.02.21.45.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 02 Jul 2017 21:45:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=k1sr11aDuT6ln5w91bfM1Ke6/QxRnRSPe9we0VZq89Q=; b=ZwAWiiyePd7uUcG3OLPdvgE1kXc26vCe5CcZ5JuoKNdCftSecF7KPjABxSpxop17Jw 0/cXtlbzYrBAjHjZfArUmDI35TIrgXCFJUFxNucOqiKf9VkqOm8jSla/Wl1mZDeOXG9D wYGSb8KqDv5v070uRdgCCo7UkzDhCLV8hvocWkRI+u1/MFW+lKvxod6tMD78VOW9T9Qo 0BH30umz/XB6nzXa8sXi915Ll77sv2MhesNb7cHA5+UTBwrEgA16E3aaErDAMy2Y7UUz B2/dBjXGAaldvWUqJl88DvPD3ZctonWfvA07rupTxSS0rApr2AOcFDFKLAvo8GCt4Df/ KMAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=k1sr11aDuT6ln5w91bfM1Ke6/QxRnRSPe9we0VZq89Q=; b=CJuZyY6ftMdFdDGHt8THhxHJ9uauScZqzvTiorciq39O/ZMZrsolcKqiscMvk03ov1 2/CuFjiafoHUiQCwHV2mQ8lklK8vc4mU+n8wbIYAtDGGNXt9H/+RvCxu4auqeQDgzY5W ViNYxZLio9dnEdWJQOEfsloVNm+cOtgvgpodtUps0xYai0vaf2PacRFPsN4Am3uOic65 jsY+4zssm+mU+6GDYblNz7TNQL0E/eLRRXRA+xlyyOMmkYVtdkEXh+OYqqqqsA7zH1vu ETm9dp9LP8a3Z5SR0BFwSirbeGw2VoHtaNSkOpNqWmx2g2+y1Qhh+IOJB7AkCICa0QIV /XPA== X-Gm-Message-State: AIVw1109+MgbyNrL3KOteongWVO1/oSEQlLoH4V2+CBjmwL4LFSG/+/5 aVNuhwzaaPLUOEIv X-Received: by 10.84.236.71 with SMTP id h7mr8315551pln.88.1499057150310; Sun, 02 Jul 2017 21:45:50 -0700 (PDT) From: Subbaraya Sundeep To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Mon, 3 Jul 2017 10:15:11 +0530 Message-Id: <1499057115-6773-2-git-send-email-sundeep.lkml@gmail.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1499057115-6773-1-git-send-email-sundeep.lkml@gmail.com> References: <1499057115-6773-1-git-send-email-sundeep.lkml@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [Qemu devel v6 PATCH 1/5] msf2: Add Smartfusion2 System timer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Subbaraya Sundeep , f4bug@amsat.org, alistair23@gmail.com, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Modelled System Timer in Microsemi's Smartfusion2 Soc. Timer has two 32bit down counters and two interrupts. Signed-off-by: Subbaraya Sundeep Reviewed-by: Alistair Francis --- hw/timer/Makefile.objs | 1 + hw/timer/mss-timer.c | 261 +++++++++++++++++++++++++++++++++++++++= ++++ include/hw/timer/mss-timer.h | 67 +++++++++++ 3 files changed, 329 insertions(+) create mode 100644 hw/timer/mss-timer.c create mode 100644 include/hw/timer/mss-timer.h diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs index dd6f27e..fc4d2da 100644 --- a/hw/timer/Makefile.objs +++ b/hw/timer/Makefile.objs @@ -41,3 +41,4 @@ common-obj-$(CONFIG_STM32F2XX_TIMER) +=3D stm32f2xx_timer= .o common-obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_timer.o =20 common-obj-$(CONFIG_SUN4V_RTC) +=3D sun4v-rtc.o +common-obj-$(CONFIG_MSF2) +=3D mss-timer.o diff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c new file mode 100644 index 0000000..e46d118 --- /dev/null +++ b/hw/timer/mss-timer.c @@ -0,0 +1,261 @@ +/* + * Block model of System timer present in + * Microsemi's SmartFusion2 and SmartFusion SoCs. + * + * Copyright (c) 2017 Subbaraya Sundeep . + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "hw/timer/mss-timer.h" + +#ifndef MSS_TIMER_ERR_DEBUG +#define MSS_TIMER_ERR_DEBUG 0 +#endif + +#define DB_PRINT_L(lvl, fmt, args...) do { \ + if (MSS_TIMER_ERR_DEBUG >=3D lvl) { \ + qemu_log("%s: " fmt "\n", __func__, ## args); \ + } \ +} while (0); + +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) + +#define R_TIM_VAL 0 +#define R_TIM_LOADVAL 1 +#define R_TIM_BGLOADVAL 2 +#define R_TIM_CTRL 3 +#define R_TIM_RIS 4 +#define R_TIM_MIS 5 + +#define TIMER_CTRL_ENBL (1 << 0) +#define TIMER_CTRL_ONESHOT (1 << 1) +#define TIMER_CTRL_INTR (1 << 2) +#define TIMER_RIS_ACK (1 << 0) +#define TIMER_RST_CLR (1 << 6) +#define TIMER_MODE (1 << 0) + +static void timer_update_irq(struct Msf2Timer *st) +{ + bool isr, ier; + + isr =3D !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK); + ier =3D !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR); + qemu_set_irq(st->irq, (ier && isr)); +} + +static void timer_update(struct Msf2Timer *st) +{ + uint64_t count; + + if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL)) { + ptimer_stop(st->ptimer); + return; + } + + count =3D st->regs[R_TIM_LOADVAL]; + ptimer_set_limit(st->ptimer, count, 1); + ptimer_run(st->ptimer, 1); +} + +static uint64_t +timer_read(void *opaque, hwaddr offset, unsigned int size) +{ + MSSTimerState *t =3D opaque; + hwaddr addr; + struct Msf2Timer *st; + uint32_t ret =3D 0; + int timer =3D 0; + int isr; + int ier; + + addr =3D offset >> 2; + /* + * Two independent timers has same base address. + * Based on address passed figure out which timer is being used. + */ + if ((addr >=3D R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) { + timer =3D 1; + addr -=3D R_TIM1_MAX; + } + + st =3D &t->timers[timer]; + + switch (addr) { + case R_TIM_VAL: + ret =3D ptimer_get_count(st->ptimer); + break; + + case R_TIM_MIS: + isr =3D !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK); + ier =3D !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR); + ret =3D ier & isr; + break; + + default: + if (addr < NUM_TIMERS * R_TIM1_MAX) { + ret =3D st->regs[addr]; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + TYPE_MSS_TIMER": 64-bit mode not supported\n"); + } + break; + } + + DB_PRINT("timer=3D%d 0x%" HWADDR_PRIx "=3D0x%" PRIx32, timer, offset, + ret); + return ret; +} + +static void +timer_write(void *opaque, hwaddr offset, + uint64_t val64, unsigned int size) +{ + MSSTimerState *t =3D opaque; + hwaddr addr; + struct Msf2Timer *st; + int timer =3D 0; + uint32_t value =3D val64; + + addr =3D offset >> 2; + /* + * Two independent timers has same base address. + * Based on addr passed figure out which timer is being used. + */ + if ((addr >=3D R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) { + timer =3D 1; + addr -=3D R_TIM1_MAX; + } + + st =3D &t->timers[timer]; + + DB_PRINT("addr=3D0x%" HWADDR_PRIx " val=3D0x%" PRIx32 " (timer=3D%d)",= offset, + value, timer); + + switch (addr) { + case R_TIM_CTRL: + st->regs[R_TIM_CTRL] =3D value; + timer_update(st); + break; + + case R_TIM_RIS: + if (value & TIMER_RIS_ACK) { + st->regs[R_TIM_RIS] &=3D ~TIMER_RIS_ACK; + } + break; + + case R_TIM_LOADVAL: + st->regs[R_TIM_LOADVAL] =3D value; + if (st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL) { + timer_update(st); + } + break; + + case R_TIM_BGLOADVAL: + st->regs[R_TIM_BGLOADVAL] =3D value; + st->regs[R_TIM_LOADVAL] =3D value; + break; + + case R_TIM_VAL: + case R_TIM_MIS: + break; + + default: + if (addr < NUM_TIMERS * R_TIM1_MAX) { + st->regs[addr] =3D value; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + TYPE_MSS_TIMER": 64-bit mode not supported\n"); + return; + } + break; + } + timer_update_irq(st); +} + +static const MemoryRegionOps timer_ops =3D { + .read =3D timer_read, + .write =3D timer_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4 + } +}; + +static void timer_hit(void *opaque) +{ + struct Msf2Timer *st =3D opaque; + + st->regs[R_TIM_RIS] |=3D TIMER_RIS_ACK; + + if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ONESHOT)) { + timer_update(st); + } + timer_update_irq(st); +} + +static void mss_timer_init(Object *obj) +{ + MSSTimerState *t =3D MSS_TIMER(obj); + int i; + + /* Init all the ptimers. */ + for (i =3D 0; i < NUM_TIMERS; i++) { + struct Msf2Timer *st =3D &t->timers[i]; + + st->bh =3D qemu_bh_new(timer_hit, st); + st->ptimer =3D ptimer_init(st->bh, PTIMER_POLICY_DEFAULT); + ptimer_set_freq(st->ptimer, t->freq_hz); + sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq); + } + + memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, TYPE_MSS_TIM= ER, + NUM_TIMERS * R_TIM1_MAX * 4); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &t->mmio); +} + +static Property mss_timer_properties[] =3D { + /* Libero GUI shows 100Mhz as default for clocks */ + DEFINE_PROP_UINT32("clock-frequency", MSSTimerState, freq_hz, + 100 * 1000000), + DEFINE_PROP_END_OF_LIST(), +}; + +static void mss_timer_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->props =3D mss_timer_properties; +} + +static const TypeInfo mss_timer_info =3D { + .name =3D TYPE_MSS_TIMER, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(MSSTimerState), + .instance_init =3D mss_timer_init, + .class_init =3D mss_timer_class_init, +}; + +static void mss_timer_register_types(void) +{ + type_register_static(&mss_timer_info); +} + +type_init(mss_timer_register_types) diff --git a/include/hw/timer/mss-timer.h b/include/hw/timer/mss-timer.h new file mode 100644 index 0000000..85aed49 --- /dev/null +++ b/include/hw/timer/mss-timer.h @@ -0,0 +1,67 @@ +/* + * Microsemi SmartFusion2 Timer. + * + * Copyright (c) 2017 Subbaraya Sundeep + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef HW_MSS_TIMER_H +#define HW_MSS_TIMER_H + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/ptimer.h" +#include "sysemu/sysemu.h" +#include "qemu/log.h" + +#define TYPE_MSS_TIMER "mss-timer" +#define MSS_TIMER(obj) OBJECT_CHECK(MSSTimerState, \ + (obj), TYPE_MSS_TIMER) + +/* + * There are two 32-bit down counting timers. + * Timers 1 and 2 can be concatenated into a single 64-bit Timer + * that operates either in Periodic mode or in One-shot mode. + * Writing 1 to the TIM64_MODE register bit 0 sets the Timers in 64-bit mo= de. + * In 64-bit mode, writing to the 32-bit registers has no effect. + * Similarly, in 32-bit mode, writing to the 64-bit mode registers + * has no effect. Only two 32-bit timers are supported currently. + */ +#define NUM_TIMERS 2 + +#define R_TIM1_MAX 6 + +struct Msf2Timer { + QEMUBH *bh; + ptimer_state *ptimer; + + uint32_t regs[R_TIM1_MAX]; + qemu_irq irq; +}; + +typedef struct MSSTimerState { + SysBusDevice parent_obj; + + MemoryRegion mmio; + uint32_t freq_hz; + struct Msf2Timer timers[NUM_TIMERS]; +} MSSTimerState; + +#endif /* HW_MSS_TIMER_H */ --=20 2.5.0 From nobody Tue May 7 12:40:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499057258252740.8816567210453; Sun, 2 Jul 2017 21:47:38 -0700 (PDT) Received: from localhost ([::1]:60303 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dRtGq-0000ar-VN for importer@patchew.org; Mon, 03 Jul 2017 00:47:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40585) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dRtFE-00080R-8I for qemu-devel@nongnu.org; Mon, 03 Jul 2017 00:45:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dRtFC-00080N-H4 for qemu-devel@nongnu.org; Mon, 03 Jul 2017 00:45:56 -0400 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:35831) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dRtFC-0007y9-7g; Mon, 03 Jul 2017 00:45:54 -0400 Received: by mail-pg0-x242.google.com with SMTP id d193so3474248pgc.2; Sun, 02 Jul 2017 21:45:54 -0700 (PDT) Received: from localhost.localdomain ([124.123.70.3]) by smtp.gmail.com with ESMTPSA id v70sm9324145pfi.110.2017.07.02.21.45.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 02 Jul 2017 21:45:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=OqXMkBUH52FmNKe5HvzWlGpK1snINHjJqqzB1aL+3YU=; b=lOY9/BtCoSCx/MIqS+y28Q1U9q/D5sG3QNzg7TfRXxbY8qT4piEaiVbId2/meaCdqk Yu+eTaxaFgfiqfoflMg8YZD2DSI7CCjayK/TnoZsVZdM4q3dq1R8G7ca3XzJciqJkGKj KZekSO1P/iBPZCjNh/RI/9MituX8ITR6qnoJCn6/57vVz6Zt9w7W+J+suRR/tbKF+waw Qt2NTBiFQyRfVpa6F++CIeCSd8SNCSkeljLNwNVU6oCVyM8c0EGtLHx+yCHM/2wolHNX +YhfuK/xesBgqfo4X7yTgRE6kAA3V+hqgbIKtPq3wbRsk+w6o5QZgMbMFkUtXAQENvaj DRXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OqXMkBUH52FmNKe5HvzWlGpK1snINHjJqqzB1aL+3YU=; b=QLLl4+rkhV4dtXECUzi9N5ILHNaxZRTeYut/jfYmEyWZP96b8vsg+p59dNxvhAyRj8 cu2If3YK1SR+KUlTBfI+0o+6zSQKv2GfCRbOy6A2jfDIZQo9CvrS7/6dYxWL7KXwgKl1 L76BxTQMQojPsQkR0dkKPcrEqYqCtNQngECpOvoZwBGIfawSbi4oumaMtmTr5uTn4OzK O1r+on+f2JF/phHWoa8hXUJrrVczXyvZFAbBSjU3gF07xwwtIImc1Cs58fOHces/9YX+ gn06y4Xpvc4QjhvjSoiu4cJrb+KXKekCVd2g+B7+sA8RmnxumVBtmamqWFar6zyHuwx7 F1Fw== X-Gm-Message-State: AIVw111XSdwX1pcO0ijyHxkJJckOdW2MLaV9hlLHMwSlbjTXeq5h/x8i xZIxtsJ00NCx+9HG X-Received: by 10.84.232.15 with SMTP id h15mr8560376plk.168.1499057153023; Sun, 02 Jul 2017 21:45:53 -0700 (PDT) From: Subbaraya Sundeep To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Mon, 3 Jul 2017 10:15:12 +0530 Message-Id: <1499057115-6773-3-git-send-email-sundeep.lkml@gmail.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1499057115-6773-1-git-send-email-sundeep.lkml@gmail.com> References: <1499057115-6773-1-git-send-email-sundeep.lkml@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [Qemu devel v6 PATCH 2/5] msf2: Microsemi Smartfusion2 System Register block. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Subbaraya Sundeep , f4bug@amsat.org, alistair23@gmail.com, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Added Sytem register block of Smartfusion2. This block has PLL registers which are accessed by guest. Signed-off-by: Subbaraya Sundeep --- hw/misc/Makefile.objs | 1 + hw/misc/msf2-sysreg.c | 200 ++++++++++++++++++++++++++++++++++++++= ++++ include/hw/misc/msf2-sysreg.h | 82 +++++++++++++++++ 3 files changed, 283 insertions(+) create mode 100644 hw/misc/msf2-sysreg.c create mode 100644 include/hw/misc/msf2-sysreg.h diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index c8b4893..0f52354 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -56,3 +56,4 @@ obj-$(CONFIG_EDU) +=3D edu.o obj-$(CONFIG_HYPERV_TESTDEV) +=3D hyperv_testdev.o obj-$(CONFIG_AUX) +=3D auxbus.o obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_scu.o aspeed_sdmc.o +obj-$(CONFIG_MSF2) +=3D msf2-sysreg.o diff --git a/hw/misc/msf2-sysreg.c b/hw/misc/msf2-sysreg.c new file mode 100644 index 0000000..64ee141 --- /dev/null +++ b/hw/misc/msf2-sysreg.c @@ -0,0 +1,200 @@ +/* + * System Register block model of Microsemi SmartFusion2. + * + * Copyright (c) 2017 Subbaraya Sundeep + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "hw/misc/msf2-sysreg.h" + +#ifndef MSF2_SYSREG_ERR_DEBUG +#define MSF2_SYSREG_ERR_DEBUG 0 +#endif + +#define DB_PRINT_L(lvl, fmt, args...) do { \ + if (MSF2_SYSREG_ERR_DEBUG >=3D lvl) { \ + qemu_log("%s: " fmt "\n", __func__, ## args); \ + } \ +} while (0); + +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) + +static inline int msf2_divbits(uint32_t div) +{ + int ret =3D 0; + + switch (div) { + case 1: + ret =3D 0; + break; + case 2: + ret =3D 1; + break; + case 4: + ret =3D 2; + break; + case 8: + ret =3D 4; + break; + case 16: + ret =3D 5; + break; + case 32: + ret =3D 6; + break; + default: + break; + } + + return ret; +} + +static void msf2_sysreg_reset(DeviceState *d) +{ + MSF2SysregState *s =3D MSF2_SYSREG(d); + + DB_PRINT("RESET"); + + s->regs[MSSDDR_PLL_STATUS_LOW_CR] =3D 0x021A2358; + s->regs[MSSDDR_PLL_STATUS] =3D 0x3; + s->regs[MSSDDR_FACC1_CR] =3D msf2_divbits(s->apb0div) << 5 | + msf2_divbits(s->apb1div) << 2; +} + +static uint64_t msf2_sysreg_read(void *opaque, hwaddr offset, + unsigned size) +{ + MSF2SysregState *s =3D opaque; + offset /=3D 4; + uint32_t ret =3D 0; + + if (offset < ARRAY_SIZE(s->regs)) { + ret =3D s->regs[offset]; + DB_PRINT("addr: 0x%08" HWADDR_PRIx " data: 0x%08" PRIx32, + offset * 4, ret); + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%08" HWADDR_PRIx "\n", __func__, + offset * 4); + } + + return ret; +} + +static void msf2_sysreg_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + MSF2SysregState *s =3D (MSF2SysregState *)opaque; + uint32_t newval =3D val; + uint32_t oldval; + + DB_PRINT("addr: 0x%08" HWADDR_PRIx " data: 0x%08" PRIx64, + offset, val); + + offset /=3D 4; + + switch (offset) { + case MSSDDR_PLL_STATUS: + break; + + case ESRAM_CR: + oldval =3D s->regs[ESRAM_CR]; + if (oldval ^ newval) { + qemu_log_mask(LOG_GUEST_ERROR, + TYPE_MSF2_SYSREG": eSRAM remapping not supported\n"= ); + abort(); + } + break; + + case DDR_CR: + oldval =3D s->regs[DDR_CR]; + if (oldval ^ newval) { + qemu_log_mask(LOG_GUEST_ERROR, + TYPE_MSF2_SYSREG": DDR remapping not supported\n"); + abort(); + } + break; + + case ENVM_REMAP_BASE_CR: + oldval =3D s->regs[ENVM_REMAP_BASE_CR]; + if (oldval ^ newval) { + qemu_log_mask(LOG_GUEST_ERROR, + TYPE_MSF2_SYSREG": eNVM remapping not supported\n"); + abort(); + } + break; + + default: + if (offset < ARRAY_SIZE(s->regs)) { + s->regs[offset] =3D val; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%08" HWADDR_PRIx "\n", __func__, + offset * 4); + } + break; + } +} + +static const MemoryRegionOps sysreg_ops =3D { + .read =3D msf2_sysreg_read, + .write =3D msf2_sysreg_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; + +static void msf2_sysreg_init(Object *obj) +{ + MSF2SysregState *s =3D MSF2_SYSREG(obj); + + memory_region_init_io(&s->iomem, obj, &sysreg_ops, s, TYPE_MSF2_SYSREG, + MSF2_SYSREG_MMIO_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); +} + +static const VMStateDescription vmstate_msf2_sysreg =3D { + .name =3D TYPE_MSF2_SYSREG, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, MSF2SysregState, MSF2_SYSREG_MMIO_SIZE = / 4), + VMSTATE_END_OF_LIST() + } +}; + +static Property msf2_sysreg_properties[] =3D { + /* default divisors in Libero GUI */ + DEFINE_PROP_UINT32("apb0divisor", MSF2SysregState, apb0div, 2), + DEFINE_PROP_UINT32("apb1divisor", MSF2SysregState, apb1div, 2), + DEFINE_PROP_END_OF_LIST(), +}; + +static void msf2_sysreg_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->vmsd =3D &vmstate_msf2_sysreg; + dc->reset =3D msf2_sysreg_reset; + dc->props =3D msf2_sysreg_properties; +} + +static const TypeInfo msf2_sysreg_info =3D { + .name =3D TYPE_MSF2_SYSREG, + .parent =3D TYPE_SYS_BUS_DEVICE, + .class_init =3D msf2_sysreg_class_init, + .instance_size =3D sizeof(MSF2SysregState), + .instance_init =3D msf2_sysreg_init, +}; + +static void msf2_sysreg_register_types(void) +{ + type_register_static(&msf2_sysreg_info); +} + +type_init(msf2_sysreg_register_types) diff --git a/include/hw/misc/msf2-sysreg.h b/include/hw/misc/msf2-sysreg.h new file mode 100644 index 0000000..5e9ea99 --- /dev/null +++ b/include/hw/misc/msf2-sysreg.h @@ -0,0 +1,82 @@ +/* + * Microsemi SmartFusion2 SYSREG + * + * Copyright (c) 2017 Subbaraya Sundeep + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef HW_MSF2_SYSREG_H +#define HW_MSF2_SYSREG_H + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/hw.h" +#include "sysemu/sysemu.h" +#include "qemu/log.h" + +enum { + ESRAM_CR =3D 0x00 / 4, + ESRAM_MAX_LAT, + DDR_CR, + ENVM_CR, + ENVM_REMAP_BASE_CR, + ENVM_REMAP_FAB_CR, + CC_CR, + CC_REGION_CR, + CC_LOCK_BASE_ADDR_CR, + CC_FLUSH_INDX_CR, + DDRB_BUF_TIMER_CR, + DDRB_NB_ADDR_CR, + DDRB_NB_SIZE_CR, + DDRB_CR, + + SOFT_RESET_CR =3D 0x48 / 4, + M3_CR, + + GPIO_SYSRESET_SEL_CR =3D 0x58 / 4, + + MDDR_CR =3D 0x60 / 4, + + MSSDDR_PLL_STATUS_LOW_CR =3D 0x90 / 4, + MSSDDR_PLL_STATUS_HIGH_CR, + MSSDDR_FACC1_CR, + MSSDDR_FACC2_CR, + + MSSDDR_PLL_STATUS =3D 0x150 / 4, + +}; + +#define MSF2_SYSREG_MMIO_SIZE 0x300 + +#define TYPE_MSF2_SYSREG "msf2-sysreg" +#define MSF2_SYSREG(obj) OBJECT_CHECK(MSF2SysregState, (obj), TYPE_MSF2_S= YSREG) + +typedef struct MSF2SysregState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + + uint32_t apb0div; + uint32_t apb1div; + + uint32_t regs[MSF2_SYSREG_MMIO_SIZE / 4]; +} MSF2SysregState; + +#endif /* HW_MSF2_SYSREG_H */ --=20 2.5.0 From nobody Tue May 7 12:40:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499057370680513.7731900101987; Sun, 2 Jul 2017 21:49:30 -0700 (PDT) Received: from localhost ([::1]:60312 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dRtIf-0002Xz-EE for importer@patchew.org; Mon, 03 Jul 2017 00:49:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40629) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dRtFH-00083d-KP for qemu-devel@nongnu.org; Mon, 03 Jul 2017 00:46:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dRtFF-000883-D7 for qemu-devel@nongnu.org; Mon, 03 Jul 2017 00:45:59 -0400 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:36055) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dRtFF-00085o-4e; Mon, 03 Jul 2017 00:45:57 -0400 Received: by mail-pg0-x243.google.com with SMTP id u36so21799969pgn.3; Sun, 02 Jul 2017 21:45:56 -0700 (PDT) Received: from localhost.localdomain ([124.123.70.3]) by smtp.gmail.com with ESMTPSA id v70sm9324145pfi.110.2017.07.02.21.45.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 02 Jul 2017 21:45:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vNwKxZqb6gyjmKTXtRvUP+3v/WQcaqzc5M8JHzqyyTQ=; b=k7YHlTpiGB7LZ4GFhNsAiO3E/IPNxZHZcXxX1vfBUslYVPqokyqIEVgtAnJWfKgHZV 2C5r1yxnUGiHp++TSgjJQKKSKUzVd8SmtFsRDBv4mqefKZEDwNj6Erdrpf4GdYPDV8xq UZM6ci8LIcG3SBCTFGfHw0APKUsP6CRZiKKque836rYExXwwPVD4JKR5OdFcnxqF+o2o hZ8AyjfMEU5pCQJmZCjsygaO83DO6FPG+BNAYXkFp5XmguXmU+bxV1HswYAAK4G1I4eo HDPkzL/G9JwiPBlrsi2EQQsS9nBA9KqNu7GOxGIAeiEEOWhDE85pbuoAHCVBlvt6VXzB QQIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vNwKxZqb6gyjmKTXtRvUP+3v/WQcaqzc5M8JHzqyyTQ=; b=Mr3j9dQux1U/Bz3slQzNXUk5ivv02G96cn7yWB77jyGhWlPQuXWBkEE+m24YAWgGwM 821zTukzGS3HeRhnksgGUZRW0b8vUuS1JI314tQwVeLJvCs/lOCzCOZ2Dw1PTp/txpNA +HEj1Xjm4XKFEipBFOxv/GtYbiqEiiVaWC7zsSu3HKNI9pu5VGqZ4PXXS52pHRaDj5MI 4tKeXEFGRuCofzS5AoFL8pDWRhrchDt7Cp2k6RZ662JGOBJQFj4o8rONEiUbz729xtT9 XChcriRcUPMoI6V+hj/ebin8+k/EacyrhwcXU6iZWLqj3tQV8+zNgghm8kywrqakbfie SYyg== X-Gm-Message-State: AIVw110OwAKnFdXxUdmzgUrVGlgYtFPqRPPQuE7UiM4NHkJktO9mBaQB w6Q145uQW0OQAHfT X-Received: by 10.84.177.131 with SMTP id x3mr8398101plb.83.1499057155814; Sun, 02 Jul 2017 21:45:55 -0700 (PDT) From: Subbaraya Sundeep To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Mon, 3 Jul 2017 10:15:13 +0530 Message-Id: <1499057115-6773-4-git-send-email-sundeep.lkml@gmail.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1499057115-6773-1-git-send-email-sundeep.lkml@gmail.com> References: <1499057115-6773-1-git-send-email-sundeep.lkml@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [Qemu devel v6 PATCH 3/5] msf2: Add Smartfusion2 SPI controller X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Subbaraya Sundeep , f4bug@amsat.org, alistair23@gmail.com, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Modelled Microsemi's Smartfusion2 SPI controller. Signed-off-by: Subbaraya Sundeep --- hw/ssi/Makefile.objs | 1 + hw/ssi/mss-spi.c | 414 +++++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/ssi/mss-spi.h | 62 +++++++ 3 files changed, 477 insertions(+) create mode 100644 hw/ssi/mss-spi.c create mode 100644 include/hw/ssi/mss-spi.h diff --git a/hw/ssi/Makefile.objs b/hw/ssi/Makefile.objs index 487add2..f5bcc65 100644 --- a/hw/ssi/Makefile.objs +++ b/hw/ssi/Makefile.objs @@ -4,6 +4,7 @@ common-obj-$(CONFIG_XILINX_SPI) +=3D xilinx_spi.o common-obj-$(CONFIG_XILINX_SPIPS) +=3D xilinx_spips.o common-obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_smc.o common-obj-$(CONFIG_STM32F2XX_SPI) +=3D stm32f2xx_spi.o +common-obj-$(CONFIG_MSF2) +=3D mss-spi.o =20 obj-$(CONFIG_OMAP) +=3D omap_spi.o obj-$(CONFIG_IMX) +=3D imx_spi.o diff --git a/hw/ssi/mss-spi.c b/hw/ssi/mss-spi.c new file mode 100644 index 0000000..a572abc --- /dev/null +++ b/hw/ssi/mss-spi.c @@ -0,0 +1,414 @@ +/* + * Block model of SPI controller present in + * Microsemi's SmartFusion2 and SmartFusion SoCs. + * + * Copyright (C) 2017 Subbaraya Sundeep + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "hw/ssi/mss-spi.h" + +#ifndef MSS_SPI_ERR_DEBUG +#define MSS_SPI_ERR_DEBUG 0 +#endif + +#define DB_PRINT_L(lvl, fmt, args...) do { \ + if (MSS_SPI_ERR_DEBUG >=3D lvl) { \ + qemu_log("%s: " fmt "\n", __func__, ## args); \ + } \ +} while (0); + +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) + +#define FIFO_CAPACITY 32 +#define FIFO_CAPACITY 32 + +#define R_SPI_CONTROL 0 +#define R_SPI_DFSIZE 1 +#define R_SPI_STATUS 2 +#define R_SPI_INTCLR 3 +#define R_SPI_RX 4 +#define R_SPI_TX 5 +#define R_SPI_CLKGEN 6 +#define R_SPI_SS 7 +#define R_SPI_MIS 8 +#define R_SPI_RIS 9 + +#define S_TXDONE (1 << 0) +#define S_RXRDY (1 << 1) +#define S_RXCHOVRF (1 << 2) +#define S_RXFIFOFUL (1 << 4) +#define S_RXFIFOFULNXT (1 << 5) +#define S_RXFIFOEMP (1 << 6) +#define S_RXFIFOEMPNXT (1 << 7) +#define S_TXFIFOFUL (1 << 8) +#define S_TXFIFOFULNXT (1 << 9) +#define S_TXFIFOEMP (1 << 10) +#define S_TXFIFOEMPNXT (1 << 11) +#define S_FRAMESTART (1 << 12) +#define S_SSEL (1 << 13) +#define S_ACTIVE (1 << 14) + +#define C_ENABLE (1 << 0) +#define C_MODE (1 << 1) +#define C_INTRXDATA (1 << 4) +#define C_INTTXDATA (1 << 5) +#define C_INTRXOVRFLO (1 << 6) +#define C_SPS (1 << 26) +#define C_BIGFIFO (1 << 29) +#define C_RESET (1 << 31) + +#define FRAMESZ_MASK 0x1F +#define FMCOUNT_MASK 0x00FFFF00 +#define FMCOUNT_SHIFT 8 + +static void txfifo_reset(MSSSpiState *s) +{ + fifo32_reset(&s->tx_fifo); + + s->regs[R_SPI_STATUS] &=3D ~S_TXFIFOFUL; + s->regs[R_SPI_STATUS] |=3D S_TXFIFOEMP; +} + +static void rxfifo_reset(MSSSpiState *s) +{ + fifo32_reset(&s->rx_fifo); + + s->regs[R_SPI_STATUS] &=3D ~S_RXFIFOFUL; + s->regs[R_SPI_STATUS] |=3D S_RXFIFOEMP; +} + +static void set_fifodepth(MSSSpiState *s) +{ + unsigned int size =3D s->regs[R_SPI_DFSIZE] & FRAMESZ_MASK; + + if (size <=3D 8) { + s->fifo_depth =3D 32; + } else if (size <=3D 16) { + s->fifo_depth =3D 16; + } else if (size <=3D 32) { + s->fifo_depth =3D 8; + } else { + s->fifo_depth =3D 4; + } +} + +static void mss_spi_do_reset(MSSSpiState *s) +{ + memset(s->regs, 0, sizeof s->regs); + s->regs[R_SPI_CONTROL] =3D 0x80000102; + s->regs[R_SPI_DFSIZE] =3D 0x4; + s->regs[R_SPI_STATUS] =3D S_SSEL | S_TXFIFOEMP | S_RXFIFOEMP; + s->regs[R_SPI_CLKGEN] =3D 0x7; + s->regs[R_SPI_RIS] =3D 0x0; + + s->fifo_depth =3D 4; + s->frame_count =3D 1; + s->enabled =3D false; + + rxfifo_reset(s); + txfifo_reset(s); +} + +static void update_mis(MSSSpiState *s) +{ + uint32_t reg =3D s->regs[R_SPI_CONTROL]; + uint32_t tmp; + + /* + * form the Control register interrupt enable bits + * same as RIS, MIS and Interrupt clear registers for simplicity + */ + tmp =3D ((reg & C_INTRXOVRFLO) >> 4) | ((reg & C_INTRXDATA) >> 3) | + ((reg & C_INTTXDATA) >> 5); + s->regs[R_SPI_MIS] |=3D tmp & s->regs[R_SPI_RIS]; +} + +static void spi_update_irq(MSSSpiState *s) +{ + int irq; + + update_mis(s); + irq =3D !!(s->regs[R_SPI_MIS]); + + qemu_set_irq(s->irq, irq); +} + +static void mss_spi_reset(DeviceState *d) +{ + mss_spi_do_reset(MSS_SPI(d)); +} + +static uint64_t +spi_read(void *opaque, hwaddr addr, unsigned int size) +{ + MSSSpiState *s =3D opaque; + uint32_t ret =3D 0; + + addr >>=3D 2; + switch (addr) { + case R_SPI_RX: + s->regs[R_SPI_STATUS] &=3D ~S_RXFIFOFUL; + s->regs[R_SPI_STATUS] &=3D ~S_RXCHOVRF; + ret =3D fifo32_pop(&s->rx_fifo); + if (fifo32_is_empty(&s->rx_fifo)) { + s->regs[R_SPI_STATUS] |=3D S_RXFIFOEMP; + } + break; + + case R_SPI_MIS: + update_mis(s); + ret =3D s->regs[R_SPI_MIS]; + break; + + default: + if (addr < ARRAY_SIZE(s->regs)) { + ret =3D s->regs[addr]; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, + addr * 4); + } + break; + } + + DB_PRINT("addr=3D0x%" HWADDR_PRIx " =3D 0x%" PRIx32, addr * 4, ret); + spi_update_irq(s); + return ret; +} + +static void assert_cs(MSSSpiState *s) +{ + qemu_set_irq(s->cs_line, 0); +} + +static void deassert_cs(MSSSpiState *s) +{ + qemu_set_irq(s->cs_line, 1); +} + +static void spi_flush_txfifo(MSSSpiState *s) +{ + uint32_t tx; + uint32_t rx; + bool sps =3D !!(s->regs[R_SPI_CONTROL] & C_SPS); + + /* + * Chip Select(CS) is automatically controlled by this controller. + * If SPS bit is set in Control register then CS is asserted + * until all the frames set in frame count of Control register are + * transferred. If SPS is not set then CS pulses between frames. + * Note that Slave Select register specifies which of the CS line + * has to be controlled automatically by controller. Bits SS[7:1] are = for + * masters in FPGA fabric since we model only Microcontroller subsystem + * of Smartfusion2 we control only one CS(SS[0]) line. + */ + while (!fifo32_is_empty(&s->tx_fifo) && s->frame_count) { + assert_cs(s); + + s->regs[R_SPI_STATUS] &=3D ~(S_TXDONE | S_RXRDY); + + tx =3D fifo32_pop(&s->tx_fifo); + DB_PRINT("data tx:0x%" PRIx32, tx); + rx =3D ssi_transfer(s->spi, tx); + DB_PRINT("data rx:0x%" PRIx32, rx); + + if (fifo32_num_used(&s->rx_fifo) =3D=3D s->fifo_depth) { + s->regs[R_SPI_STATUS] |=3D S_RXCHOVRF; + s->regs[R_SPI_RIS] |=3D S_RXCHOVRF; + } else { + fifo32_push(&s->rx_fifo, rx); + s->regs[R_SPI_STATUS] &=3D ~S_RXFIFOEMP; + if (fifo32_num_used(&s->rx_fifo) =3D=3D (s->fifo_depth - 1)) { + s->regs[R_SPI_STATUS] |=3D S_RXFIFOFULNXT; + } + if (fifo32_num_used(&s->rx_fifo) =3D=3D s->fifo_depth) { + s->regs[R_SPI_STATUS] |=3D S_RXFIFOFUL; + } + } + s->frame_count--; + if (!sps) { + deassert_cs(s); + assert_cs(s); + } + } + + if (!sps) { + deassert_cs(s); + } + + if (!s->frame_count) { + s->frame_count =3D (s->regs[R_SPI_CONTROL] & FMCOUNT_MASK) >> + FMCOUNT_SHIFT; + if (sps) { + deassert_cs(s); + } + s->regs[R_SPI_RIS] |=3D S_TXDONE | S_RXRDY; + s->regs[R_SPI_STATUS] |=3D S_TXDONE | S_RXRDY; + } +} + +static void spi_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + MSSSpiState *s =3D opaque; + uint32_t value =3D val64; + + DB_PRINT("addr=3D0x%" HWADDR_PRIx " =3D0x%" PRIx32, addr, value); + addr >>=3D 2; + + switch (addr) { + case R_SPI_TX: + /* adding to already full FIFO */ + if (fifo32_num_used(&s->tx_fifo) =3D=3D s->fifo_depth) { + break; + } + s->regs[R_SPI_STATUS] &=3D ~S_TXFIFOEMP; + fifo32_push(&s->tx_fifo, value); + if (fifo32_num_used(&s->tx_fifo) =3D=3D (s->fifo_depth - 1)) { + s->regs[R_SPI_STATUS] |=3D S_TXFIFOFULNXT; + } + if (fifo32_num_used(&s->tx_fifo) =3D=3D s->fifo_depth) { + s->regs[R_SPI_STATUS] |=3D S_TXFIFOFUL; + } + if (s->enabled) { + spi_flush_txfifo(s); + } + break; + + case R_SPI_CONTROL: + s->regs[R_SPI_CONTROL] =3D value; + if (value & C_BIGFIFO) { + set_fifodepth(s); + } else { + s->fifo_depth =3D 4; + } + s->enabled =3D value & C_ENABLE; + s->frame_count =3D (value & FMCOUNT_MASK) >> FMCOUNT_SHIFT; + if (value & C_RESET) { + mss_spi_do_reset(s); + } + break; + + case R_SPI_DFSIZE: + if (s->enabled) { + break; + } + s->regs[R_SPI_DFSIZE] =3D value; + break; + + case R_SPI_INTCLR: + s->regs[R_SPI_INTCLR] =3D value; + if (value & S_TXDONE) { + s->regs[R_SPI_RIS] &=3D ~S_TXDONE; + } + if (value & S_RXRDY) { + s->regs[R_SPI_RIS] &=3D ~S_RXRDY; + } + if (value & S_RXCHOVRF) { + s->regs[R_SPI_RIS] &=3D ~S_RXCHOVRF; + } + break; + + case R_SPI_MIS: + case R_SPI_STATUS: + case R_SPI_RIS: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Write to read only register 0x%" HWADDR_PRIx= "\n", + __func__, addr * 4); + break; + + default: + if (addr < ARRAY_SIZE(s->regs)) { + s->regs[addr] =3D value; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, + addr * 4); + } + break; + } + + spi_update_irq(s); +} + +static const MemoryRegionOps spi_ops =3D { + .read =3D spi_read, + .write =3D spi_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4 + } +}; + +static void mss_spi_realize(DeviceState *dev, Error **errp) +{ + MSSSpiState *s =3D MSS_SPI(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + + s->spi =3D ssi_create_bus(dev, "spi"); + + sysbus_init_irq(sbd, &s->irq); + ssi_auto_connect_slaves(dev, &s->cs_line, s->spi); + sysbus_init_irq(sbd, &s->cs_line); + + memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s, + TYPE_MSS_SPI, R_SPI_MAX * 4); + sysbus_init_mmio(sbd, &s->mmio); + + fifo32_create(&s->tx_fifo, FIFO_CAPACITY); + fifo32_create(&s->rx_fifo, FIFO_CAPACITY); +} + +static const VMStateDescription vmstate_mss_spi =3D { + .name =3D TYPE_MSS_SPI, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_FIFO32(tx_fifo, MSSSpiState), + VMSTATE_FIFO32(rx_fifo, MSSSpiState), + VMSTATE_UINT32_ARRAY(regs, MSSSpiState, R_SPI_MAX), + VMSTATE_END_OF_LIST() + } +}; + +static void mss_spi_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D mss_spi_realize; + dc->reset =3D mss_spi_reset; + dc->vmsd =3D &vmstate_mss_spi; +} + +static const TypeInfo mss_spi_info =3D { + .name =3D TYPE_MSS_SPI, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(MSSSpiState), + .class_init =3D mss_spi_class_init, +}; + +static void mss_spi_register_types(void) +{ + type_register_static(&mss_spi_info); +} + +type_init(mss_spi_register_types) diff --git a/include/hw/ssi/mss-spi.h b/include/hw/ssi/mss-spi.h new file mode 100644 index 0000000..6c8c0b1 --- /dev/null +++ b/include/hw/ssi/mss-spi.h @@ -0,0 +1,62 @@ +/* + * Microsemi SmartFusion2 SPI + * + * Copyright (c) 2017 Subbaraya Sundeep + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef HW_MSS_SPI_H +#define HW_MSS_SPI_H + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/hw.h" +#include "hw/ssi/ssi.h" +#include "qemu/fifo32.h" +#include "sysemu/sysemu.h" +#include "qemu/log.h" + +#define TYPE_MSS_SPI "mss-spi" +#define MSS_SPI(obj) OBJECT_CHECK(MSSSpiState, (obj), TYPE_MSS_SPI) + +#define R_SPI_MAX 16 + +typedef struct MSSSpiState { + SysBusDevice parent_obj; + + MemoryRegion mmio; + + qemu_irq irq; + + qemu_irq cs_line; + + SSIBus *spi; + + Fifo32 rx_fifo; + Fifo32 tx_fifo; + + int fifo_depth; + uint32_t frame_count; + bool enabled; + + uint32_t regs[R_SPI_MAX]; +} MSSSpiState; + +#endif /* HW_MSS_SPI_H */ --=20 2.5.0 From nobody Tue May 7 12:40:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499057366913178.55169932009994; Sun, 2 Jul 2017 21:49:26 -0700 (PDT) Received: from localhost ([::1]:60311 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dRtIb-0002Vc-Mh for importer@patchew.org; Mon, 03 Jul 2017 00:49:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40657) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dRtFM-00086s-TA for qemu-devel@nongnu.org; Mon, 03 Jul 2017 00:46:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dRtFH-0008Db-TF for qemu-devel@nongnu.org; Mon, 03 Jul 2017 00:46:04 -0400 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:36058) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dRtFH-0008Bd-L0; Mon, 03 Jul 2017 00:45:59 -0400 Received: by mail-pg0-x243.google.com with SMTP id u36so21800042pgn.3; Sun, 02 Jul 2017 21:45:59 -0700 (PDT) Received: from localhost.localdomain ([124.123.70.3]) by smtp.gmail.com with ESMTPSA id v70sm9324145pfi.110.2017.07.02.21.45.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 02 Jul 2017 21:45:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9mPQkmafV4ZWSOs9jkNWltNBNqJR0v6kkmwQzXzFkhA=; b=kWci1uFZ69kN3POazM2PvuDWZQbWBEIUAPjBUEJc8XQ8V++E6lCVzNzmgI5Veh54a5 3ZvgwKgC+TWPs0d2O9PRoDJO1GVo+h0+eGc82roabFijZeMSMWTw1AKQWO/FNRkB8VWp ODlnicUz7hHlUxYpzsYjSV2+5McCkwWdOe6jtUdRQz50bIbcywoUk9E3x8QMyFmZbPuw w2/Nu2terrtoNkKD0EtmTdyHJjxB9z0DLsDgsIkWcJ4HMe5d6b9a1T48LzpEs2U6c0Wu vLPzYA5S2+AEYb77i5omoyht1tyB8x4mum9aaDW9L0ROZU4YcUxbcaOMuNwofxB2ixEi PXQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9mPQkmafV4ZWSOs9jkNWltNBNqJR0v6kkmwQzXzFkhA=; b=oFVzFYSzQlt8HhfZGRQOustGnW9+hUcU581G1xu+RixM1GKNmvAMR1vxsXHfO2Fy1h KxT1yUDF4MCUnYPQhozB1ubJ4Ptfr+kgd3rlemBxlZWoJzE07cbdCD4DO2BMQzGUHrK6 DXlzMLnen9ivWWgiJmnIP7aUYrNlDBDEEVxvLScOeGqwYLkVpkWgGwGxnEXLu1q7yWxk 4ueZKhll5qbgFXwuef0dLjSkn8A1fQSme+qnSt5SMDacKHzpf5eEorqHNRvarldDygb2 TXhopL5eqc51lgo5m3ChNllQIqODF5f87hyXH0h3hoVR1rkG62iNvYIh413M4gmQ4aXa GeeA== X-Gm-Message-State: AIVw113nX0Gh7MKJnk/7wtLDAxX2JoMRjRlxhPl/tOxmuNcGGw8f1PeT 74vp6PaQWUZEnDqE X-Received: by 10.99.116.28 with SMTP id p28mr8362927pgc.262.1499057158476; Sun, 02 Jul 2017 21:45:58 -0700 (PDT) From: Subbaraya Sundeep To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Mon, 3 Jul 2017 10:15:14 +0530 Message-Id: <1499057115-6773-5-git-send-email-sundeep.lkml@gmail.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1499057115-6773-1-git-send-email-sundeep.lkml@gmail.com> References: <1499057115-6773-1-git-send-email-sundeep.lkml@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [Qemu devel v6 PATCH 4/5] msf2: Add Smartfusion2 SoC. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Subbaraya Sundeep , f4bug@amsat.org, alistair23@gmail.com, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Smartfusion2 SoC has hardened Microcontroller subsystem and flash based FPGA fabric. This patch adds support for Microcontroller subsystem in the SoC. Signed-off-by: Subbaraya Sundeep Reviewed-by: Alistair Francis --- default-configs/arm-softmmu.mak | 1 + hw/arm/Makefile.objs | 1 + hw/arm/msf2-soc.c | 216 ++++++++++++++++++++++++++++++++++++= ++++ include/hw/arm/msf2-soc.h | 67 +++++++++++++ 4 files changed, 285 insertions(+) create mode 100644 hw/arm/msf2-soc.c create mode 100644 include/hw/arm/msf2-soc.h diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.= mak index 78d7af0..7062512 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -122,3 +122,4 @@ CONFIG_ACPI=3Dy CONFIG_SMBIOS=3Dy CONFIG_ASPEED_SOC=3Dy CONFIG_GPIO_KEY=3Dy +CONFIG_MSF2=3Dy diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index 4c5c4ee..c828061 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -18,3 +18,4 @@ obj-$(CONFIG_FSL_IMX25) +=3D fsl-imx25.o imx25_pdk.o obj-$(CONFIG_FSL_IMX31) +=3D fsl-imx31.o kzm.o obj-$(CONFIG_FSL_IMX6) +=3D fsl-imx6.o sabrelite.o obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_soc.o aspeed.o +obj-$(CONFIG_MSF2) +=3D msf2-soc.o diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c new file mode 100644 index 0000000..d45827f --- /dev/null +++ b/hw/arm/msf2-soc.c @@ -0,0 +1,216 @@ +/* + * SmartFusion2 SoC emulation. + * + * Copyright (c) 2017 Subbaraya Sundeep + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu-common.h" +#include "hw/arm/arm.h" +#include "exec/address-spaces.h" +#include "hw/char/serial.h" +#include "hw/boards.h" +#include "sysemu/block-backend.h" +#include "hw/arm/msf2-soc.h" + +#define MSF2_TIMER_BASE 0x40004000 +#define MSF2_SYSREG_BASE 0x40038000 + +#define ENVM_BASE_ADDRESS 0x60000000 + +#define SRAM_BASE_ADDRESS 0x20000000 + +#define MSF2_ENVM_SIZE (512 * K_BYTE) +#define MSF2_ESRAM_SIZE (64 * K_BYTE) + +static const uint32_t spi_addr[MSF2_NUM_SPIS] =3D { 0x40001000 , 0x4001100= 0 }; +static const uint32_t uart_addr[MSF2_NUM_UARTS] =3D { 0x40000000 , 0x40010= 000 }; + +static const int spi_irq[MSF2_NUM_SPIS] =3D { 2, 3 }; +static const int uart_irq[MSF2_NUM_UARTS] =3D { 10, 11 }; +static const int timer_irq[MSF2_NUM_TIMERS] =3D { 14, 15 }; + +static void m2sxxx_soc_initfn(Object *obj) +{ + MSF2State *s =3D MSF2_SOC(obj); + int i; + + object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M); + qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default()); + + object_initialize(&s->sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG); + qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default()); + + object_initialize(&s->timer, sizeof(s->timer), TYPE_MSS_TIMER); + qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default()); + + for (i =3D 0; i < MSF2_NUM_SPIS; i++) { + object_initialize(&s->spi[i], sizeof(s->spi[i]), + TYPE_MSS_SPI); + qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); + } +} + +static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp) +{ + MSF2State *s =3D MSF2_SOC(dev_soc); + DeviceState *dev, *armv7m; + SysBusDevice *busdev; + Error *err =3D NULL; + int i; + + MemoryRegion *system_memory =3D get_system_memory(); + MemoryRegion *nvm =3D g_new(MemoryRegion, 1); + MemoryRegion *nvm_alias =3D g_new(MemoryRegion, 1); + MemoryRegion *sram =3D g_new(MemoryRegion, 1); + + memory_region_init_ram(nvm, NULL, "MSF2.eNVM", s->envm_size, + &error_fatal); + + /* + * On power-on, the eNVM region 0x60000000 is automatically + * remapped to the Cortex-M3 processor executable region + * start address (0x0). We do not support remapping other eNVM, + * eSRAM and DDR regions by guest(via Sysreg) currently. + */ + memory_region_init_alias(nvm_alias, NULL, "MSF2.eNVM.alias", + nvm, 0, s->envm_size); + vmstate_register_ram_global(nvm); + + memory_region_set_readonly(nvm, true); + memory_region_set_readonly(nvm_alias, true); + + memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm); + memory_region_add_subregion(system_memory, 0, nvm_alias); + + memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size, + &error_fatal); + vmstate_register_ram_global(sram); + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram); + + armv7m =3D DEVICE(&s->armv7m); + qdev_prop_set_uint32(armv7m, "num-irq", 81); + qdev_prop_set_string(armv7m, "cpu-model", "cortex-m3"); + object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory(= )), + "memory", &error_abort); + object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err); + if (err !=3D NULL) { + error_propagate(errp, err); + return; + } + + system_clock_scale =3D NANOSECONDS_PER_SECOND / s->m3clk; + + for (i =3D 0; i < MSF2_NUM_UARTS; i++) { + if (serial_hds[i]) { + serial_mm_init(get_system_memory(), uart_addr[i], 2, + qdev_get_gpio_in(armv7m, uart_irq[i]), + 115200, serial_hds[i], DEVICE_NATIVE_ENDIAN); + } + } + + dev =3D DEVICE(&s->timer); + /* APB0 clock is the timer input clock */ + qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk / s->apb0div); + object_property_set_bool(OBJECT(&s->timer), true, "realized", &err); + if (err !=3D NULL) { + error_propagate(errp, err); + return; + } + busdev =3D SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE); + sysbus_connect_irq(busdev, 0, + qdev_get_gpio_in(armv7m, timer_irq[0])); + sysbus_connect_irq(busdev, 1, + qdev_get_gpio_in(armv7m, timer_irq[1])); + + dev =3D DEVICE(&s->sysreg); + qdev_prop_set_uint32(dev, "apb0divisor", s->apb0div); + qdev_prop_set_uint32(dev, "apb1divisor", s->apb1div); + object_property_set_bool(OBJECT(&s->sysreg), true, "realized", &err); + if (err !=3D NULL) { + error_propagate(errp, err); + return; + } + busdev =3D SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE); + + for (i =3D 0; i < MSF2_NUM_SPIS; i++) { + gchar *bus_name =3D g_strdup_printf("spi%d", i); + + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &er= r); + if (err !=3D NULL) { + g_free(bus_name); + error_propagate(errp, err); + return; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, + qdev_get_gpio_in(armv7m, spi_irq[i])); + + /* Alias controller SPI bus to the SoC itself */ + object_property_add_alias(OBJECT(s), bus_name, + OBJECT(&s->spi[i]), "spi", + &error_abort); + g_free(bus_name); + } +} + +static Property m2sxxx_soc_properties[] =3D { + /* + * part name specifies the type of SmartFusion2 device variant(this + * property is for information purpose only. + */ + DEFINE_PROP_STRING("part-name", MSF2State, part_name), + DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_SIZE), + DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size, MSF2_ESRAM_SIZ= E), + /* Libero GUI shows 100Mhz as default for clocks */ + DEFINE_PROP_UINT32("m3clk", MSF2State, m3clk, 100 * 1000000), + /* default divisors in Libero GUI */ + DEFINE_PROP_UINT32("apb0div", MSF2State, apb0div, 2), + DEFINE_PROP_UINT32("apb1div", MSF2State, apb1div, 2), + DEFINE_PROP_END_OF_LIST(), +}; + +static void m2sxxx_soc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D m2sxxx_soc_realize; + dc->props =3D m2sxxx_soc_properties; +} + +static const TypeInfo m2sxxx_soc_info =3D { + .name =3D TYPE_MSF2_SOC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(MSF2State), + .instance_init =3D m2sxxx_soc_initfn, + .class_init =3D m2sxxx_soc_class_init, +}; + +static void m2sxxx_soc_types(void) +{ + type_register_static(&m2sxxx_soc_info); +} + +type_init(m2sxxx_soc_types) diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h new file mode 100644 index 0000000..9ed677a --- /dev/null +++ b/include/hw/arm/msf2-soc.h @@ -0,0 +1,67 @@ +/* + * Microsemi Smartfusion2 SoC + * + * Copyright (c) 2017 Subbaraya Sundeep + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef HW_ARM_MSF2_SOC_H +#define HW_ARM_MSF2_SOC_H + +#include "hw/misc/msf2-sysreg.h" +#include "hw/timer/mss-timer.h" +#include "hw/ssi/mss-spi.h" +#include "hw/arm/armv7m.h" +#include "qemu/cutils.h" + +#define TYPE_MSF2_SOC "msf2-soc" +#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC) + +#define MSF2_NUM_SPIS 2 +#define MSF2_NUM_UARTS 2 + +/* + * System timer consists of two programmable 32-bit + * decrementing counters that generate individual interrupts to + * the Cortex-M3 processor + */ +#define MSF2_NUM_TIMERS 2 + +typedef struct MSF2State { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + ARMv7MState armv7m; + + char *part_name; + uint64_t envm_size; + uint64_t esram_size; + + uint32_t m3clk; + uint32_t apb0div; + uint32_t apb1div; + + MSF2SysregState sysreg; + MSSTimerState timer; + MSSSpiState spi[MSF2_NUM_SPIS]; +} MSF2State; + +#endif --=20 2.5.0 From nobody Tue May 7 12:40:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499057456035987.843229823137; Sun, 2 Jul 2017 21:50:56 -0700 (PDT) Received: from localhost ([::1]:60326 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dRtK2-0003TQ-RR for importer@patchew.org; Mon, 03 Jul 2017 00:50:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40659) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dRtFM-00086t-Th for qemu-devel@nongnu.org; Mon, 03 Jul 2017 00:46:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dRtFK-0008JD-GG for qemu-devel@nongnu.org; Mon, 03 Jul 2017 00:46:04 -0400 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:33781) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dRtFK-0008HQ-8H; Mon, 03 Jul 2017 00:46:02 -0400 Received: by mail-pg0-x244.google.com with SMTP id u62so21812368pgb.0; Sun, 02 Jul 2017 21:46:02 -0700 (PDT) Received: from localhost.localdomain ([124.123.70.3]) by smtp.gmail.com with ESMTPSA id v70sm9324145pfi.110.2017.07.02.21.45.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 02 Jul 2017 21:46:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dqnjQ8lAXxCQdbAOx8Aexl6KCCYCMvkbxCtcjvaK1IE=; b=FXEQ09CRrmeI0FAZLprl5drGysTelxqT6B3HN4Sr6/r+Iofk02e+ojb4zczw+b553i oucD4kXNQOFZiTvn6AoG4IPdtpa6qXPTujHaosfR+8LZCmmXfROo5v4qg5B//CsoXspS S9yGSwUgs1n9mRZG3unSk1wFKqbSAtklHWSJ0W4Om/xerBSlYANedNvOO8rsVv549b1r 2I9UzTr3UpdCuDbA0hpiIpEd46tDTIt8G7ngEgdhFer2ZKYra7wjji7Lr3ttqUInd7aK eX0nGDOp3wpG/SyYW2PDW88Gi3w1LBXccJhKmyJIud1EUQvTj8UcTEZ+azDbn3z4Ol0L tUpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dqnjQ8lAXxCQdbAOx8Aexl6KCCYCMvkbxCtcjvaK1IE=; b=qwrrlvwqGmcwxXE6oeTxD7jhkGAFDfjYEj9JNudnP9HpY4w1MxjYhz4z5l+tGxWsK+ FjIhkhCcnSklqUHg6+99vflemvMCQvkkDxuU2caGc9RPfB5HaNZSqZoEBy1BVptFqXeV nU60yR5kA3+moeiJuV6zSl4PBm4Wu20DtccLhHmTxHr8aZVlZOu2+quzhwF4abz+8Y38 IJpOKAKXKuvMEwkDS7438zdKTMjZm+qKH3AajCDXAflvuN2tenC5n0hyYG7ymk+hyVxd 7uJojc9iGaTGMbbXBCgtv1xA/Ofe5LykSSOrpoQut+0FW9f+z0Kg8NcBP+NAAlIfdpR1 dFDw== X-Gm-Message-State: AIVw113Mfxl9S1AJ5bKmYgQQSsC455tVqe69zBAGvkl5hmGbkxGb7ZxQ eTVLpVdrGu3JB4CB X-Received: by 10.99.39.69 with SMTP id n66mr3370246pgn.94.1499057161221; Sun, 02 Jul 2017 21:46:01 -0700 (PDT) From: Subbaraya Sundeep To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Mon, 3 Jul 2017 10:15:15 +0530 Message-Id: <1499057115-6773-6-git-send-email-sundeep.lkml@gmail.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1499057115-6773-1-git-send-email-sundeep.lkml@gmail.com> References: <1499057115-6773-1-git-send-email-sundeep.lkml@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [Qemu devel v6 PATCH 5/5] msf2: Add Emcraft's Smartfusion2 SOM kit. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Subbaraya Sundeep , f4bug@amsat.org, alistair23@gmail.com, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Emulated Emcraft's Smartfusion2 System On Module starter kit. Signed-off-by: Subbaraya Sundeep --- hw/arm/Makefile.objs | 1 + hw/arm/msf2-som.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 95 insertions(+) create mode 100644 hw/arm/msf2-som.c diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index c828061..2073934 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -5,6 +5,7 @@ obj-y +=3D omap_sx1.o palm.o realview.o spitz.o stellaris.o obj-y +=3D tosa.o versatilepb.o vexpress.o virt.o xilinx_zynq.o z2.o obj-$(CONFIG_ACPI) +=3D virt-acpi-build.o obj-y +=3D netduino2.o +obj-$(CONFIG_MSF2) +=3D msf2-som.o obj-y +=3D sysbus-fdt.o =20 obj-y +=3D armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c new file mode 100644 index 0000000..ea945b1 --- /dev/null +++ b/hw/arm/msf2-som.c @@ -0,0 +1,94 @@ +/* + * SmartFusion2 SOM starter kit(from Emcraft) emulation. + * + * Copyright (c) 2017 Subbaraya Sundeep + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/boards.h" +#include "hw/arm/msf2-soc.h" +#include "hw/arm/arm.h" +#include "exec/address-spaces.h" + +#define DDR_BASE_ADDRESS 0xA0000000 +#define DDR_SIZE (64 * M_BYTE) + +#define M2S010_ENVM_SIZE (256 * K_BYTE) +#define M2S010_ESRAM_SIZE (64 * K_BYTE) + +static void emcraft_sf2_init(MachineState *machine) +{ + DeviceState *dev; + DeviceState *spi_flash; + MSF2State *soc; + DriveInfo *dinfo =3D drive_get_next(IF_MTD); + qemu_irq cs_line; + SSIBus *spi_bus; + MemoryRegion *sysmem =3D get_system_memory(); + MemoryRegion *ddr =3D g_new(MemoryRegion, 1); + + memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE, + &error_fatal); + vmstate_register_ram_global(ddr); + memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr); + + dev =3D qdev_create(NULL, TYPE_MSF2_SOC); + qdev_prop_set_string(dev, "part-name", "M2S010"); + qdev_prop_set_uint64(dev, "eNVM-size", M2S010_ENVM_SIZE); + qdev_prop_set_uint64(dev, "eSRAM-size", M2S010_ESRAM_SIZE); + + /* + * CPU clock and peripheral clocks(APB0, APB1)are configurable + * in Libero. CPU clock is divided by APB0 and APB1 divisors for + * peripherals. Emcraft's SoM kit comes with these settings by default. + */ + qdev_prop_set_uint32(dev, "m3clk", 142 * 1000000); + qdev_prop_set_uint32(dev, "apb0div", 2); + qdev_prop_set_uint32(dev, "apb1div", 2); + + object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal); + + soc =3D MSF2_SOC(dev); + + /* Attach SPI flash to SPI0 controller */ + spi_bus =3D (SSIBus *)qdev_get_child_bus(dev, "spi0"); + spi_flash =3D ssi_create_slave_no_init(spi_bus, "s25sl12801"); + qdev_prop_set_uint8(spi_flash, "spansion-cr2nv", 1); + if (dinfo) { + qdev_prop_set_drive(spi_flash, "drive", blk_by_legacy_dinfo(dinfo), + &error_fatal); + } + qdev_init_nofail(spi_flash); + cs_line =3D qdev_get_gpio_in_named(spi_flash, SSI_GPIO_CS, 0); + sysbus_connect_irq(SYS_BUS_DEVICE(&soc->spi[0]), 1, cs_line); + + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, + soc->envm_size); +} + +static void emcraft_sf2_machine_init(MachineClass *mc) +{ + mc->desc =3D "SmartFusion2 SOM kit from Emcraft"; + mc->init =3D emcraft_sf2_init; +} + +DEFINE_MACHINE("emcraft-sf2", emcraft_sf2_machine_init) --=20 2.5.0