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[81.231.233.234]) by smtp.gmail.com with ESMTPSA id x11sm1424602ljd.5.2017.06.30.06.45.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 30 Jun 2017 06:45:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZIrNi69GSmgTCE1BDm591BaIaZ7IfIndaBwRH1LnK20=; b=tqleLHTn2xW2m7tFt10nmpInBmrc7LwfraBHt3s+x17N4PN3GPZJoePq9Ef5xmUzn1 8AWHB0fmf21AAa2shf8N3By9gzyiX/oe/imkFoUVo0dIG5NR3RMzM7AmFNcSM/sx/Xtc G5EpXKo1gNaVjM02tDMiX7gwBH54txNf7v5WhtYxMAXdLJxz0X/2JnZPOlkC4FWOH1sV MUnJG+tW3xdc2/FrAVxX26H5BgQuVMEpuW0ubwf+002jKkbjKutautFnevjS7F/U9gsy Og0CcCeIXm5OEvd6BzrVfuCRIcZ1x6fLfXL15ILIBXNa3PHd6eCBBH3r9uE0+0O4dh2t C+3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZIrNi69GSmgTCE1BDm591BaIaZ7IfIndaBwRH1LnK20=; b=BQtPQNZ7/Kg9ruhSVw7WPi1bbeMGiB7o9tRpGv/9Ij4SGZ7+Ki/1zP9PPpHY3o1Wh/ kBGdSug73E/Zey4AqNSpbdfSKXf0lOpuH/mMScvBvsJIRA73Mw5ELLaRyZlv6ceoV+ay 3rEy2gDH8ufPZQogAr/48txEERV9kuVT1tLfWao3r3caQnpkcu6snVb1EdV+esNVvm1o kRVlcmofJjBbiNsicNdFFUV3Ch/GE4sEMO3OHCzROXnU97IeyTzCcPHqUKcPhIGSeyx+ K15WNYma25VK7u9UNXqfi0bpiYu53JF0S3EuQh5HdU9qxyfmlgitUuJKvVMUin37g9WX mWJg== X-Gm-Message-State: AKS2vOxxbU+V+o1uzyjBPCPx7vjhl70RFJl7PVH9mXME83zH53If7aET kyStfGREYD6stU6c X-Received: by 10.25.15.221 with SMTP id 90mr6668001lfp.10.1498830305901; Fri, 30 Jun 2017 06:45:05 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Fri, 30 Jun 2017 15:45:01 +0200 Message-Id: <1498830302-19274-2-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1498830302-19274-1-git-send-email-edgar.iglesias@gmail.com> References: <1498830302-19274-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::243 Subject: [Qemu-devel] [PATCH v1 1/2] target-arm: Move the regime_xxx helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Move the regime_xxx helpers in preparation for future code that will reuse them. No functional change. Signed-off-by: Edgar E. Iglesias Reviewed-by: Alistair Francis --- target/arm/helper.c | 404 ++++++++++++++++++++++++++----------------------= ---- 1 file changed, 202 insertions(+), 202 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 2594faa..fd1027e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -35,6 +35,208 @@ static bool get_phys_addr_lpae(CPUARMState *env, target= _ulong address, #define PMCRD 0x8 #define PMCRC 0x4 #define PMCRE 0x1 + +/* Return the exception level which controls this address translation regi= me */ +static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) +{ + switch (mmu_idx) { + case ARMMMUIdx_S2NS: + case ARMMMUIdx_S1E2: + return 2; + case ARMMMUIdx_S1E3: + return 3; + case ARMMMUIdx_S1SE0: + return arm_el_is_aa64(env, 3) ? 1 : 3; + case ARMMMUIdx_S1SE1: + case ARMMMUIdx_S1NSE0: + case ARMMMUIdx_S1NSE1: + case ARMMMUIdx_MPriv: + case ARMMMUIdx_MNegPri: + case ARMMMUIdx_MUser: + return 1; + default: + g_assert_not_reached(); + } +} + +/* Return true if this address translation regime is secure */ +static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) +{ + switch (mmu_idx) { + case ARMMMUIdx_S12NSE0: + case ARMMMUIdx_S12NSE1: + case ARMMMUIdx_S1NSE0: + case ARMMMUIdx_S1NSE1: + case ARMMMUIdx_S1E2: + case ARMMMUIdx_S2NS: + case ARMMMUIdx_MPriv: + case ARMMMUIdx_MNegPri: + case ARMMMUIdx_MUser: + return false; + case ARMMMUIdx_S1E3: + case ARMMMUIdx_S1SE0: + case ARMMMUIdx_S1SE1: + return true; + default: + g_assert_not_reached(); + } +} + +/* Return the SCTLR value which controls this address translation regime */ +static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) +{ + return env->cp15.sctlr_el[regime_el(env, mmu_idx)]; +} + +/* Return true if the specified stage of address translation is disabled */ +static inline bool regime_translation_disabled(CPUARMState *env, + ARMMMUIdx mmu_idx) +{ + if (arm_feature(env, ARM_FEATURE_M)) { + switch (env->v7m.mpu_ctrl & + (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK= )) { + case R_V7M_MPU_CTRL_ENABLE_MASK: + /* Enabled, but not for HardFault and NMI */ + return mmu_idx =3D=3D ARMMMUIdx_MNegPri; + case R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK: + /* Enabled for all cases */ + return false; + case 0: + default: + /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but + * we warned about that in armv7m_nvic.c when the guest set it. + */ + return true; + } + } + + if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { + return (env->cp15.hcr_el2 & HCR_VM) =3D=3D 0; + } + return (regime_sctlr(env, mmu_idx) & SCTLR_M) =3D=3D 0; +} + +static inline bool regime_translation_big_endian(CPUARMState *env, + ARMMMUIdx mmu_idx) +{ + return (regime_sctlr(env, mmu_idx) & SCTLR_EE) !=3D 0; +} + +/* Return the TCR controlling this translation regime */ +static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) +{ + if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { + return &env->cp15.vtcr_el2; + } + return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; +} + +/* Convert a possible stage1+2 MMU index into the appropriate + * stage 1 MMU index + */ +static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) +{ + if (mmu_idx =3D=3D ARMMMUIdx_S12NSE0 || mmu_idx =3D=3D ARMMMUIdx_S12NS= E1) { + mmu_idx +=3D (ARMMMUIdx_S1NSE0 - ARMMMUIdx_S12NSE0); + } + return mmu_idx; +} + +/* Returns TBI0 value for current regime el */ +uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) +{ + TCR *tcr; + uint32_t el; + + /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert + * a stage 1+2 mmu index into the appropriate stage 1 mmu index. + */ + mmu_idx =3D stage_1_mmu_idx(mmu_idx); + + tcr =3D regime_tcr(env, mmu_idx); + el =3D regime_el(env, mmu_idx); + + if (el > 1) { + return extract64(tcr->raw_tcr, 20, 1); + } else { + return extract64(tcr->raw_tcr, 37, 1); + } +} + +/* Returns TBI1 value for current regime el */ +uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) +{ + TCR *tcr; + uint32_t el; + + /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert + * a stage 1+2 mmu index into the appropriate stage 1 mmu index. + */ + mmu_idx =3D stage_1_mmu_idx(mmu_idx); + + tcr =3D regime_tcr(env, mmu_idx); + el =3D regime_el(env, mmu_idx); + + if (el > 1) { + return 0; + } else { + return extract64(tcr->raw_tcr, 38, 1); + } +} + +/* Return the TTBR associated with this translation regime */ +static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, + int ttbrn) +{ + if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { + return env->cp15.vttbr_el2; + } + if (ttbrn =3D=3D 0) { + return env->cp15.ttbr0_el[regime_el(env, mmu_idx)]; + } else { + return env->cp15.ttbr1_el[regime_el(env, mmu_idx)]; + } +} + +/* Return true if the translation regime is using LPAE format page tables = */ +static bool regime_using_lpae_format(CPUARMState *env, + ARMMMUIdx mmu_idx) +{ + int el =3D regime_el(env, mmu_idx); + if (el =3D=3D 2 || arm_el_is_aa64(env, el)) { + return true; + } + if (arm_feature(env, ARM_FEATURE_LPAE) + && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) { + return true; + } + return false; +} + +/* Returns true if the stage 1 translation regime is using LPAE format page + * tables. Used when raising alignment exceptions, whose FSR changes depen= ding + * on whether the long or short descriptor format is in use. */ +bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) +{ + mmu_idx =3D stage_1_mmu_idx(mmu_idx); + + return regime_using_lpae_format(env, mmu_idx); +} + +static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) +{ + switch (mmu_idx) { + case ARMMMUIdx_S1SE0: + case ARMMMUIdx_S1NSE0: + case ARMMMUIdx_MUser: + return true; + default: + return false; + case ARMMMUIdx_S12NSE0: + case ARMMMUIdx_S12NSE1: + g_assert_not_reached(); + } +} #endif =20 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) @@ -7022,208 +7224,6 @@ void arm_cpu_do_interrupt(CPUState *cs) } } =20 -/* Return the exception level which controls this address translation regi= me */ -static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - switch (mmu_idx) { - case ARMMMUIdx_S2NS: - case ARMMMUIdx_S1E2: - return 2; - case ARMMMUIdx_S1E3: - return 3; - case ARMMMUIdx_S1SE0: - return arm_el_is_aa64(env, 3) ? 1 : 3; - case ARMMMUIdx_S1SE1: - case ARMMMUIdx_S1NSE0: - case ARMMMUIdx_S1NSE1: - case ARMMMUIdx_MPriv: - case ARMMMUIdx_MNegPri: - case ARMMMUIdx_MUser: - return 1; - default: - g_assert_not_reached(); - } -} - -/* Return true if this address translation regime is secure */ -static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - switch (mmu_idx) { - case ARMMMUIdx_S12NSE0: - case ARMMMUIdx_S12NSE1: - case ARMMMUIdx_S1NSE0: - case ARMMMUIdx_S1NSE1: - case ARMMMUIdx_S1E2: - case ARMMMUIdx_S2NS: - case ARMMMUIdx_MPriv: - case ARMMMUIdx_MNegPri: - case ARMMMUIdx_MUser: - return false; - case ARMMMUIdx_S1E3: - case ARMMMUIdx_S1SE0: - case ARMMMUIdx_S1SE1: - return true; - default: - g_assert_not_reached(); - } -} - -/* Return the SCTLR value which controls this address translation regime */ -static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - return env->cp15.sctlr_el[regime_el(env, mmu_idx)]; -} - -/* Return true if the specified stage of address translation is disabled */ -static inline bool regime_translation_disabled(CPUARMState *env, - ARMMMUIdx mmu_idx) -{ - if (arm_feature(env, ARM_FEATURE_M)) { - switch (env->v7m.mpu_ctrl & - (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK= )) { - case R_V7M_MPU_CTRL_ENABLE_MASK: - /* Enabled, but not for HardFault and NMI */ - return mmu_idx =3D=3D ARMMMUIdx_MNegPri; - case R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK: - /* Enabled for all cases */ - return false; - case 0: - default: - /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but - * we warned about that in armv7m_nvic.c when the guest set it. - */ - return true; - } - } - - if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { - return (env->cp15.hcr_el2 & HCR_VM) =3D=3D 0; - } - return (regime_sctlr(env, mmu_idx) & SCTLR_M) =3D=3D 0; -} - -static inline bool regime_translation_big_endian(CPUARMState *env, - ARMMMUIdx mmu_idx) -{ - return (regime_sctlr(env, mmu_idx) & SCTLR_EE) !=3D 0; -} - -/* Return the TCR controlling this translation regime */ -static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { - return &env->cp15.vtcr_el2; - } - return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; -} - -/* Convert a possible stage1+2 MMU index into the appropriate - * stage 1 MMU index - */ -static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) -{ - if (mmu_idx =3D=3D ARMMMUIdx_S12NSE0 || mmu_idx =3D=3D ARMMMUIdx_S12NS= E1) { - mmu_idx +=3D (ARMMMUIdx_S1NSE0 - ARMMMUIdx_S12NSE0); - } - return mmu_idx; -} - -/* Returns TBI0 value for current regime el */ -uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - TCR *tcr; - uint32_t el; - - /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert - * a stage 1+2 mmu index into the appropriate stage 1 mmu index. - */ - mmu_idx =3D stage_1_mmu_idx(mmu_idx); - - tcr =3D regime_tcr(env, mmu_idx); - el =3D regime_el(env, mmu_idx); - - if (el > 1) { - return extract64(tcr->raw_tcr, 20, 1); - } else { - return extract64(tcr->raw_tcr, 37, 1); - } -} - -/* Returns TBI1 value for current regime el */ -uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - TCR *tcr; - uint32_t el; - - /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert - * a stage 1+2 mmu index into the appropriate stage 1 mmu index. - */ - mmu_idx =3D stage_1_mmu_idx(mmu_idx); - - tcr =3D regime_tcr(env, mmu_idx); - el =3D regime_el(env, mmu_idx); - - if (el > 1) { - return 0; - } else { - return extract64(tcr->raw_tcr, 38, 1); - } -} - -/* Return the TTBR associated with this translation regime */ -static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, - int ttbrn) -{ - if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { - return env->cp15.vttbr_el2; - } - if (ttbrn =3D=3D 0) { - return env->cp15.ttbr0_el[regime_el(env, mmu_idx)]; - } else { - return env->cp15.ttbr1_el[regime_el(env, mmu_idx)]; - } -} - -/* Return true if the translation regime is using LPAE format page tables = */ -static inline bool regime_using_lpae_format(CPUARMState *env, - ARMMMUIdx mmu_idx) -{ - int el =3D regime_el(env, mmu_idx); - if (el =3D=3D 2 || arm_el_is_aa64(env, el)) { - return true; - } - if (arm_feature(env, ARM_FEATURE_LPAE) - && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) { - return true; - } - return false; -} - -/* Returns true if the stage 1 translation regime is using LPAE format page - * tables. Used when raising alignment exceptions, whose FSR changes depen= ding - * on whether the long or short descriptor format is in use. */ -bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - mmu_idx =3D stage_1_mmu_idx(mmu_idx); - - return regime_using_lpae_format(env, mmu_idx); -} - -static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - switch (mmu_idx) { - case ARMMMUIdx_S1SE0: - case ARMMMUIdx_S1NSE0: - case ARMMMUIdx_MUser: - return true; - default: - return false; - case ARMMMUIdx_S12NSE0: - case ARMMMUIdx_S12NSE1: - g_assert_not_reached(); - } -} - /* Translate section/page access permissions to page * R/W protection flags * --=20 2.7.4 From nobody Sat Apr 27 22:04:22 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498830417778934.431242450336; Fri, 30 Jun 2017 06:46:57 -0700 (PDT) Received: from localhost ([::1]:44615 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQwG7-0007gt-AC for importer@patchew.org; Fri, 30 Jun 2017 09:46:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50647) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQwEQ-0006DL-Rd for qemu-devel@nongnu.org; Fri, 30 Jun 2017 09:45:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQwEP-0007dx-G4 for qemu-devel@nongnu.org; Fri, 30 Jun 2017 09:45:10 -0400 Received: from mail-lf0-x243.google.com ([2a00:1450:4010:c07::243]:34369) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dQwEP-0007cK-8N; Fri, 30 Jun 2017 09:45:09 -0400 Received: by mail-lf0-x243.google.com with SMTP id g21so10121738lfk.1; Fri, 30 Jun 2017 06:45:09 -0700 (PDT) Received: from localhost (81-231-233-234-no56.tbcn.telia.com. [81.231.233.234]) by smtp.gmail.com with ESMTPSA id 3sm1646621lju.69.2017.06.30.06.45.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 30 Jun 2017 06:45:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=p5ZUed3+fyuQ5Au5llR9OOBWdlCSo7ZYkk2o3195Oqk=; b=XxZhA0ZbSQhsF9P0aOdOPfmh9zrDPPVe6nyHJuOi1L2Zk8I2ETNpB+EDAYRTtH3ms9 eUlnlv/m5O76FTz55N987Oo95tU2u1iqjOcKY9gUzuVA+9fTdHyrzk4PCgldXSTb/ltP N8rY37+ytTiYYgFOC9D+LtmMWWE+OYWoqs1Gm1k04NoW/4kZJcw4hL+1qPCqcqZxsmhR oH2GMmvuJdwMr7CS3Biz9q53pWL+LwqbBzRp5I/269No4enDEdPoLEsj6/nm6fgXpagN 9mnrQjg8H9CLQkmrPGKBq9/FXLU9zIUIzfa9GadyFvCrd4cVTqcAIfd68FK3PILTYncg RKlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=p5ZUed3+fyuQ5Au5llR9OOBWdlCSo7ZYkk2o3195Oqk=; b=awYX0IitYS5FgwPbL8beZJaAmLWiMI2SNL7QLCNsV+Dh9QtcP+uCg5jMZd3jtsk9C6 3U60DudyCyQdQO4TIpX9PBkSQwbzdthq4qs/m3MwBUGS2ic7sK+QYV8LW5X75p1waLkk ISQtnayU6xwg9da0LoAINX5KayAAEvUpjHVKExAoWRArFKomUgUGlzDPbW5HRyi8BvKu 4pD8lKCDYJsQK53+wAqF2JRJw3wkErN+8Q7KZZrv0DuZpSMa6/jFVZgAYfEhp0nCsJHY 821GjB74t/JI1uMt53CuVssCu5+mWpVDPDLoW2wOYryHU12qeJxa0yZxRaIpd06F3xLe VX+g== X-Gm-Message-State: AKS2vOw12b7Y11qKLYw1xBthlQWOigXmiDZ4IarXk+DmoYurvwpu/OWS 4OpBf6skhIkHIp4F X-Received: by 10.46.33.165 with SMTP id h37mr7144061lji.15.1498830307750; Fri, 30 Jun 2017 06:45:07 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Fri, 30 Jun 2017 15:45:02 +0200 Message-Id: <1498830302-19274-3-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1498830302-19274-1-git-send-email-edgar.iglesias@gmail.com> References: <1498830302-19274-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::243 Subject: [Qemu-devel] [PATCH v1 2/2] target-arm: Extend PAR format determination X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Extend PAR format determination to handle more cases. Signed-off-by: Edgar E. Iglesias --- target/arm/helper.c | 30 +++++++++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index fd1027e..6a1fffe 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2345,12 +2345,40 @@ static uint64_t do_ats_write(CPUARMState *env, uint= 64_t value, uint32_t fsr; bool ret; uint64_t par64; + bool format64 =3D false; MemTxAttrs attrs =3D {}; ARMMMUFaultInfo fi =3D {}; =20 ret =3D get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs, &prot, &page_size, &fsr, &fi); - if (extended_addresses_enabled(env)) { + + if (is_a64(env)) { + format64 =3D true; + } else if (arm_feature(env, ARM_FEATURE_LPAE)) { + /* + * ATS1Cxx: + * * TTBCR.EAE determines whether the result is returned using the + * 32-bit or the 64-bit PAR format + * * Instructions executed in Hyp mode always use the 64bit format + * + * ATS1S2NSOxx uses the 64bit format if any of the following is tr= ue: + * * The Non-secure TTBCR.EAE bit is set to 1 + * * The implementation includes EL2, and the value of HCR.VM is 1 + * + * ATS1Hx always uses the 64bit format (not supported yet). + */ + format64 =3D regime_using_lpae_format(env, mmu_idx); + + if (arm_feature(env, ARM_FEATURE_EL2)) { + if (mmu_idx =3D=3D ARMMMUIdx_S12NSE0 || mmu_idx =3D=3D ARMMMUI= dx_S12NSE1) { + format64 |=3D env->cp15.hcr_el2 & HCR_VM; + } else { + format64 |=3D arm_current_el(env) =3D=3D 2; + } + } + } + + if (format64) { /* fsr is a DFSR/IFSR value for the long descriptor * translation table format, but with WnR always clear. * Convert it to a 64-bit PAR. --=20 2.7.4