From nobody Tue Feb 10 04:15:34 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498656383647228.7202031948989; Wed, 28 Jun 2017 06:26:23 -0700 (PDT) Received: from localhost ([::1]:33405 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCz7-0006Mf-GX for importer@patchew.org; Wed, 28 Jun 2017 09:26:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57582) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCyN-000627-HO for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:25:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQCyI-0007mc-I2 for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:25:35 -0400 Received: from roura.ac.upc.es ([147.83.33.10]:56132) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCyI-0007mA-6T; Wed, 28 Jun 2017 09:25:30 -0400 Received: from correu-2.ac.upc.es (correu-2.ac.upc.es [147.83.30.92]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5SDPL7r027456; Wed, 28 Jun 2017 15:25:21 +0200 Received: from localhost (unknown [132.68.50.243]) by correu-2.ac.upc.es (Postfix) with ESMTPSA id CBA081E3; Wed, 28 Jun 2017 15:25:15 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Wed, 28 Jun 2017 16:25:14 +0300 Message-Id: <149865631443.17063.7093785957776924619.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149865219962.17063.10630533069463266646.stgit@frigg.lan> References: <149865219962.17063.10630533069463266646.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5SDPL7r027456 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v11 17/29] target/arm: [tcg] Port to init_globals X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , "Emilio G. Cota" , "open list:ARM" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson --- target/arm/translate.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 23a07fc2c6..fc28cd45f7 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11843,6 +11843,18 @@ static void arm_trblock_init_disas_context(DisasCo= ntextBase *dcbase, dc->ss_same_el =3D false; /* Can't be true since EL_d must be AArch64 = */ } =20 +static void arm_trblock_init_globals(DisasContextBase *dcbase, CPUState *c= pu) +{ + cpu_F0s =3D tcg_temp_new_i32(); + cpu_F1s =3D tcg_temp_new_i32(); + cpu_F0d =3D tcg_temp_new_i64(); + cpu_F1d =3D tcg_temp_new_i64(); + cpu_V0 =3D cpu_F0d; + cpu_V1 =3D cpu_F1d; + /* FIXME: cpu_M0 can probably be the same as cpu_V0. */ + cpu_M0 =3D tcg_temp_new_i64(); +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { @@ -11871,14 +11883,7 @@ void gen_intermediate_code(CPUState *cpu, Translat= ionBlock *tb) arm_trblock_init_disas_context(&dc->base, cpu); =20 =20 - cpu_F0s =3D tcg_temp_new_i32(); - cpu_F1s =3D tcg_temp_new_i32(); - cpu_F0d =3D tcg_temp_new_i64(); - cpu_F1d =3D tcg_temp_new_i64(); - cpu_V0 =3D cpu_F0d; - cpu_V1 =3D cpu_F1d; - /* FIXME: cpu_M0 can probably be the same as cpu_V0. */ - cpu_M0 =3D tcg_temp_new_i64(); + arm_trblock_init_globals(&dc->base, cpu); next_page_start =3D (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PA= GE_SIZE; max_insns =3D tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) {