From nobody Sat May 4 11:44:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498653853321658.0886090656779; Wed, 28 Jun 2017 05:44:13 -0700 (PDT) Received: from localhost ([::1]:33114 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCKG-0007JI-Vx for importer@patchew.org; Wed, 28 Jun 2017 08:44:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37158) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQBz2-00057V-B6 for qemu-devel@nongnu.org; Wed, 28 Jun 2017 08:22:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQByy-0002VJ-2D for qemu-devel@nongnu.org; Wed, 28 Jun 2017 08:22:12 -0400 Received: from roura.ac.upc.es ([147.83.33.10]:58686) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQByn-0002QM-Mq; Wed, 28 Jun 2017 08:21:58 -0400 Received: from correu-2.ac.upc.es (correu-2.ac.upc.es [147.83.30.92]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5SCKnsA025450; Wed, 28 Jun 2017 14:20:49 +0200 Received: from localhost (unknown [132.68.50.243]) by correu-2.ac.upc.es (Postfix) with ESMTPSA id 431691C4; Wed, 28 Jun 2017 14:20:43 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Wed, 28 Jun 2017 15:20:42 +0300 Message-Id: <149865244195.17063.11938084353514091141.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149865219962.17063.10630533069463266646.stgit@frigg.lan> References: <149865219962.17063.10630533069463266646.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5SCKnsA025450 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v11 01/29] Pass generic CPUState to gen_intermediate_code() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Anthony Green , Mark Cave-Ayland , Max Filippov , "Edgar E. Iglesias" , Guan Xuetao , Marek Vasut , Alexander Graf , "Emilio G. Cota" , Richard Henderson , Artyom Tarasenko , Eduardo Habkost , "open list:ARM" , Yongbok Kim , Stafford Horne , =?UTF-8?q?Alex=20Benn=C3=A9e?= , David Gibson , Peter Crosthwaite , Bastian Koppelmann , Chris Wulff , Laurent Vivier , Michael Walle , "open list:PowerPC" , Paolo Bonzini , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Needed to implement a target-agnostic gen_intermediate_code() in the future. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: David Gibson Reviewed-by: Richard Henderson --- accel/tcg/translate-all.c | 2 +- include/exec/exec-all.h | 2 +- target/alpha/translate.c | 11 +++++------ target/arm/translate-a64.c | 6 +++--- target/arm/translate.c | 18 +++++++++--------- target/arm/translate.h | 4 ++-- target/cris/translate.c | 17 ++++++++--------- target/hppa/translate.c | 5 ++--- target/i386/translate.c | 13 ++++++------- target/lm32/translate.c | 22 +++++++++++----------- target/m68k/translate.c | 15 +++++++-------- target/microblaze/translate.c | 22 +++++++++++----------- target/mips/translate.c | 15 +++++++-------- target/moxie/translate.c | 14 +++++++------- target/nios2/translate.c | 5 ++--- target/openrisc/translate.c | 20 ++++++++++---------- target/ppc/translate.c | 15 +++++++-------- target/s390x/translate.c | 13 ++++++------- target/sh4/translate.c | 15 +++++++-------- target/sparc/translate.c | 11 +++++------ target/tilegx/translate.c | 7 +++---- target/tricore/translate.c | 9 ++++----- target/unicore32/translate.c | 17 ++++++++--------- target/xtensa/translate.c | 13 ++++++------- 24 files changed, 138 insertions(+), 153 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index f6ad46b613..2dc93f420a 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1299,7 +1299,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_func_start(&tcg_ctx); =20 tcg_ctx.cpu =3D ENV_GET_CPU(env); - gen_intermediate_code(env, tb); + gen_intermediate_code(cpu, tb); tcg_ctx.cpu =3D NULL; =20 trace_translate_block(tb, tb->pc, tb->tc_ptr); diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 724ec73dce..a7cd106587 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -43,7 +43,7 @@ typedef ram_addr_t tb_page_addr_t; =20 #include "qemu/log.h" =20 -void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb); +void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb); void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb, target_ulong *data); =20 diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 232af9e177..c1227c51b0 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -2911,10 +2911,9 @@ static ExitStatus translate_one(DisasContext *ctx, u= int32_t insn) return ret; } =20 -void gen_intermediate_code(CPUAlphaState *env, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb) { - AlphaCPU *cpu =3D alpha_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUAlphaState *env =3D cpu->env_ptr; DisasContext ctx, *ctxp =3D &ctx; target_ulong pc_start; target_ulong pc_mask; @@ -2929,7 +2928,7 @@ void gen_intermediate_code(CPUAlphaState *env, struct= TranslationBlock *tb) ctx.pc =3D pc_start; ctx.mem_idx =3D cpu_mmu_index(env, false); ctx.implver =3D env->implver; - ctx.singlestep_enabled =3D cs->singlestep_enabled; + ctx.singlestep_enabled =3D cpu->singlestep_enabled; =20 #ifdef CONFIG_USER_ONLY ctx.ir =3D cpu_std_ir; @@ -2972,7 +2971,7 @@ void gen_intermediate_code(CPUAlphaState *env, struct= TranslationBlock *tb) tcg_gen_insn_start(ctx.pc); num_insns++; =20 - if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cpu, ctx.pc, BP_ANY))) { ret =3D gen_excp(&ctx, EXCP_DEBUG, 0); /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be @@ -3047,7 +3046,7 @@ void gen_intermediate_code(CPUAlphaState *env, struct= TranslationBlock *tb) && qemu_log_in_addr_range(pc_start)) { qemu_log_lock(); qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, ctx.pc - pc_start, 1); + log_target_disas(cpu, pc_start, ctx.pc - pc_start, 1); qemu_log("\n"); qemu_log_unlock(); } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e55547d95d..f9bd1a9679 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11190,10 +11190,10 @@ static void disas_a64_insn(CPUARMState *env, Disa= sContext *s) free_tmp_a64(s); } =20 -void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb) +void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb) { - CPUState *cs =3D CPU(cpu); - CPUARMState *env =3D &cpu->env; + CPUARMState *env =3D cs->env_ptr; + ARMCPU *cpu =3D arm_env_get_cpu(env); DisasContext dc1, *dc =3D &dc1; target_ulong pc_start; target_ulong next_page_start; diff --git a/target/arm/translate.c b/target/arm/translate.c index 0862f9e4aa..032a263604 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11787,10 +11787,10 @@ static bool insn_crosses_page(CPUARMState *env, D= isasContext *s) } =20 /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { - ARMCPU *cpu =3D arm_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUARMState *env =3D cpu->env_ptr; + ARMCPU *arm_cpu =3D arm_env_get_cpu(env); DisasContext dc1, *dc =3D &dc1; target_ulong pc_start; target_ulong next_page_start; @@ -11814,7 +11814,7 @@ void gen_intermediate_code(CPUARMState *env, Transl= ationBlock *tb) =20 dc->is_jmp =3D DISAS_NEXT; dc->pc =3D pc_start; - dc->singlestep_enabled =3D cs->singlestep_enabled; + dc->singlestep_enabled =3D cpu->singlestep_enabled; dc->condjmp =3D 0; =20 dc->aarch64 =3D 0; @@ -11840,7 +11840,7 @@ void gen_intermediate_code(CPUARMState *env, Transl= ationBlock *tb) dc->vec_stride =3D ARM_TBFLAG_VECSTRIDE(tb->flags); dc->c15_cpar =3D ARM_TBFLAG_XSCALE_CPAR(tb->flags); dc->v7m_handler_mode =3D ARM_TBFLAG_HANDLER(tb->flags); - dc->cp_regs =3D cpu->cp_regs; + dc->cp_regs =3D arm_cpu->cp_regs; dc->features =3D env->features; =20 /* Single step state. The code-generation logic here is: @@ -11941,9 +11941,9 @@ void gen_intermediate_code(CPUARMState *env, Transl= ationBlock *tb) } #endif =20 - if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { + QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { if (bp->pc =3D=3D dc->pc) { if (bp->flags & BP_CPU) { gen_set_condexec(dc); @@ -12042,7 +12042,7 @@ void gen_intermediate_code(CPUARMState *env, Transl= ationBlock *tb) if (dc->condjmp) { /* FIXME: This can theoretically happen with self-modifying code. */ - cpu_abort(cs, "IO on conditional branch instruction"); + cpu_abort(cpu, "IO on conditional branch instruction"); } gen_io_end(); } @@ -12156,7 +12156,7 @@ done_generating: qemu_log_lock(); qemu_log("----------------\n"); qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, dc->pc - pc_start, + log_target_disas(cpu, pc_start, dc->pc - pc_start, dc->thumb | (dc->sctlr_b << 1)); qemu_log("\n"); qemu_log_unlock(); diff --git a/target/arm/translate.h b/target/arm/translate.h index 15d383d9af..e5da614db5 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -146,7 +146,7 @@ static void disas_set_insn_syndrome(DisasContext *s, ui= nt32_t syn) =20 #ifdef TARGET_AARCH64 void a64_translate_init(void); -void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb); +void gen_intermediate_code_a64(CPUState *cpu, TranslationBlock *tb); void gen_a64_set_pc_im(uint64_t val); void aarch64_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags); @@ -155,7 +155,7 @@ static inline void a64_translate_init(void) { } =20 -static inline void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock= *tb) +static inline void gen_intermediate_code_a64(CPUState *cpu, TranslationBlo= ck *tb) { } =20 diff --git a/target/cris/translate.c b/target/cris/translate.c index 0ee05ca02d..35931e7061 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -3080,10 +3080,9 @@ static unsigned int crisv32_decoder(CPUCRISState *en= v, DisasContext *dc) */ =20 /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUCRISState *env, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb) { - CRISCPU *cpu =3D cris_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUCRISState *env =3D cpu->env_ptr; uint32_t pc_start; unsigned int insn_len; struct DisasContext ctx; @@ -3105,13 +3104,13 @@ void gen_intermediate_code(CPUCRISState *env, struc= t TranslationBlock *tb) * delayslot, like in real hw. */ pc_start =3D tb->pc & ~1; - dc->cpu =3D cpu; + dc->cpu =3D cris_env_get_cpu(env); dc->tb =3D tb; =20 dc->is_jmp =3D DISAS_NEXT; dc->ppc =3D pc_start; dc->pc =3D pc_start; - dc->singlestep_enabled =3D cs->singlestep_enabled; + dc->singlestep_enabled =3D cpu->singlestep_enabled; dc->flags_uptodate =3D 1; dc->flagx_known =3D 1; dc->flags_x =3D tb->flags & X_FLAG; @@ -3151,7 +3150,7 @@ void gen_intermediate_code(CPUCRISState *env, struct = TranslationBlock *tb) ? dc->ppc | 1 : dc->pc); num_insns++; =20 - if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cpu, dc->pc, BP_ANY))) { cris_evaluate_flags(dc); tcg_gen_movi_tl(env_pc, dc->pc); t_gen_raise_exception(EXCP_DEBUG); @@ -3225,7 +3224,7 @@ void gen_intermediate_code(CPUCRISState *env, struct = TranslationBlock *tb) =20 /* If we are rexecuting a branch due to exceptions on delay slots don't break. */ - if (!(tb->pc & 1) && cs->singlestep_enabled) { + if (!(tb->pc & 1) && cpu->singlestep_enabled) { break; } } while (!dc->is_jmp && !dc->cpustate_changed @@ -3258,7 +3257,7 @@ void gen_intermediate_code(CPUCRISState *env, struct = TranslationBlock *tb) =20 cris_evaluate_flags(dc); =20 - if (unlikely(cs->singlestep_enabled)) { + if (unlikely(cpu->singlestep_enabled)) { if (dc->is_jmp =3D=3D DISAS_NEXT) { tcg_gen_movi_tl(env_pc, npc); } @@ -3293,7 +3292,7 @@ void gen_intermediate_code(CPUCRISState *env, struct = TranslationBlock *tb) qemu_log_lock(); qemu_log("--------------\n"); qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, dc->pc - pc_start, + log_target_disas(cpu, pc_start, dc->pc - pc_start, env->pregs[PR_VR]); qemu_log("\nisize=3D%d osize=3D%d\n", dc->pc - pc_start, tcg_op_buf_count()); diff --git a/target/hppa/translate.c b/target/hppa/translate.c index e10abc5e04..900870cd5a 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3740,10 +3740,9 @@ static ExitStatus translate_one(DisasContext *ctx, u= int32_t insn) return gen_illegal(ctx); } =20 -void gen_intermediate_code(CPUHPPAState *env, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) { - HPPACPU *cpu =3D hppa_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUHPPAState *env =3D cs->env_ptr; DisasContext ctx; ExitStatus ret; int num_insns, max_insns, i; diff --git a/target/i386/translate.c b/target/i386/translate.c index ed3b896db4..b94303ff10 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8378,10 +8378,9 @@ void tcg_x86_init(void) } =20 /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { - X86CPU *cpu =3D x86_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUX86State *env =3D cpu->env_ptr; DisasContext dc1, *dc =3D &dc1; target_ulong pc_ptr; uint32_t flags; @@ -8404,7 +8403,7 @@ void gen_intermediate_code(CPUX86State *env, Translat= ionBlock *tb) dc->cpl =3D (flags >> HF_CPL_SHIFT) & 3; dc->iopl =3D (flags >> IOPL_SHIFT) & 3; dc->tf =3D (flags >> TF_SHIFT) & 1; - dc->singlestep_enabled =3D cs->singlestep_enabled; + dc->singlestep_enabled =3D cpu->singlestep_enabled; dc->cc_op =3D CC_OP_DYNAMIC; dc->cc_op_dirty =3D false; dc->cs_base =3D cs_base; @@ -8426,7 +8425,7 @@ void gen_intermediate_code(CPUX86State *env, Translat= ionBlock *tb) dc->code64 =3D (flags >> HF_CS64_SHIFT) & 1; #endif dc->flags =3D flags; - dc->jmp_opt =3D !(dc->tf || cs->singlestep_enabled || + dc->jmp_opt =3D !(dc->tf || cpu->singlestep_enabled || (flags & HF_INHIBIT_IRQ_MASK)); /* Do not optimize repz jumps at all in icount mode, because rep movsS instructions are execured with different paths @@ -8475,7 +8474,7 @@ void gen_intermediate_code(CPUX86State *env, Translat= ionBlock *tb) num_insns++; =20 /* If RF is set, suppress an internally generated breakpoint. */ - if (unlikely(cpu_breakpoint_test(cs, pc_ptr, + if (unlikely(cpu_breakpoint_test(cpu, pc_ptr, tb->flags & HF_RF_MASK ? BP_GDB : BP_ANY))) { gen_debug(dc, pc_ptr - dc->cs_base); @@ -8551,7 +8550,7 @@ done_generating: else #endif disas_flags =3D !dc->code32; - log_target_disas(cs, pc_start, pc_ptr - pc_start, disas_flags); + log_target_disas(cpu, pc_start, pc_ptr - pc_start, disas_flags); qemu_log("\n"); qemu_log_unlock(); } diff --git a/target/lm32/translate.c b/target/lm32/translate.c index 692882f447..0ac34fc620 100644 --- a/target/lm32/translate.c +++ b/target/lm32/translate.c @@ -1044,10 +1044,10 @@ static inline void decode(DisasContext *dc, uint32_= t ir) } =20 /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPULM32State *env, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb) { - LM32CPU *cpu =3D lm32_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPULM32State *env =3D cpu->env_ptr; + LM32CPU *lm32_cpu =3D lm32_env_get_cpu(env); struct DisasContext ctx, *dc =3D &ctx; uint32_t pc_start; uint32_t next_page_start; @@ -1055,14 +1055,14 @@ void gen_intermediate_code(CPULM32State *env, struc= t TranslationBlock *tb) int max_insns; =20 pc_start =3D tb->pc; - dc->features =3D cpu->features; - dc->num_breakpoints =3D cpu->num_breakpoints; - dc->num_watchpoints =3D cpu->num_watchpoints; + dc->features =3D lm32_cpu->features; + dc->num_breakpoints =3D lm32_cpu->num_breakpoints; + dc->num_watchpoints =3D lm32_cpu->num_watchpoints; dc->tb =3D tb; =20 dc->is_jmp =3D DISAS_NEXT; dc->pc =3D pc_start; - dc->singlestep_enabled =3D cs->singlestep_enabled; + dc->singlestep_enabled =3D cpu->singlestep_enabled; =20 if (pc_start & 3) { qemu_log_mask(LOG_GUEST_ERROR, @@ -1085,7 +1085,7 @@ void gen_intermediate_code(CPULM32State *env, struct = TranslationBlock *tb) tcg_gen_insn_start(dc->pc); num_insns++; =20 - if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cpu, dc->pc, BP_ANY))) { tcg_gen_movi_tl(cpu_pc, dc->pc); t_gen_raise_exception(dc, EXCP_DEBUG); dc->is_jmp =3D DISAS_UPDATE; @@ -1108,7 +1108,7 @@ void gen_intermediate_code(CPULM32State *env, struct = TranslationBlock *tb) dc->pc +=3D 4; } while (!dc->is_jmp && !tcg_op_buf_full() - && !cs->singlestep_enabled + && !cpu->singlestep_enabled && !singlestep && (dc->pc < next_page_start) && num_insns < max_insns); @@ -1117,7 +1117,7 @@ void gen_intermediate_code(CPULM32State *env, struct = TranslationBlock *tb) gen_io_end(); } =20 - if (unlikely(cs->singlestep_enabled)) { + if (unlikely(cpu->singlestep_enabled)) { if (dc->is_jmp =3D=3D DISAS_NEXT) { tcg_gen_movi_tl(cpu_pc, dc->pc); } @@ -1150,7 +1150,7 @@ void gen_intermediate_code(CPULM32State *env, struct = TranslationBlock *tb) && qemu_log_in_addr_range(pc_start)) { qemu_log_lock(); qemu_log("\n"); - log_target_disas(cs, pc_start, dc->pc - pc_start, 0); + log_target_disas(cpu, pc_start, dc->pc - pc_start, 0); qemu_log("\nisize=3D%d osize=3D%d\n", dc->pc - pc_start, tcg_op_buf_count()); qemu_log_unlock(); diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 7aa0fdc238..01ef3923c9 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -5369,10 +5369,9 @@ static void disas_m68k_insn(CPUM68KState * env, Disa= sContext *s) } =20 /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { - M68kCPU *cpu =3D m68k_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUM68KState *env =3D cpu->env_ptr; DisasContext dc1, *dc =3D &dc1; target_ulong pc_start; int pc_offset; @@ -5389,7 +5388,7 @@ void gen_intermediate_code(CPUM68KState *env, Transla= tionBlock *tb) dc->pc =3D pc_start; dc->cc_op =3D CC_OP_DYNAMIC; dc->cc_op_synced =3D 1; - dc->singlestep_enabled =3D cs->singlestep_enabled; + dc->singlestep_enabled =3D cpu->singlestep_enabled; dc->user =3D (env->sr & SR_S) =3D=3D 0; dc->done_mac =3D 0; dc->writeback_mask =3D 0; @@ -5409,7 +5408,7 @@ void gen_intermediate_code(CPUM68KState *env, Transla= tionBlock *tb) tcg_gen_insn_start(dc->pc, dc->cc_op); num_insns++; =20 - if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cpu, dc->pc, BP_ANY))) { gen_exception(dc, dc->pc, EXCP_DEBUG); dc->is_jmp =3D DISAS_JUMP; /* The address covered by the breakpoint must be included in @@ -5427,14 +5426,14 @@ void gen_intermediate_code(CPUM68KState *env, Trans= lationBlock *tb) dc->insn_pc =3D dc->pc; disas_m68k_insn(env, dc); } while (!dc->is_jmp && !tcg_op_buf_full() && - !cs->singlestep_enabled && + !cpu->singlestep_enabled && !singlestep && (pc_offset) < (TARGET_PAGE_SIZE - 32) && num_insns < max_insns); =20 if (tb->cflags & CF_LAST_IO) gen_io_end(); - if (unlikely(cs->singlestep_enabled)) { + if (unlikely(cpu->singlestep_enabled)) { /* Make sure the pc is updated, and raise a debug exception. */ if (!dc->is_jmp) { update_cc_op(dc); @@ -5467,7 +5466,7 @@ void gen_intermediate_code(CPUM68KState *env, Transla= tionBlock *tb) qemu_log_lock(); qemu_log("----------------\n"); qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, dc->pc - pc_start, 0); + log_target_disas(cpu, pc_start, dc->pc - pc_start, 0); qemu_log("\n"); qemu_log_unlock(); } diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 0bb609513c..d5f499658d 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1594,10 +1594,10 @@ static inline void decode(DisasContext *dc, uint32_= t ir) } =20 /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUMBState *env, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb) { - MicroBlazeCPU *cpu =3D mb_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUMBState *env =3D cpu->env_ptr; + MicroBlazeCPU *mb_cpu =3D mb_env_get_cpu(env); uint32_t pc_start; struct DisasContext ctx; struct DisasContext *dc =3D &ctx; @@ -1607,7 +1607,7 @@ void gen_intermediate_code(CPUMBState *env, struct Tr= anslationBlock *tb) int max_insns; =20 pc_start =3D tb->pc; - dc->cpu =3D cpu; + dc->cpu =3D mb_cpu; dc->tb =3D tb; org_flags =3D dc->synced_flags =3D dc->tb_flags =3D tb->flags; =20 @@ -1618,13 +1618,13 @@ void gen_intermediate_code(CPUMBState *env, struct = TranslationBlock *tb) dc->jmp =3D JMP_INDIRECT; } dc->pc =3D pc_start; - dc->singlestep_enabled =3D cs->singlestep_enabled; + dc->singlestep_enabled =3D cpu->singlestep_enabled; dc->cpustate_changed =3D 0; dc->abort_at_next_insn =3D 0; dc->nr_nops =3D 0; =20 if (pc_start & 3) { - cpu_abort(cs, "Microblaze: unaligned PC=3D%x\n", pc_start); + cpu_abort(cpu, "Microblaze: unaligned PC=3D%x\n", pc_start); } =20 next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; @@ -1650,7 +1650,7 @@ void gen_intermediate_code(CPUMBState *env, struct Tr= anslationBlock *tb) } #endif =20 - if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cpu, dc->pc, BP_ANY))) { t_gen_raise_exception(dc, EXCP_DEBUG); dc->is_jmp =3D DISAS_UPDATE; /* The address covered by the breakpoint must be included in @@ -1707,7 +1707,7 @@ void gen_intermediate_code(CPUMBState *env, struct Tr= anslationBlock *tb) break; } } - if (cs->singlestep_enabled) { + if (cpu->singlestep_enabled) { break; } } while (!dc->is_jmp && !dc->cpustate_changed @@ -1728,7 +1728,7 @@ void gen_intermediate_code(CPUMBState *env, struct Tr= anslationBlock *tb) =20 if (tb->cflags & CF_LAST_IO) gen_io_end(); - /* Force an update if the per-tb cpu state has changed. */ + /* Force an update if the per-tb mb_cpu state has changed. */ if (dc->is_jmp =3D=3D DISAS_NEXT && (dc->cpustate_changed || org_flags !=3D dc->tb_flags)) { dc->is_jmp =3D DISAS_UPDATE; @@ -1736,7 +1736,7 @@ void gen_intermediate_code(CPUMBState *env, struct Tr= anslationBlock *tb) } t_sync_flags(dc); =20 - if (unlikely(cs->singlestep_enabled)) { + if (unlikely(cpu->singlestep_enabled)) { TCGv_i32 tmp =3D tcg_const_i32(EXCP_DEBUG); =20 if (dc->is_jmp !=3D DISAS_JUMP) { @@ -1773,7 +1773,7 @@ void gen_intermediate_code(CPUMBState *env, struct Tr= anslationBlock *tb) qemu_log_lock(); qemu_log("--------------\n"); #if DISAS_GNU - log_target_disas(cs, pc_start, dc->pc - pc_start, 0); + log_target_disas(cpu, pc_start, dc->pc - pc_start, 0); #endif qemu_log("\nisize=3D%d osize=3D%d\n", dc->pc - pc_start, tcg_op_buf_count()); diff --git a/target/mips/translate.c b/target/mips/translate.c index 559f8fed89..1f9e02f426 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -19878,10 +19878,9 @@ static void decode_opc(CPUMIPSState *env, DisasCon= text *ctx) } } =20 -void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb) { - MIPSCPU *cpu =3D mips_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUMIPSState *env =3D cpu->env_ptr; DisasContext ctx; target_ulong pc_start; target_ulong next_page_start; @@ -19894,7 +19893,7 @@ void gen_intermediate_code(CPUMIPSState *env, struc= t TranslationBlock *tb) next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; ctx.pc =3D pc_start; ctx.saved_pc =3D -1; - ctx.singlestep_enabled =3D cs->singlestep_enabled; + ctx.singlestep_enabled =3D cpu->singlestep_enabled; ctx.insn_flags =3D env->insn_flags; ctx.CP0_Config1 =3D env->CP0_Config1; ctx.tb =3D tb; @@ -19941,7 +19940,7 @@ void gen_intermediate_code(CPUMIPSState *env, struc= t TranslationBlock *tb) tcg_gen_insn_start(ctx.pc, ctx.hflags & MIPS_HFLAG_BMASK, ctx.btar= get); num_insns++; =20 - if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cpu, ctx.pc, BP_ANY))) { save_cpu_state(&ctx, 1); ctx.bstate =3D BS_BRANCH; gen_helper_raise_exception_debug(cpu_env); @@ -19996,7 +19995,7 @@ void gen_intermediate_code(CPUMIPSState *env, struc= t TranslationBlock *tb) This is what GDB expects and is consistent with what the hardware does (e.g. if a delay slot instruction faults, the reported PC is the PC of the branch). */ - if (cs->singlestep_enabled && (ctx.hflags & MIPS_HFLAG_BMASK) =3D= =3D 0) { + if (cpu->singlestep_enabled && (ctx.hflags & MIPS_HFLAG_BMASK) =3D= =3D 0) { break; } =20 @@ -20017,7 +20016,7 @@ void gen_intermediate_code(CPUMIPSState *env, struc= t TranslationBlock *tb) if (tb->cflags & CF_LAST_IO) { gen_io_end(); } - if (cs->singlestep_enabled && ctx.bstate !=3D BS_BRANCH) { + if (cpu->singlestep_enabled && ctx.bstate !=3D BS_BRANCH) { save_cpu_state(&ctx, ctx.bstate !=3D BS_EXCP); gen_helper_raise_exception_debug(cpu_env); } else { @@ -20049,7 +20048,7 @@ done_generating: && qemu_log_in_addr_range(pc_start)) { qemu_log_lock(); qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, ctx.pc - pc_start, 0); + log_target_disas(cpu, pc_start, ctx.pc - pc_start, 0); qemu_log("\n"); qemu_log_unlock(); } diff --git a/target/moxie/translate.c b/target/moxie/translate.c index 0660b44c08..176063a1de 100644 --- a/target/moxie/translate.c +++ b/target/moxie/translate.c @@ -822,10 +822,10 @@ static int decode_opc(MoxieCPU *cpu, DisasContext *ct= x) } =20 /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUMoxieState *env, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb) { - MoxieCPU *cpu =3D moxie_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUMoxieState *env =3D cpu->env_ptr; + MoxieCPU *moxie_cpu =3D moxie_env_get_cpu(env); DisasContext ctx; target_ulong pc_start; int num_insns, max_insns; @@ -851,7 +851,7 @@ void gen_intermediate_code(CPUMoxieState *env, struct T= ranslationBlock *tb) tcg_gen_insn_start(ctx.pc); num_insns++; =20 - if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cpu, ctx.pc, BP_ANY))) { tcg_gen_movi_i32(cpu_pc, ctx.pc); gen_helper_debug(cpu_env); ctx.bstate =3D BS_EXCP; @@ -864,12 +864,12 @@ void gen_intermediate_code(CPUMoxieState *env, struct= TranslationBlock *tb) } =20 ctx.opcode =3D cpu_lduw_code(env, ctx.pc); - ctx.pc +=3D decode_opc(cpu, &ctx); + ctx.pc +=3D decode_opc(moxie_cpu, &ctx); =20 if (num_insns >=3D max_insns) { break; } - if (cs->singlestep_enabled) { + if (cpu->singlestep_enabled) { break; } if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) =3D=3D 0) { @@ -877,7 +877,7 @@ void gen_intermediate_code(CPUMoxieState *env, struct T= ranslationBlock *tb) } } while (ctx.bstate =3D=3D BS_NONE && !tcg_op_buf_full()); =20 - if (cs->singlestep_enabled) { + if (cpu->singlestep_enabled) { tcg_gen_movi_tl(cpu_pc, ctx.pc); gen_helper_debug(cpu_env); } else { diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 2f3c2e5dfb..8b97d6585f 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -799,10 +799,9 @@ static void gen_exception(DisasContext *dc, uint32_t e= xcp) } =20 /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUNios2State *env, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { - Nios2CPU *cpu =3D nios2_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUNios2State *env =3D cs->env_ptr; DisasContext dc1, *dc =3D &dc1; int num_insns; int max_insns; diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index e49518e893..4a28c96e53 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1518,10 +1518,10 @@ static void disas_openrisc_insn(DisasContext *dc, O= penRISCCPU *cpu) } } =20 -void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock = *tb) +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb) { - OpenRISCCPU *cpu =3D openrisc_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUOpenRISCState *env =3D cpu->env_ptr; + OpenRISCCPU *or_cpu =3D openrisc_env_get_cpu(env); struct DisasContext ctx, *dc =3D &ctx; uint32_t pc_start; uint32_t next_page_start; @@ -1533,10 +1533,10 @@ void gen_intermediate_code(CPUOpenRISCState *env, s= truct TranslationBlock *tb) =20 dc->is_jmp =3D DISAS_NEXT; dc->pc =3D pc_start; - dc->mem_idx =3D cpu_mmu_index(&cpu->env, false); + dc->mem_idx =3D cpu_mmu_index(&or_cpu->env, false); dc->tb_flags =3D tb->flags; dc->delayed_branch =3D (dc->tb_flags & TB_FLAGS_DFLAG) !=3D 0; - dc->singlestep_enabled =3D cs->singlestep_enabled; + dc->singlestep_enabled =3D cpu->singlestep_enabled; =20 next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; num_insns =3D 0; @@ -1571,7 +1571,7 @@ void gen_intermediate_code(CPUOpenRISCState *env, str= uct TranslationBlock *tb) | (num_insns ? 2 : 0)); num_insns++; =20 - if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cpu, dc->pc, BP_ANY))) { tcg_gen_movi_tl(cpu_pc, dc->pc); gen_exception(dc, EXCP_DEBUG); dc->is_jmp =3D DISAS_UPDATE; @@ -1586,7 +1586,7 @@ void gen_intermediate_code(CPUOpenRISCState *env, str= uct TranslationBlock *tb) if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } - disas_openrisc_insn(dc, cpu); + disas_openrisc_insn(dc, or_cpu); dc->pc =3D dc->pc + 4; =20 /* delay slot */ @@ -1601,7 +1601,7 @@ void gen_intermediate_code(CPUOpenRISCState *env, str= uct TranslationBlock *tb) } } while (!dc->is_jmp && !tcg_op_buf_full() - && !cs->singlestep_enabled + && !cpu->singlestep_enabled && !singlestep && (dc->pc < next_page_start) && num_insns < max_insns); @@ -1619,7 +1619,7 @@ void gen_intermediate_code(CPUOpenRISCState *env, str= uct TranslationBlock *tb) dc->is_jmp =3D DISAS_UPDATE; tcg_gen_movi_tl(cpu_pc, dc->pc); } - if (unlikely(cs->singlestep_enabled)) { + if (unlikely(cpu->singlestep_enabled)) { gen_exception(dc, EXCP_DEBUG); } else { switch (dc->is_jmp) { @@ -1647,7 +1647,7 @@ void gen_intermediate_code(CPUOpenRISCState *env, str= uct TranslationBlock *tb) =20 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && qemu_log_in_addr_range(pc_start)) { - log_target_disas(cs, pc_start, tb->size, 0); + log_target_disas(cpu, pc_start, tb->size, 0); qemu_log("\n"); qemu_log_unlock(); } diff --git a/target/ppc/translate.c b/target/ppc/translate.c index c0cd64d927..9a934117d8 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7203,10 +7203,9 @@ void ppc_cpu_dump_statistics(CPUState *cs, FILE*f, } =20 /*************************************************************************= ****/ -void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUPPCState *env =3D cpu->env_ptr; DisasContext ctx, *ctxp =3D &ctx; opc_handler_t **table, *handler; target_ulong pc_start; @@ -7267,7 +7266,7 @@ void gen_intermediate_code(CPUPPCState *env, struct T= ranslationBlock *tb) ctx.singlestep_enabled =3D 0; if ((env->flags & POWERPC_FLAG_BE) && msr_be) ctx.singlestep_enabled |=3D CPU_BRANCH_STEP; - if (unlikely(cs->singlestep_enabled)) { + if (unlikely(cpu->singlestep_enabled)) { ctx.singlestep_enabled |=3D GDBSTUB_SINGLE_STEP; } #if defined (DO_SINGLE_STEP) && 0 @@ -7290,7 +7289,7 @@ void gen_intermediate_code(CPUPPCState *env, struct T= ranslationBlock *tb) tcg_gen_insn_start(ctx.nip); num_insns++; =20 - if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cpu, ctx.nip, BP_ANY))) { gen_debug_exception(ctxp); /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be @@ -7369,7 +7368,7 @@ void gen_intermediate_code(CPUPPCState *env, struct T= ranslationBlock *tb) ctx.exception !=3D POWERPC_EXCP_BRANCH)) { gen_exception_nip(ctxp, POWERPC_EXCP_TRACE, ctx.nip); } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) =3D=3D 0) = || - (cs->singlestep_enabled) || + (cpu->singlestep_enabled) || singlestep || num_insns >=3D max_insns)) { /* if we reach a page boundary or are single stepping, stop @@ -7389,7 +7388,7 @@ void gen_intermediate_code(CPUPPCState *env, struct T= ranslationBlock *tb) if (ctx.exception =3D=3D POWERPC_EXCP_NONE) { gen_goto_tb(&ctx, 0, ctx.nip); } else if (ctx.exception !=3D POWERPC_EXCP_BRANCH) { - if (unlikely(cs->singlestep_enabled)) { + if (unlikely(cpu->singlestep_enabled)) { gen_debug_exception(ctxp); } /* Generate the return instruction */ @@ -7408,7 +7407,7 @@ void gen_intermediate_code(CPUPPCState *env, struct T= ranslationBlock *tb) flags |=3D ctx.le_mode << 16; qemu_log_lock(); qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, ctx.nip - pc_start, flags); + log_target_disas(cpu, pc_start, ctx.nip - pc_start, flags); qemu_log("\n"); qemu_log_unlock(); } diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 592d6b0f38..19ea08bb9d 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -5764,10 +5764,9 @@ static ExitStatus translate_one(CPUS390XState *env, = DisasContext *s) return ret; } =20 -void gen_intermediate_code(CPUS390XState *env, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb) { - S390CPU *cpu =3D s390_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUS390XState *env =3D cpu->env_ptr; DisasContext dc; target_ulong pc_start; uint64_t next_page_start; @@ -5786,7 +5785,7 @@ void gen_intermediate_code(CPUS390XState *env, struct= TranslationBlock *tb) dc.pc =3D pc_start; dc.cc_op =3D CC_OP_DYNAMIC; dc.ex_value =3D tb->cs_base; - do_debug =3D dc.singlestep_enabled =3D cs->singlestep_enabled; + do_debug =3D dc.singlestep_enabled =3D cpu->singlestep_enabled; =20 next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; =20 @@ -5805,7 +5804,7 @@ void gen_intermediate_code(CPUS390XState *env, struct= TranslationBlock *tb) tcg_gen_insn_start(dc.pc, dc.cc_op); num_insns++; =20 - if (unlikely(cpu_breakpoint_test(cs, dc.pc, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cpu, dc.pc, BP_ANY))) { status =3D EXIT_PC_STALE; do_debug =3D true; /* The address covered by the breakpoint must be included in @@ -5829,7 +5828,7 @@ void gen_intermediate_code(CPUS390XState *env, struct= TranslationBlock *tb) || tcg_op_buf_full() || num_insns >=3D max_insns || singlestep - || cs->singlestep_enabled + || cpu->singlestep_enabled || dc.ex_value)) { status =3D EXIT_PC_STALE; } @@ -5880,7 +5879,7 @@ void gen_intermediate_code(CPUS390XState *env, struct= TranslationBlock *tb) qemu_log("IN: EXECUTE %016" PRIx64 "\n", dc.ex_value); } else { qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, dc.pc - pc_start, 1); + log_target_disas(cpu, pc_start, dc.pc - pc_start, 1); qemu_log("\n"); } qemu_log_unlock(); diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 8bc132b27b..6a797072d4 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -1815,10 +1815,9 @@ static void decode_opc(DisasContext * ctx) } } =20 -void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb) { - SuperHCPU *cpu =3D sh_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUSH4State *env =3D cpu->env_ptr; DisasContext ctx; target_ulong pc_start; int num_insns; @@ -1834,7 +1833,7 @@ void gen_intermediate_code(CPUSH4State * env, struct = TranslationBlock *tb) so assume it is a dynamic branch. */ ctx.delayed_pc =3D -1; /* use delayed pc from env pointer */ ctx.tb =3D tb; - ctx.singlestep_enabled =3D cs->singlestep_enabled; + ctx.singlestep_enabled =3D cpu->singlestep_enabled; ctx.features =3D env->features; ctx.has_movcal =3D (ctx.tbflags & TB_FLAG_PENDING_MOVCA); =20 @@ -1852,7 +1851,7 @@ void gen_intermediate_code(CPUSH4State * env, struct = TranslationBlock *tb) tcg_gen_insn_start(ctx.pc, ctx.envflags); num_insns++; =20 - if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cpu, ctx.pc, BP_ANY))) { /* We have hit a breakpoint - make sure PC is up-to-date */ gen_save_cpu_state(&ctx, true); gen_helper_debug(cpu_env); @@ -1874,7 +1873,7 @@ void gen_intermediate_code(CPUSH4State * env, struct = TranslationBlock *tb) ctx.pc +=3D 2; if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) =3D=3D 0) break; - if (cs->singlestep_enabled) { + if (cpu->singlestep_enabled) { break; } if (num_insns >=3D max_insns) @@ -1884,7 +1883,7 @@ void gen_intermediate_code(CPUSH4State * env, struct = TranslationBlock *tb) } if (tb->cflags & CF_LAST_IO) gen_io_end(); - if (cs->singlestep_enabled) { + if (cpu->singlestep_enabled) { gen_save_cpu_state(&ctx, true); gen_helper_debug(cpu_env); } else { @@ -1915,7 +1914,7 @@ void gen_intermediate_code(CPUSH4State * env, struct = TranslationBlock *tb) && qemu_log_in_addr_range(pc_start)) { qemu_log_lock(); qemu_log("IN:\n"); /* , lookup_symbol(pc_start)); */ - log_target_disas(cs, pc_start, ctx.pc - pc_start, 0); + log_target_disas(cpu, pc_start, ctx.pc - pc_start, 0); qemu_log("\n"); qemu_log_unlock(); } diff --git a/target/sparc/translate.c b/target/sparc/translate.c index aa6734d54e..90c43e4460 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5747,10 +5747,9 @@ static void disas_sparc_insn(DisasContext * dc, unsi= gned int insn) } } =20 -void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb) +void gen_intermediate_code(CPUState *cpu, TranslationBlock * tb) { - SPARCCPU *cpu =3D sparc_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUSPARCState *env =3D cpu->env_ptr; target_ulong pc_start, last_pc; DisasContext dc1, *dc =3D &dc1; int num_insns; @@ -5768,7 +5767,7 @@ void gen_intermediate_code(CPUSPARCState * env, Trans= lationBlock * tb) dc->def =3D env->def; dc->fpu_enabled =3D tb_fpu_enabled(tb->flags); dc->address_mask_32bit =3D tb_am_enabled(tb->flags); - dc->singlestep =3D (cs->singlestep_enabled || singlestep); + dc->singlestep =3D (cpu->singlestep_enabled || singlestep); #ifndef CONFIG_USER_ONLY dc->supervisor =3D (tb->flags & TB_FLAG_SUPER) !=3D 0; #endif @@ -5800,7 +5799,7 @@ void gen_intermediate_code(CPUSPARCState * env, Trans= lationBlock * tb) num_insns++; last_pc =3D dc->pc; =20 - if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cpu, dc->pc, BP_ANY))) { if (dc->pc !=3D pc_start) { save_state(dc); } @@ -5864,7 +5863,7 @@ void gen_intermediate_code(CPUSPARCState * env, Trans= lationBlock * tb) qemu_log_lock(); qemu_log("--------------\n"); qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, last_pc + 4 - pc_start, 0); + log_target_disas(cpu, pc_start, last_pc + 4 - pc_start, 0); qemu_log("\n"); qemu_log_unlock(); } diff --git a/target/tilegx/translate.c b/target/tilegx/translate.c index ff2ef7b63d..a86e9e9d22 100644 --- a/target/tilegx/translate.c +++ b/target/tilegx/translate.c @@ -2370,12 +2370,11 @@ static void translate_one_bundle(DisasContext *dc, = uint64_t bundle) } } =20 -void gen_intermediate_code(CPUTLGState *env, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb) { - TileGXCPU *cpu =3D tilegx_env_get_cpu(env); + CPUTLGState *env =3D cpu->env_ptr; DisasContext ctx; DisasContext *dc =3D &ctx; - CPUState *cs =3D CPU(cpu); uint64_t pc_start =3D tb->pc; uint64_t next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PA= GE_SIZE; int num_insns =3D 0; @@ -2397,7 +2396,7 @@ void gen_intermediate_code(CPUTLGState *env, struct T= ranslationBlock *tb) if (!max_insns) { max_insns =3D CF_COUNT_MASK; } - if (cs->singlestep_enabled || singlestep) { + if (cpu->singlestep_enabled || singlestep) { max_insns =3D 1; } if (max_insns > TCG_MAX_INSNS) { diff --git a/target/tricore/translate.c b/target/tricore/translate.c index ddd2dd07dd..1930da2f2a 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -8782,10 +8782,9 @@ static void decode_opc(CPUTriCoreState *env, DisasCo= ntext *ctx, int *is_branch) } } =20 -void gen_intermediate_code(CPUTriCoreState *env, struct TranslationBlock *= tb) +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb) { - TriCoreCPU *cpu =3D tricore_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUTriCoreState *env =3D cpu->env_ptr; DisasContext ctx; target_ulong pc_start; int num_insns, max_insns; @@ -8806,7 +8805,7 @@ void gen_intermediate_code(CPUTriCoreState *env, stru= ct TranslationBlock *tb) ctx.pc =3D pc_start; ctx.saved_pc =3D -1; ctx.tb =3D tb; - ctx.singlestep_enabled =3D cs->singlestep_enabled; + ctx.singlestep_enabled =3D cpu->singlestep_enabled; ctx.bstate =3D BS_NONE; ctx.mem_idx =3D cpu_mmu_index(env, false); =20 @@ -8840,7 +8839,7 @@ void gen_intermediate_code(CPUTriCoreState *env, stru= ct TranslationBlock *tb) && qemu_log_in_addr_range(pc_start)) { qemu_log_lock(); qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, ctx.pc - pc_start, 0); + log_target_disas(cpu, pc_start, ctx.pc - pc_start, 0); qemu_log("\n"); qemu_log_unlock(); } diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c index 666a2016a8..494ed58c10 100644 --- a/target/unicore32/translate.c +++ b/target/unicore32/translate.c @@ -1869,10 +1869,9 @@ static void disas_uc32_insn(CPUUniCore32State *env, = DisasContext *s) } =20 /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUUniCore32State *env, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUUniCore32State *env =3D cpu->env_ptr; DisasContext dc1, *dc =3D &dc1; target_ulong pc_start; uint32_t next_page_start; @@ -1888,7 +1887,7 @@ void gen_intermediate_code(CPUUniCore32State *env, Tr= anslationBlock *tb) =20 dc->is_jmp =3D DISAS_NEXT; dc->pc =3D pc_start; - dc->singlestep_enabled =3D cs->singlestep_enabled; + dc->singlestep_enabled =3D cpu->singlestep_enabled; dc->condjmp =3D 0; cpu_F0s =3D tcg_temp_new_i32(); cpu_F1s =3D tcg_temp_new_i32(); @@ -1917,7 +1916,7 @@ void gen_intermediate_code(CPUUniCore32State *env, Tr= anslationBlock *tb) tcg_gen_insn_start(dc->pc); num_insns++; =20 - if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cpu, dc->pc, BP_ANY))) { gen_set_pc_im(dc->pc); gen_exception(EXCP_DEBUG); dc->is_jmp =3D DISAS_JUMP; @@ -1949,7 +1948,7 @@ void gen_intermediate_code(CPUUniCore32State *env, Tr= anslationBlock *tb) * Also stop translation when a page boundary is reached. This * ensures prefetch aborts occur at the right place. */ } while (!dc->is_jmp && !tcg_op_buf_full() && - !cs->singlestep_enabled && + !cpu->singlestep_enabled && !singlestep && dc->pc < next_page_start && num_insns < max_insns); @@ -1958,7 +1957,7 @@ void gen_intermediate_code(CPUUniCore32State *env, Tr= anslationBlock *tb) if (dc->condjmp) { /* FIXME: This can theoretically happen with self-modifying code. */ - cpu_abort(cs, "IO on conditional branch instruction"); + cpu_abort(cpu, "IO on conditional branch instruction"); } gen_io_end(); } @@ -1966,7 +1965,7 @@ void gen_intermediate_code(CPUUniCore32State *env, Tr= anslationBlock *tb) /* At this stage dc->condjmp will only be set when the skipped instruction was a conditional branch or trap, and the PC has already been written. */ - if (unlikely(cs->singlestep_enabled)) { + if (unlikely(cpu->singlestep_enabled)) { /* Make sure the pc is updated, and raise a debug exception. */ if (dc->condjmp) { if (dc->is_jmp =3D=3D DISAS_SYSCALL) { @@ -2027,7 +2026,7 @@ done_generating: qemu_log_lock(); qemu_log("----------------\n"); qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, dc->pc - pc_start, 0); + log_target_disas(cpu, pc_start, dc->pc - pc_start, 0); qemu_log("\n"); qemu_log_unlock(); } diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 263002486c..63e4f25c08 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -3117,10 +3117,9 @@ static void gen_ibreak_check(CPUXtensaState *env, Di= sasContext *dc) } } =20 -void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { - XtensaCPU *cpu =3D xtensa_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUXtensaState *env =3D cpu->env_ptr; DisasContext dc; int insn_count =3D 0; int max_insns =3D tb->cflags & CF_COUNT_MASK; @@ -3136,7 +3135,7 @@ void gen_intermediate_code(CPUXtensaState *env, Trans= lationBlock *tb) } =20 dc.config =3D env->config; - dc.singlestep_enabled =3D cs->singlestep_enabled; + dc.singlestep_enabled =3D cpu->singlestep_enabled; dc.tb =3D tb; dc.pc =3D pc_start; dc.ring =3D tb->flags & XTENSA_TBFLAG_RING_MASK; @@ -3179,7 +3178,7 @@ void gen_intermediate_code(CPUXtensaState *env, Trans= lationBlock *tb) tcg_gen_insn_start(dc.pc); ++insn_count; =20 - if (unlikely(cpu_breakpoint_test(cs, dc.pc, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cpu, dc.pc, BP_ANY))) { tcg_gen_movi_i32(cpu_pc, dc.pc); gen_exception(&dc, EXCP_DEBUG); dc.is_jmp =3D DISAS_UPDATE; @@ -3215,7 +3214,7 @@ void gen_intermediate_code(CPUXtensaState *env, Trans= lationBlock *tb) if (dc.icount) { tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount); } - if (cs->singlestep_enabled) { + if (cpu->singlestep_enabled) { tcg_gen_movi_i32(cpu_pc, dc.pc); gen_exception(&dc, EXCP_DEBUG); break; @@ -3247,7 +3246,7 @@ done: qemu_log_lock(); qemu_log("----------------\n"); qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, dc.pc - pc_start, 0); + log_target_disas(cpu, pc_start, dc.pc - pc_start, 0); qemu_log("\n"); qemu_log_unlock(); } From nobody Sat May 4 11:44:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498653001892315.1858436798516; Wed, 28 Jun 2017 05:30:01 -0700 (PDT) Received: from localhost ([::1]:32965 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQC6Z-0004Jw-Lc for importer@patchew.org; Wed, 28 Jun 2017 08:29:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38034) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQC1n-0008Ae-Ic for qemu-devel@nongnu.org; Wed, 28 Jun 2017 08:25:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQC1j-0003V8-Hk for qemu-devel@nongnu.org; Wed, 28 Jun 2017 08:25:03 -0400 Received: from roura.ac.upc.es ([147.83.33.10]:40190) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQC1j-0003Uu-5U for qemu-devel@nongnu.org; Wed, 28 Jun 2017 08:24:59 -0400 Received: from correu-2.ac.upc.es (correu-2.ac.upc.es [147.83.30.92]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5SCOpAP025571; Wed, 28 Jun 2017 14:24:51 +0200 Received: from localhost (unknown [132.68.50.243]) by correu-2.ac.upc.es (Postfix) with ESMTPSA id BA0321C4; Wed, 28 Jun 2017 14:24:45 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Wed, 28 Jun 2017 15:24:44 +0300 Message-Id: <149865268422.17063.3930054464827416476.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149865219962.17063.10630533069463266646.stgit@frigg.lan> References: <149865219962.17063.10630533069463266646.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5SCOpAP025571 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v11 02/29] cpu-exec: Avoid global variables in icount-related functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Peter Crosthwaite , "Emilio G. Cota" , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Signed-off-by: Llu=C3=ADs Vilanova --- include/exec/gen-icount.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index 62d462e494..3fb17d435a 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -19,7 +19,7 @@ static inline void gen_tb_start(TranslationBlock *tb) count =3D tcg_temp_new_i32(); } =20 - tcg_gen_ld_i32(count, cpu_env, + tcg_gen_ld_i32(count, tcg_ctx.tcg_env, -ENV_OFFSET + offsetof(CPUState, icount_decr.u32)); =20 if (tb->cflags & CF_USE_ICOUNT) { @@ -37,7 +37,7 @@ static inline void gen_tb_start(TranslationBlock *tb) tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, exitreq_label); =20 if (tb->cflags & CF_USE_ICOUNT) { - tcg_gen_st16_i32(count, cpu_env, + tcg_gen_st16_i32(count, tcg_ctx.tcg_env, -ENV_OFFSET + offsetof(CPUState, icount_decr.u16.= low)); } =20 @@ -62,14 +62,14 @@ static void gen_tb_end(TranslationBlock *tb, int num_in= sns) static inline void gen_io_start(void) { TCGv_i32 tmp =3D tcg_const_i32(1); - tcg_gen_st_i32(tmp, cpu_env, -ENV_OFFSET + offsetof(CPUState, can_do_i= o)); + tcg_gen_st_i32(tmp, tcg_ctx.tcg_env, -ENV_OFFSET + offsetof(CPUState, = can_do_io)); tcg_temp_free_i32(tmp); } =20 static inline void gen_io_end(void) { TCGv_i32 tmp =3D tcg_const_i32(0); - tcg_gen_st_i32(tmp, cpu_env, -ENV_OFFSET + offsetof(CPUState, can_do_i= o)); + tcg_gen_st_i32(tmp, tcg_ctx.tcg_env, -ENV_OFFSET + offsetof(CPUState, = can_do_io)); tcg_temp_free_i32(tmp); } =20 From nobody Sat May 4 11:44:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498653294372953.6047420236831; Wed, 28 Jun 2017 05:34:54 -0700 (PDT) Received: from localhost ([::1]:33006 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCBJ-000069-2V for importer@patchew.org; Wed, 28 Jun 2017 08:34:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39443) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQC5g-0003pJ-TQ for qemu-devel@nongnu.org; Wed, 28 Jun 2017 08:29:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQC5c-0006JQ-TX for qemu-devel@nongnu.org; Wed, 28 Jun 2017 08:29:04 -0400 Received: from roura.ac.upc.es ([147.83.33.10]:53617) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQC5c-0006IO-7M; Wed, 28 Jun 2017 08:29:00 -0400 Received: from correu-1.ac.upc.es (correu-1.ac.upc.es [147.83.30.91]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5SCSr1W025690; Wed, 28 Jun 2017 14:28:53 +0200 Received: from localhost (unknown [132.68.50.243]) by correu-1.ac.upc.es (Postfix) with ESMTPSA id BD849165; Wed, 28 Jun 2017 14:28:47 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Wed, 28 Jun 2017 15:28:46 +0300 Message-Id: <149865292643.17063.14495945233139782748.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149865219962.17063.10630533069463266646.stgit@frigg.lan> References: <149865219962.17063.10630533069463266646.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5SCSr1W025690 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v11 03/29] target: [tcg] Use a generic enum for DISAS_ values X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , Peter Maydell , Eduardo Habkost , Peter Crosthwaite , Chris Wulff , Laurent Vivier , Alexander Graf , Max Filippov , Michael Walle , "Emilio G. Cota" , "open list:ARM" , "Edgar E. Iglesias" , Paolo Bonzini , Stafford Horne , Guan Xuetao , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Used later. An enum makes expected values explicit and bounds the value spa= ce of switches. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson --- include/exec/exec-all.h | 6 ------ include/exec/translator.h | 38 ++++++++++++++++++++++++++++++++++++++ target/arm/translate.h | 26 ++++++++++++++++---------- target/cris/translate.c | 7 ++++++- target/i386/translate.c | 4 ++++ target/lm32/translate.c | 6 ++++++ target/m68k/translate.c | 7 ++++++- target/microblaze/translate.c | 6 ++++++ target/nios2/translate.c | 6 ++++++ target/openrisc/translate.c | 6 ++++++ target/s390x/translate.c | 3 ++- target/unicore32/translate.c | 7 ++++++- target/xtensa/translate.c | 4 ++++ 13 files changed, 106 insertions(+), 20 deletions(-) create mode 100644 include/exec/translator.h diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index a7cd106587..7e58d64313 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -35,12 +35,6 @@ typedef abi_ulong tb_page_addr_t; typedef ram_addr_t tb_page_addr_t; #endif =20 -/* is_jmp field values */ -#define DISAS_NEXT 0 /* next instruction can be analyzed */ -#define DISAS_JUMP 1 /* only pc was modified dynamically */ -#define DISAS_UPDATE 2 /* cpu state was modified dynamically */ -#define DISAS_TB_JUMP 3 /* only pc was modified statically */ - #include "qemu/log.h" =20 void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb); diff --git a/include/exec/translator.h b/include/exec/translator.h new file mode 100644 index 0000000000..1ffab03a53 --- /dev/null +++ b/include/exec/translator.h @@ -0,0 +1,38 @@ +/* + * Generic intermediate code generation. + * + * Copyright (C) 2016-2017 Llu=C3=ADs Vilanova + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef EXEC__TRANSLATOR_H +#define EXEC__TRANSLATOR_H + +/** + * DisasJumpType: + * @DISAS_NEXT: Next instruction in program order. + * @DISAS_TOO_MANY: Too many instructions translated. + * @DISAS_TARGET: Start of target-specific conditions. + * + * What instruction to disassemble next. + */ +typedef enum DisasJumpType { + DISAS_NEXT, + DISAS_TOO_MANY, + DISAS_TARGET_0, + DISAS_TARGET_1, + DISAS_TARGET_2, + DISAS_TARGET_3, + DISAS_TARGET_4, + DISAS_TARGET_5, + DISAS_TARGET_6, + DISAS_TARGET_7, + DISAS_TARGET_8, + DISAS_TARGET_9, + DISAS_TARGET_10, + DISAS_TARGET_11, +} DisasJumpType; + +#endif /* EXEC__TRANSLATOR_H */ diff --git a/target/arm/translate.h b/target/arm/translate.h index e5da614db5..aba3f44c9f 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -1,6 +1,9 @@ #ifndef TARGET_ARM_TRANSLATE_H #define TARGET_ARM_TRANSLATE_H =20 +#include "exec/translator.h" + + /* internal defines */ typedef struct DisasContext { target_ulong pc; @@ -119,30 +122,33 @@ static void disas_set_insn_syndrome(DisasContext *s, = uint32_t syn) s->insn_start_idx =3D 0; } =20 -/* target-specific extra values for is_jmp */ +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically= */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ /* These instructions trap after executing, so the A32/T32 decoder must * defer them until after the conditional execution state has been updated. * WFI also needs special handling when single-stepping. */ -#define DISAS_WFI 4 -#define DISAS_SWI 5 +#define DISAS_WFI DISAS_TARGET_3 +#define DISAS_SWI DISAS_TARGET_4 /* For instructions which unconditionally cause an exception we can skip * emitting unreachable code at the end of the TB in the A64 decoder */ -#define DISAS_EXC 6 +#define DISAS_EXC DISAS_TARGET_5 /* WFE */ -#define DISAS_WFE 7 -#define DISAS_HVC 8 -#define DISAS_SMC 9 -#define DISAS_YIELD 10 +#define DISAS_WFE DISAS_TARGET_6 +#define DISAS_HVC DISAS_TARGET_7 +#define DISAS_SMC DISAS_TARGET_8 +#define DISAS_YIELD DISAS_TARGET_9 /* M profile branch which might be an exception return (and so needs * custom end-of-TB code) */ -#define DISAS_BX_EXCRET 11 +#define DISAS_BX_EXCRET DISAS_TARGET_10 /* For instructions which want an immediate exit to the main loop, * as opposed to attempting to use lookup_and_goto_ptr. */ -#define DISAS_EXIT 12 +#define DISAS_EXIT DISAS_TARGET_11 =20 #ifdef TARGET_AARCH64 void a64_translate_init(void); diff --git a/target/cris/translate.c b/target/cris/translate.c index 35931e7061..164eed2e9c 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -31,6 +31,7 @@ #include "exec/helper-proto.h" #include "mmu.h" #include "exec/cpu_ldst.h" +#include "exec/translator.h" #include "crisv32-decode.h" =20 #include "exec/helper-gen.h" @@ -50,7 +51,11 @@ #define BUG() (gen_BUG(dc, __FILE__, __LINE__)) #define BUG_ON(x) ({if (x) BUG();}) =20 -#define DISAS_SWI 5 +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically= */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ +#define DISAS_SWI DISAS_TARGET_3 =20 /* Used by the decoder. */ #define EXTRACT_FIELD(src, start, end) \ diff --git a/target/i386/translate.c b/target/i386/translate.c index b94303ff10..5b02637400 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -24,6 +24,7 @@ #include "exec/exec-all.h" #include "tcg-op.h" #include "exec/cpu_ldst.h" +#include "exec/translator.h" =20 #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -71,6 +72,9 @@ =20 //#define MACRO_TEST 1 =20 +/* is_jmp field values */ +#define DISAS_TB_JUMP DISAS_TARGET_0 /* only pc was modified statically */ + /* global register indexes */ static TCGv_env cpu_env; static TCGv cpu_A0; diff --git a/target/lm32/translate.c b/target/lm32/translate.c index 0ac34fc620..c33884e18e 100644 --- a/target/lm32/translate.c +++ b/target/lm32/translate.c @@ -22,6 +22,7 @@ #include "disas/disas.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/translator.h" #include "tcg-op.h" =20 #include "exec/cpu_ldst.h" @@ -47,6 +48,11 @@ =20 #define MEM_INDEX 0 =20 +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically= */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ + static TCGv_env cpu_env; static TCGv cpu_R[32]; static TCGv cpu_pc; diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 01ef3923c9..26afa3cf8c 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -25,6 +25,7 @@ #include "tcg-op.h" #include "qemu/log.h" #include "exec/cpu_ldst.h" +#include "exec/translator.h" =20 #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -173,7 +174,11 @@ static void do_writebacks(DisasContext *s) } } =20 -#define DISAS_JUMP_NEXT 4 +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically= */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamical= ly */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically = */ +#define DISAS_JUMP_NEXT DISAS_TARGET_3 =20 #if defined(CONFIG_USER_ONLY) #define IS_USER(s) 1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index d5f499658d..f6cbf29299 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -27,6 +27,7 @@ #include "microblaze-decode.h" #include "exec/cpu_ldst.h" #include "exec/helper-gen.h" +#include "exec/translator.h" =20 #include "trace-tcg.h" #include "exec/log.h" @@ -46,6 +47,11 @@ #define EXTRACT_FIELD(src, start, end) \ (((src) >> start) & ((1 << (end - start + 1)) - 1)) =20 +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically= */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ + static TCGv env_debug; static TCGv_env cpu_env; static TCGv cpu_R[32]; diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 8b97d6585f..6b0961837d 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -29,6 +29,12 @@ #include "exec/helper-gen.h" #include "exec/log.h" #include "exec/cpu_ldst.h" +#include "exec/translator.h" + +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically= */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ =20 #define INSTRUCTION_FLG(func, flags) { (func), (flags) } #define INSTRUCTION(func) \ diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 4a28c96e53..b3ca1bd586 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -27,6 +27,7 @@ #include "qemu/log.h" #include "qemu/bitops.h" #include "exec/cpu_ldst.h" +#include "exec/translator.h" =20 #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -37,6 +38,11 @@ #define LOG_DIS(str, ...) \ qemu_log_mask(CPU_LOG_TB_IN_ASM, "%08x: " str, dc->pc, ## __VA_ARGS__) =20 +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically= */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ + typedef struct DisasContext { TranslationBlock *tb; target_ulong pc; diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 19ea08bb9d..ccddbc907b 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -76,7 +76,8 @@ typedef struct { } u; } DisasCompare; =20 -#define DISAS_EXCP 4 +/* is_jmp field values */ +#define DISAS_EXCP DISAS_TARGET_0 =20 #ifdef DEBUG_INLINE_BRANCHES static uint64_t inline_branch_hit[CC_OP_MAX]; diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c index 494ed58c10..194aaf64ca 100644 --- a/target/unicore32/translate.c +++ b/target/unicore32/translate.c @@ -16,6 +16,7 @@ #include "tcg-op.h" #include "qemu/log.h" #include "exec/cpu_ldst.h" +#include "exec/translator.h" =20 #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -45,9 +46,13 @@ typedef struct DisasContext { #define IS_USER(s) 1 #endif =20 +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically= */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ /* These instructions trap after executing, so defer them until after the conditional executions state has been updated. */ -#define DISAS_SYSCALL 5 +#define DISAS_SYSCALL DISAS_TARGET_3 =20 static TCGv_env cpu_env; static TCGv_i32 cpu_R[32]; diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 63e4f25c08..1f4b214c6a 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -38,6 +38,7 @@ #include "sysemu/sysemu.h" #include "exec/cpu_ldst.h" #include "exec/semihost.h" +#include "exec/translator.h" =20 #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -46,6 +47,9 @@ #include "exec/log.h" =20 =20 +/* is_jmp field values */ +#define DISAS_UPDATE DISAS_TARGET_0 /* cpu state was modified dynamically= */ + typedef struct DisasContext { const XtensaConfig *config; TranslationBlock *tb; From nobody Sat May 4 11:44:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Wed, 28 Jun 2017 14:32:55 +0200 Received: from localhost (unknown [132.68.50.243]) by correu-1.ac.upc.es (Postfix) with ESMTPSA id AAB3A13A; Wed, 28 Jun 2017 14:32:49 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Wed, 28 Jun 2017 15:32:48 +0300 Message-Id: <149865316837.17063.1608754834009945976.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149865219962.17063.10630533069463266646.stgit@frigg.lan> References: <149865219962.17063.10630533069463266646.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5SCWtAC025797 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v11 04/29] target: [tcg] Add generic translation framework X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Peter Crosthwaite , "Emilio G. Cota" , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson --- accel/tcg/Makefile.objs | 1=20 accel/tcg/translator.c | 153 +++++++++++++++++++++++++++++++++++++++++= ++++ include/exec/gen-icount.h | 2 - include/exec/translator.h | 104 +++++++++++++++++++++++++++++++ 4 files changed, 259 insertions(+), 1 deletion(-) create mode 100644 accel/tcg/translator.c diff --git a/accel/tcg/Makefile.objs b/accel/tcg/Makefile.objs index f173cd5397..3a5da5357c 100644 --- a/accel/tcg/Makefile.objs +++ b/accel/tcg/Makefile.objs @@ -1,3 +1,4 @@ obj-$(CONFIG_SOFTMMU) +=3D tcg-all.o obj-$(CONFIG_SOFTMMU) +=3D cputlb.o obj-y +=3D cpu-exec.o cpu-exec-common.o translate-all.o translate-common.o +obj-y +=3D translator.o diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c new file mode 100644 index 0000000000..b941ebdc62 --- /dev/null +++ b/accel/tcg/translator.c @@ -0,0 +1,153 @@ +/* + * Generic intermediate code generation. + * + * Copyright (C) 2016-2017 Llu=C3=ADs Vilanova + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "qemu/error-report.h" +#include "cpu.h" +#include "tcg/tcg.h" +#include "tcg/tcg-op.h" +#include "exec/exec-all.h" +#include "exec/gen-icount.h" +#include "exec/log.h" +#include "exec/translator.h" + + +static inline void translate_block_tcg_check(const DisasContextBase *db) +{ + if (tcg_check_temp_count()) { + error_report("warning: TCG temporary leaks before "TARGET_FMT_lx, + db->pc_next); + } +} + +void translate_block(const TranslatorOps *ops, DisasContextBase *db, + CPUState *cpu, TranslationBlock *tb) +{ + int max_insns; + + /* Initialize DisasContext */ + db->tb =3D tb; + db->pc_first =3D tb->pc; + db->pc_next =3D db->pc_first; + db->is_jmp =3D DISAS_NEXT; + db->num_insns =3D 0; + db->singlestep_enabled =3D cpu->singlestep_enabled; + ops->init_disas_context(db, cpu); + + /* Initialize globals */ + ops->init_globals(db, cpu); + tcg_clear_temp_count(); + + /* Instruction counting */ + max_insns =3D db->tb->cflags & CF_COUNT_MASK; + if (max_insns =3D=3D 0) { + max_insns =3D CF_COUNT_MASK; + } + if (max_insns > TCG_MAX_INSNS) { + max_insns =3D TCG_MAX_INSNS; + } + if (db->singlestep_enabled || singlestep) { + max_insns =3D 1; + } + + /* Start translating */ + gen_tb_start(db->tb); + ops->tb_start(db, cpu); + + while (true) { + db->num_insns++; + ops->insn_start(db, cpu); + + /* Early exit before breakpoint checks */ + if (unlikely(db->is_jmp !=3D DISAS_NEXT)) { + break; + } + + /* Pass breakpoint hits to target for further processing */ + if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { + CPUBreakpoint *bp; + QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { + if (bp->pc =3D=3D db->pc_next) { + BreakpointCheckType bp_check =3D + ops->breakpoint_check(db, cpu, bp); + switch (bp_check) { + case BC_MISS: + /* Target ignored this breakpoint, go to next */ + break; + case BC_HIT_INSN: + /* Hit, keep translating */ + /* + * TODO: if we're never going to have more than one + * BP in a single address, we can simply use= a + * bool here. + */ + goto done_breakpoints; + case BC_HIT_TB: + /* Hit, end TB */ + goto done_generating; + default: + g_assert_not_reached(); + } + } + } + } + done_breakpoints: + + /* Accept I/O on last instruction */ + if (db->num_insns =3D=3D max_insns && (db->tb->cflags & CF_LAST_IO= )) { + gen_io_start(); + } + + /* Disassemble one instruction */ + db->pc_next =3D ops->translate_insn(db, cpu); + + /**************************************************/ + /* Conditions to stop translation */ + /**************************************************/ + + /* Target-specific conditions set by disassembly */ + if (db->is_jmp !=3D DISAS_NEXT) { + break; + } + + /* Too many instructions */ + if (tcg_op_buf_full() || db->num_insns >=3D max_insns) { + db->is_jmp =3D DISAS_TOO_MANY; + break; + } + + translate_block_tcg_check(db); + } + + ops->tb_stop(db, cpu); + + if (db->tb->cflags & CF_LAST_IO) { + gen_io_end(); + } + +done_generating: + gen_tb_end(db->tb, db->num_insns); + + translate_block_tcg_check(db); + +#ifdef DEBUG_DISAS + if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) + && qemu_log_in_addr_range(db->pc_first)) { + qemu_log_lock(); + qemu_log("----------------\n"); + ops->disas_log(db, cpu); + qemu_log("\n"); + qemu_log_unlock(); + } +#endif + + db->tb->size =3D db->pc_next - db->pc_first; + db->tb->icount =3D db->num_insns; +} diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index 3fb17d435a..d66ca09f60 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -44,7 +44,7 @@ static inline void gen_tb_start(TranslationBlock *tb) tcg_temp_free_i32(count); } =20 -static void gen_tb_end(TranslationBlock *tb, int num_insns) +static inline void gen_tb_end(TranslationBlock *tb, int num_insns) { if (tb->cflags & CF_USE_ICOUNT) { /* Update the num_insn immediate parameter now that we know diff --git a/include/exec/translator.h b/include/exec/translator.h index 1ffab03a53..c6fe64f988 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -10,6 +10,38 @@ #ifndef EXEC__TRANSLATOR_H #define EXEC__TRANSLATOR_H =20 +/* + * Include this header from a target-specific file, and add a + * + * DisasContextBase base; + * + * member in your target-specific DisasContext. + */ + + +#include "exec/exec-all.h" +#include "tcg/tcg.h" + + +/** + * BreakpointCheckType: + * @BC_MISS: No hit + * @BC_HIT_INSN: Hit, but continue translating TB + * @BC_HIT_TB: Hit, stop translating TB + * + * How to react to a breakpoint. A hit means no more breakpoints will be c= hecked + * for the current instruction. + * + * Not all breakpoints associated to an address are necessarily raised by + * targets (e.g., due to conditions encoded in their flags), so tey can de= cide + * that a breakpoint missed the address (@BP_MISS). + */ +typedef enum BreakpointCheckType { + BC_MISS, + BC_HIT_INSN, + BC_HIT_TB, +} BreakpointCheckType; + /** * DisasJumpType: * @DISAS_NEXT: Next instruction in program order. @@ -33,6 +65,78 @@ typedef enum DisasJumpType { DISAS_TARGET_9, DISAS_TARGET_10, DISAS_TARGET_11, + DISAS_TARGET_12, + DISAS_TARGET_13, + DISAS_TARGET_14, } DisasJumpType; =20 +/** + * DisasContextBase: + * @tb: Translation block for this disassembly. + * @pc_first: Address of first guest instruction in this TB. + * @pc_next: Address of next guest instruction in this TB (current during + * disassembly). + * @is_jmp: What instruction to disassemble next. + * @num_insns: Number of translated instructions (including current). + * @singlestep_enabled: "Hardware" single stepping enabled. + * + * Architecture-agnostic disassembly context. + */ +typedef struct DisasContextBase { + TranslationBlock *tb; + target_ulong pc_first; + target_ulong pc_next; + DisasJumpType is_jmp; + unsigned int num_insns; + bool singlestep_enabled; +} DisasContextBase; + +/** + * TranslatorOps: + * @init_disas_context: Initialize a DisasContext struct (DisasContextBase= has + * already been initialized). + * @init_globals: Initialize global variables. + * @tb_start: Start translating a new TB. + * @insn_start: Start translating a new instruction. + * @breakpoint_check: Check if a breakpoint did hit. When called, the brea= kpoint + * has already been checked to match the PC. + * @disas_insn: Disassemble one instruction an return the PC for the next + * one. Can set db->is_jmp to DJ_TARGET or above to stop + * translation. + * @tb_stop: Stop translating a TB. + * @disas_flags: Get flags argument for log_target_disas(). + * + * Target-specific operations for the generic translator loop. + */ +typedef struct TranslatorOps { + void (*init_disas_context)(DisasContextBase *db, CPUState *cpu); + void (*init_globals)(DisasContextBase *db, CPUState *cpu); + void (*tb_start)(DisasContextBase *db, CPUState *cpu); + void (*insn_start)(DisasContextBase *db, CPUState *cpu); + BreakpointCheckType (*breakpoint_check)(DisasContextBase *db, CPUState= *cpu, + const CPUBreakpoint *bp); + target_ulong (*translate_insn)(DisasContextBase *db, CPUState *cpu); + void (*tb_stop)(DisasContextBase *db, CPUState *cpu); + void (*disas_log)(const DisasContextBase *db, CPUState *cpu); +} TranslatorOps; + +/** + * translate_block: + * @ops: Target-specific operations. + * @db: Disassembly context. + * @cpu: Target vCPU. + * @tb: Translation block. + * + * Generic translator loop. + * + * Translation will stop in the following cases (in order): + * - When set by #TranslatorOps::insn_start. + * - When set by #TranslatorOps::translate_insn. + * - When the TCG operation buffer is full. + * - When single-stepping is enabled (system-wide or on the current vCPU). + * - When too many instructions have been translated. + */ +void translate_block(const TranslatorOps *ops, DisasContextBase *db, + CPUState *cpu, TranslationBlock *tb); + #endif /* EXEC__TRANSLATOR_H */ From nobody Sat May 4 11:44:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 149865405945274.91318481280337; Wed, 28 Jun 2017 05:47:39 -0700 (PDT) Received: from localhost ([::1]:33146 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCNe-0001Vl-8j for importer@patchew.org; Wed, 28 Jun 2017 08:47:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42546) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCDe-0002C8-La for qemu-devel@nongnu.org; Wed, 28 Jun 2017 08:37:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQCDb-0003LC-G1 for qemu-devel@nongnu.org; Wed, 28 Jun 2017 08:37:18 -0400 Received: from roura.ac.upc.es ([147.83.33.10]:38354) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCDa-0003Kv-Op for qemu-devel@nongnu.org; Wed, 28 Jun 2017 08:37:15 -0400 Received: from correu-1.ac.upc.es (correu-1.ac.upc.es [147.83.30.91]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5SCavpi025942; Wed, 28 Jun 2017 14:36:57 +0200 Received: from localhost (unknown [132.68.50.243]) by correu-1.ac.upc.es (Postfix) with ESMTPSA id 9BB2B17D; Wed, 28 Jun 2017 14:36:51 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Wed, 28 Jun 2017 15:36:50 +0300 Message-Id: <149865341027.17063.1860120579163763533.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149865219962.17063.10630533069463266646.stgit@frigg.lan> References: <149865219962.17063.10630533069463266646.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5SCavpi025942 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v11 05/29] target/i386: [tcg] Port to DisasContextBase X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Peter Crosthwaite , "Emilio G. Cota" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson --- target/i386/translate.c | 142 +++++++++++++++++++++++--------------------= ---- 1 file changed, 70 insertions(+), 72 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 5b02637400..8cf2485e2c 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -99,6 +99,8 @@ static int x86_64_hregs; #endif =20 typedef struct DisasContext { + DisasContextBase base; + /* current insn context */ int override; /* -1 if no override */ int prefix; @@ -106,8 +108,6 @@ typedef struct DisasContext { TCGMemOp dflag; target_ulong pc_start; target_ulong pc; /* pc =3D eip + cs_base */ - int is_jmp; /* 1 =3D means jump (stop translation), 2 means CPU - static state change (stop translation) */ /* current block context */ target_ulong cs_base; /* base of CS segment */ int pe; /* protected mode */ @@ -128,12 +128,10 @@ typedef struct DisasContext { int cpl; int iopl; int tf; /* TF cpu flag */ - int singlestep_enabled; /* "hardware" single step enabled */ int jmp_opt; /* use direct block chaining for direct jumps */ int repz_opt; /* optimize jumps within repz instructions */ int mem_index; /* select memory access functions */ uint64_t flags; /* all execution flags */ - struct TranslationBlock *tb; int popl_esp_hack; /* for correct popl with esp base handling */ int rip_offset; /* only used in x86_64, but left for simplicity */ int cpuid_features; @@ -1123,7 +1121,7 @@ static void gen_bpt_io(DisasContext *s, TCGv_i32 t_po= rt, int ot) =20 static inline void gen_ins(DisasContext *s, TCGMemOp ot) { - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_string_movl_A0_EDI(s); @@ -1138,14 +1136,14 @@ static inline void gen_ins(DisasContext *s, TCGMemO= p ot) gen_op_movl_T0_Dshift(ot); gen_op_add_reg_T0(s->aflag, R_EDI); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); } } =20 static inline void gen_outs(DisasContext *s, TCGMemOp ot) { - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_string_movl_A0_ESI(s); @@ -1158,7 +1156,7 @@ static inline void gen_outs(DisasContext *s, TCGMemOp= ot) gen_op_movl_T0_Dshift(ot); gen_op_add_reg_T0(s->aflag, R_ESI); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); } } @@ -2141,7 +2139,7 @@ static inline int insn_const_size(TCGMemOp ot) static inline bool use_goto_tb(DisasContext *s, target_ulong pc) { #ifndef CONFIG_USER_ONLY - return (pc & TARGET_PAGE_MASK) =3D=3D (s->tb->pc & TARGET_PAGE_MASK) || + return (pc & TARGET_PAGE_MASK) =3D=3D (s->base.tb->pc & TARGET_PAGE_MA= SK) || (pc & TARGET_PAGE_MASK) =3D=3D (s->pc_start & TARGET_PAGE_MASK); #else return true; @@ -2156,7 +2154,7 @@ static inline void gen_goto_tb(DisasContext *s, int t= b_num, target_ulong eip) /* jump to same page: we can use a direct jump */ tcg_gen_goto_tb(tb_num); gen_jmp_im(eip); - tcg_gen_exit_tb((uintptr_t)s->tb + tb_num); + tcg_gen_exit_tb((uintptr_t)s->base.tb + tb_num); } else { /* jump to another page */ gen_jmp_im(eip); @@ -2177,7 +2175,7 @@ static inline void gen_jcc(DisasContext *s, int b, =20 gen_set_label(l1); gen_goto_tb(s, 1, val); - s->is_jmp =3D DISAS_TB_JUMP; + s->base.is_jmp =3D DISAS_TB_JUMP; } else { l1 =3D gen_new_label(); l2 =3D gen_new_label(); @@ -2248,11 +2246,11 @@ static void gen_movl_seg_T0(DisasContext *s, int se= g_reg) stop as a special handling must be done to disable hardware interrupts for the next instruction */ if (seg_reg =3D=3D R_SS || (s->code32 && seg_reg < R_FS)) - s->is_jmp =3D DISAS_TB_JUMP; + s->base.is_jmp =3D DISAS_TB_JUMP; } else { gen_op_movl_seg_T0_vm(seg_reg); if (seg_reg =3D=3D R_SS) - s->is_jmp =3D DISAS_TB_JUMP; + s->base.is_jmp =3D DISAS_TB_JUMP; } } =20 @@ -2424,7 +2422,7 @@ static void gen_exception(DisasContext *s, int trapno= , target_ulong cur_eip) gen_update_cc_op(s); gen_jmp_im(cur_eip); gen_helper_raise_exception(cpu_env, tcg_const_i32(trapno)); - s->is_jmp =3D DISAS_TB_JUMP; + s->base.is_jmp =3D DISAS_TB_JUMP; } =20 /* Generate #UD for the current instruction. The assumption here is that @@ -2462,7 +2460,7 @@ static void gen_interrupt(DisasContext *s, int intno, gen_jmp_im(cur_eip); gen_helper_raise_interrupt(cpu_env, tcg_const_i32(intno), tcg_const_i32(next_eip - cur_eip)); - s->is_jmp =3D DISAS_TB_JUMP; + s->base.is_jmp =3D DISAS_TB_JUMP; } =20 static void gen_debug(DisasContext *s, target_ulong cur_eip) @@ -2470,7 +2468,7 @@ static void gen_debug(DisasContext *s, target_ulong c= ur_eip) gen_update_cc_op(s); gen_jmp_im(cur_eip); gen_helper_debug(cpu_env); - s->is_jmp =3D DISAS_TB_JUMP; + s->base.is_jmp =3D DISAS_TB_JUMP; } =20 static void gen_set_hflag(DisasContext *s, uint32_t mask) @@ -2526,10 +2524,10 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bo= ol recheck_tf, TCGv jr) gen_reset_hflag(s, HF_INHIBIT_IRQ_MASK); } =20 - if (s->tb->flags & HF_RF_MASK) { + if (s->base.tb->flags & HF_RF_MASK) { gen_helper_reset_rf(cpu_env); } - if (s->singlestep_enabled) { + if (s->base.singlestep_enabled) { gen_helper_debug(cpu_env); } else if (recheck_tf) { gen_helper_rechecking_single_step(cpu_env); @@ -2545,7 +2543,7 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bool= recheck_tf, TCGv jr) } else { tcg_gen_exit_tb(0); } - s->is_jmp =3D DISAS_TB_JUMP; + s->base.is_jmp =3D DISAS_TB_JUMP; } =20 static inline void @@ -2584,7 +2582,7 @@ static void gen_jmp_tb(DisasContext *s, target_ulong = eip, int tb_num) set_cc_op(s, CC_OP_DYNAMIC); if (s->jmp_opt) { gen_goto_tb(s, tb_num, eip); - s->is_jmp =3D DISAS_TB_JUMP; + s->base.is_jmp =3D DISAS_TB_JUMP; } else { gen_jmp_im(eip); gen_eob(s); @@ -4419,7 +4417,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s= , int b, } } =20 -/* convert one instruction. s->is_jmp is set if the translation must +/* convert one instruction. s->base.is_jmp is set if the translation must be stopped. Return the next pc value */ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, target_ulong pc_start) @@ -5379,7 +5377,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_movl_seg_T0(s, reg); gen_pop_update(s, ot); /* Note that reg =3D=3D R_SS in gen_movl_seg_T0 always sets is_jmp= . */ - if (s->is_jmp) { + if (s->base.is_jmp) { gen_jmp_im(s->pc - s->cs_base); if (reg =3D=3D R_SS) { s->tf =3D 0; @@ -5394,7 +5392,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, ot =3D gen_pop_T0(s); gen_movl_seg_T0(s, (b >> 3) & 7); gen_pop_update(s, ot); - if (s->is_jmp) { + if (s->base.is_jmp) { gen_jmp_im(s->pc - s->cs_base); gen_eob(s); } @@ -5445,7 +5443,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); gen_movl_seg_T0(s, reg); /* Note that reg =3D=3D R_SS in gen_movl_seg_T0 always sets is_jmp= . */ - if (s->is_jmp) { + if (s->base.is_jmp) { gen_jmp_im(s->pc - s->cs_base); if (reg =3D=3D R_SS) { s->tf =3D 0; @@ -5654,7 +5652,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_movl_seg_T0(s, op); /* then put the data */ gen_op_mov_reg_v(ot, reg, cpu_T1); - if (s->is_jmp) { + if (s->base.is_jmp) { gen_jmp_im(s->pc - s->cs_base); gen_eob(s); } @@ -6310,7 +6308,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); } else { gen_ins(s, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_jmp(s, s->pc - s->cs_base); } } @@ -6325,7 +6323,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base= ); } else { gen_outs(s, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_jmp(s, s->pc - s->cs_base); } } @@ -6341,14 +6339,14 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, tcg_gen_movi_tl(cpu_T0, val); gen_check_io(s, ot, pc_start - s->cs_base, SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } tcg_gen_movi_i32(cpu_tmp2_i32, val); gen_helper_in_func(ot, cpu_T1, cpu_tmp2_i32); gen_op_mov_reg_v(ot, R_EAX, cpu_T1); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -6362,14 +6360,14 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, svm_is_rep(prefixes)); gen_op_mov_v_reg(ot, cpu_T1, R_EAX); =20 - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } tcg_gen_movi_i32(cpu_tmp2_i32, val); tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T1); gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -6380,14 +6378,14 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, tcg_gen_ext16u_tl(cpu_T0, cpu_regs[R_EDX]); gen_check_io(s, ot, pc_start - s->cs_base, SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0); gen_helper_in_func(ot, cpu_T1, cpu_tmp2_i32); gen_op_mov_reg_v(ot, R_EAX, cpu_T1); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -6400,14 +6398,14 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, svm_is_rep(prefixes)); gen_op_mov_v_reg(ot, cpu_T1, R_EAX); =20 - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0); tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T1); gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -6946,7 +6944,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); gen_helper_pause(cpu_env, tcg_const_i32(s->pc - pc_start)); - s->is_jmp =3D DISAS_TB_JUMP; + s->base.is_jmp =3D DISAS_TB_JUMP; } break; case 0x9b: /* fwait */ @@ -7115,11 +7113,11 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, case 0x131: /* rdtsc */ gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_rdtsc(cpu_env); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -7191,7 +7189,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); gen_helper_hlt(cpu_env, tcg_const_i32(s->pc - pc_start)); - s->is_jmp =3D DISAS_TB_JUMP; + s->base.is_jmp =3D DISAS_TB_JUMP; } break; case 0x100: @@ -7374,7 +7372,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_helper_vmrun(cpu_env, tcg_const_i32(s->aflag - 1), tcg_const_i32(s->pc - pc_start)); tcg_gen_exit_tb(0); - s->is_jmp =3D DISAS_TB_JUMP; + s->base.is_jmp =3D DISAS_TB_JUMP; break; =20 case 0xd9: /* VMMCALL */ @@ -7574,11 +7572,11 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, } gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_rdtscp(cpu_env); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -7943,24 +7941,24 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); if (b & 2) { - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_op_mov_v_reg(ot, cpu_T0, rm); gen_helper_write_crN(cpu_env, tcg_const_i32(reg), cpu_T0); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); } gen_jmp_im(s->pc - s->cs_base); gen_eob(s); } else { - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_read_crN(cpu_T0, cpu_env, tcg_const_i32(reg= )); gen_op_mov_reg_v(ot, rm, cpu_T0); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); } } @@ -8386,15 +8384,13 @@ void gen_intermediate_code(CPUState *cpu, Translati= onBlock *tb) { CPUX86State *env =3D cpu->env_ptr; DisasContext dc1, *dc =3D &dc1; - target_ulong pc_ptr; uint32_t flags; - target_ulong pc_start; target_ulong cs_base; int num_insns; int max_insns; =20 /* generate intermediate code */ - pc_start =3D tb->pc; + dc->base.pc_first =3D tb->pc; cs_base =3D tb->cs_base; flags =3D tb->flags; =20 @@ -8407,11 +8403,11 @@ void gen_intermediate_code(CPUState *cpu, Translati= onBlock *tb) dc->cpl =3D (flags >> HF_CPL_SHIFT) & 3; dc->iopl =3D (flags >> IOPL_SHIFT) & 3; dc->tf =3D (flags >> TF_SHIFT) & 1; - dc->singlestep_enabled =3D cpu->singlestep_enabled; + dc->base.singlestep_enabled =3D cpu->singlestep_enabled; dc->cc_op =3D CC_OP_DYNAMIC; dc->cc_op_dirty =3D false; dc->cs_base =3D cs_base; - dc->tb =3D tb; + dc->base.tb =3D tb; dc->popl_esp_hack =3D 0; /* select memory access functions */ dc->mem_index =3D 0; @@ -8461,8 +8457,8 @@ void gen_intermediate_code(CPUState *cpu, Translation= Block *tb) cpu_ptr1 =3D tcg_temp_new_ptr(); cpu_cc_srcT =3D tcg_temp_local_new(); =20 - dc->is_jmp =3D DISAS_NEXT; - pc_ptr =3D pc_start; + dc->base.is_jmp =3D DISAS_NEXT; + dc->base.pc_next =3D dc->base.pc_first; num_insns =3D 0; max_insns =3D tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { @@ -8474,37 +8470,38 @@ void gen_intermediate_code(CPUState *cpu, Translati= onBlock *tb) =20 gen_tb_start(tb); for(;;) { - tcg_gen_insn_start(pc_ptr, dc->cc_op); + tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); num_insns++; =20 /* If RF is set, suppress an internally generated breakpoint. */ - if (unlikely(cpu_breakpoint_test(cpu, pc_ptr, + if (unlikely(cpu_breakpoint_test(cpu, dc->base.pc_next, tb->flags & HF_RF_MASK ? BP_GDB : BP_ANY))) { - gen_debug(dc, pc_ptr - dc->cs_base); + gen_debug(dc, dc->base.pc_next - dc->cs_base); /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that the logic setting tb->size below does the right thing. */ - pc_ptr +=3D 1; + dc->base.pc_next +=3D 1; goto done_generating; } if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } =20 - pc_ptr =3D disas_insn(env, dc, pc_ptr); + dc->base.pc_next =3D disas_insn(env, dc, dc->base.pc_next); /* stop translation if indicated */ - if (dc->is_jmp) + if (dc->base.is_jmp) { break; + } /* if single step mode, we generate only one instruction and generate an exception */ /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear the flag and abort the translation to give the irqs a change to be happen */ - if (dc->tf || dc->singlestep_enabled || + if (dc->tf || dc->base.singlestep_enabled || (flags & HF_INHIBIT_IRQ_MASK)) { - gen_jmp_im(pc_ptr - dc->cs_base); + gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); break; } @@ -8515,23 +8512,23 @@ void gen_intermediate_code(CPUState *cpu, Translati= onBlock *tb) because an exception hasn't stopped this code. */ if ((tb->cflags & CF_USE_ICOUNT) - && ((pc_ptr & TARGET_PAGE_MASK) - !=3D ((pc_ptr + TARGET_MAX_INSN_SIZE - 1) & TARGET_PAGE_MA= SK) - || (pc_ptr & ~TARGET_PAGE_MASK) =3D=3D 0)) { - gen_jmp_im(pc_ptr - dc->cs_base); + && ((dc->base.pc_next & TARGET_PAGE_MASK) + !=3D ((dc->base.pc_next + TARGET_MAX_INSN_SIZE - 1) & TARG= ET_PAGE_MASK) + || (dc->base.pc_next & ~TARGET_PAGE_MASK) =3D=3D 0)) { + gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); break; } /* if too long translation, stop generation too */ if (tcg_op_buf_full() || - (pc_ptr - pc_start) >=3D (TARGET_PAGE_SIZE - 32) || + (dc->base.pc_next - dc->base.pc_first) >=3D (TARGET_PAGE_SIZE = - 32) || num_insns >=3D max_insns) { - gen_jmp_im(pc_ptr - dc->cs_base); + gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); break; } if (singlestep) { - gen_jmp_im(pc_ptr - dc->cs_base); + gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); break; } @@ -8543,24 +8540,25 @@ done_generating: =20 #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(pc_start)) { + && qemu_log_in_addr_range(dc->base.pc_first)) { int disas_flags; qemu_log_lock(); qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(pc_start)); + qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); #ifdef TARGET_X86_64 if (dc->code64) disas_flags =3D 2; else #endif disas_flags =3D !dc->code32; - log_target_disas(cpu, pc_start, pc_ptr - pc_start, disas_flags); + log_target_disas(cpu, dc->base.pc_first, dc->base.pc_next - dc->ba= se.pc_first, + disas_flags); qemu_log("\n"); qemu_log_unlock(); } #endif =20 - tb->size =3D pc_ptr - pc_start; + tb->size =3D dc->base.pc_next - dc->base.pc_first; tb->icount =3D num_insns; } =20 From nobody Sat May 4 11:44:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498653735683849.6271820233065; Wed, 28 Jun 2017 05:42:15 -0700 (PDT) Received: from localhost ([::1]:33110 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCIP-0005sI-DI for importer@patchew.org; Wed, 28 Jun 2017 08:42:13 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44733) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCHK-0005H6-MJ for qemu-devel@nongnu.org; Wed, 28 Jun 2017 08:41:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQCHH-0005kf-Jo for qemu-devel@nongnu.org; Wed, 28 Jun 2017 08:41:06 -0400 Received: from roura.ac.upc.es ([147.83.33.10]:57809) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCHH-0005jc-5I for qemu-devel@nongnu.org; Wed, 28 Jun 2017 08:41:03 -0400 Received: from correu-1.ac.upc.es (correu-1.ac.upc.es [147.83.30.91]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5SCexwQ026080; Wed, 28 Jun 2017 14:40:59 +0200 Received: from localhost (unknown [132.68.50.243]) by correu-1.ac.upc.es (Postfix) with ESMTPSA id BAAF21C4; Wed, 28 Jun 2017 14:40:53 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Wed, 28 Jun 2017 15:40:52 +0300 Message-Id: <149865365245.17063.7830070270971603805.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149865219962.17063.10630533069463266646.stgit@frigg.lan> References: <149865219962.17063.10630533069463266646.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5SCexwQ026080 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v11 06/29] target/i386: [tcg] Refactor init_disas_context X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Peter Crosthwaite , "Emilio G. Cota" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson --- target/i386/translate.c | 43 ++++++++++++++++++++++++------------------- 1 file changed, 24 insertions(+), 19 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 8cf2485e2c..04453ce48a 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8379,20 +8379,12 @@ void tcg_x86_init(void) } } =20 -/* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) +static void i386_trblock_init_disas_context(DisasContextBase *dcbase, CPUS= tate *cpu) { + DisasContext *dc =3D container_of(dcbase, DisasContext, base); CPUX86State *env =3D cpu->env_ptr; - DisasContext dc1, *dc =3D &dc1; - uint32_t flags; - target_ulong cs_base; - int num_insns; - int max_insns; - - /* generate intermediate code */ - dc->base.pc_first =3D tb->pc; - cs_base =3D tb->cs_base; - flags =3D tb->flags; + uint32_t flags =3D dc->base.tb->flags; + target_ulong cs_base =3D dc->base.tb->cs_base; =20 dc->pe =3D (flags >> HF_PE_SHIFT) & 1; dc->code32 =3D (flags >> HF_CS32_SHIFT) & 1; @@ -8403,11 +8395,9 @@ void gen_intermediate_code(CPUState *cpu, Translatio= nBlock *tb) dc->cpl =3D (flags >> HF_CPL_SHIFT) & 3; dc->iopl =3D (flags >> IOPL_SHIFT) & 3; dc->tf =3D (flags >> TF_SHIFT) & 1; - dc->base.singlestep_enabled =3D cpu->singlestep_enabled; dc->cc_op =3D CC_OP_DYNAMIC; dc->cc_op_dirty =3D false; dc->cs_base =3D cs_base; - dc->base.tb =3D tb; dc->popl_esp_hack =3D 0; /* select memory access functions */ dc->mem_index =3D 0; @@ -8425,7 +8415,7 @@ void gen_intermediate_code(CPUState *cpu, Translation= Block *tb) dc->code64 =3D (flags >> HF_CS64_SHIFT) & 1; #endif dc->flags =3D flags; - dc->jmp_opt =3D !(dc->tf || cpu->singlestep_enabled || + dc->jmp_opt =3D !(dc->tf || dc->base.singlestep_enabled || (flags & HF_INHIBIT_IRQ_MASK)); /* Do not optimize repz jumps at all in icount mode, because rep movsS instructions are execured with different paths @@ -8437,12 +8427,29 @@ void gen_intermediate_code(CPUState *cpu, Translati= onBlock *tb) record/replay modes and there will always be an additional step for ecx=3D0 when icount is enabled. */ - dc->repz_opt =3D !dc->jmp_opt && !(tb->cflags & CF_USE_ICOUNT); + dc->repz_opt =3D !dc->jmp_opt && !(dc->base.tb->cflags & CF_USE_ICOUNT= ); #if 0 /* check addseg logic */ if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32)) printf("ERROR addseg\n"); #endif +} + +/* generate intermediate code for basic block 'tb'. */ +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) +{ + CPUX86State *env =3D cpu->env_ptr; + DisasContext dc1, *dc =3D &dc1; + int num_insns; + int max_insns; + + /* generate intermediate code */ + dc->base.singlestep_enabled =3D cpu->singlestep_enabled; + dc->base.tb =3D tb; + dc->base.is_jmp =3D DISAS_NEXT; + dc->base.pc_first =3D tb->pc; + dc->base.pc_next =3D dc->base.pc_first; + i386_trblock_init_disas_context(&dc->base, cpu); =20 cpu_T0 =3D tcg_temp_new(); cpu_T1 =3D tcg_temp_new(); @@ -8457,8 +8464,6 @@ void gen_intermediate_code(CPUState *cpu, Translation= Block *tb) cpu_ptr1 =3D tcg_temp_new_ptr(); cpu_cc_srcT =3D tcg_temp_local_new(); =20 - dc->base.is_jmp =3D DISAS_NEXT; - dc->base.pc_next =3D dc->base.pc_first; num_insns =3D 0; max_insns =3D tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { @@ -8500,7 +8505,7 @@ void gen_intermediate_code(CPUState *cpu, Translation= Block *tb) the flag and abort the translation to give the irqs a change to be happen */ if (dc->tf || dc->base.singlestep_enabled || - (flags & HF_INHIBIT_IRQ_MASK)) { + (dc->base.tb->flags & HF_INHIBIT_IRQ_MASK)) { gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); break; From nobody Sat May 4 11:44:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498654007003350.41883489087127; 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Wed, 28 Jun 2017 14:44:55 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Wed, 28 Jun 2017 15:44:54 +0300 Message-Id: <149865389443.17063.5223786571159875501.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149865219962.17063.10630533069463266646.stgit@frigg.lan> References: <149865219962.17063.10630533069463266646.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5SCj1lG026222 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v11 07/29] target/i386: [tcg] Refactor init_globals X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Peter Crosthwaite , "Emilio G. Cota" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson --- target/i386/translate.c | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 04453ce48a..d015ea73fa 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8435,6 +8435,22 @@ static void i386_trblock_init_disas_context(DisasCon= textBase *dcbase, CPUState * #endif } =20 +static void i386_trblock_init_globals(DisasContextBase *dcbase, CPUState *= cpu) +{ + cpu_T0 =3D tcg_temp_new(); + cpu_T1 =3D tcg_temp_new(); + cpu_A0 =3D tcg_temp_new(); + + cpu_tmp0 =3D tcg_temp_new(); + cpu_tmp1_i64 =3D tcg_temp_new_i64(); + cpu_tmp2_i32 =3D tcg_temp_new_i32(); + cpu_tmp3_i32 =3D tcg_temp_new_i32(); + cpu_tmp4 =3D tcg_temp_new(); + cpu_ptr0 =3D tcg_temp_new_ptr(); + cpu_ptr1 =3D tcg_temp_new_ptr(); + cpu_cc_srcT =3D tcg_temp_local_new(); +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { @@ -8451,18 +8467,7 @@ void gen_intermediate_code(CPUState *cpu, Translatio= nBlock *tb) dc->base.pc_next =3D dc->base.pc_first; i386_trblock_init_disas_context(&dc->base, cpu); =20 - cpu_T0 =3D tcg_temp_new(); - cpu_T1 =3D tcg_temp_new(); - cpu_A0 =3D tcg_temp_new(); - - cpu_tmp0 =3D tcg_temp_new(); - cpu_tmp1_i64 =3D tcg_temp_new_i64(); - cpu_tmp2_i32 =3D tcg_temp_new_i32(); - cpu_tmp3_i32 =3D tcg_temp_new_i32(); - cpu_tmp4 =3D tcg_temp_new(); - cpu_ptr0 =3D tcg_temp_new_ptr(); - cpu_ptr1 =3D tcg_temp_new_ptr(); - cpu_cc_srcT =3D tcg_temp_local_new(); + i386_trblock_init_globals(&dc->base, cpu); =20 num_insns =3D 0; max_insns =3D tb->cflags & CF_COUNT_MASK; From nobody Sat May 4 11:44:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498654386533910.2318240747446; Wed, 28 Jun 2017 05:53:06 -0700 (PDT) Received: from localhost ([::1]:33203 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCSu-0005sE-6T for importer@patchew.org; Wed, 28 Jun 2017 08:53:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47152) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCPA-00032n-81 for qemu-devel@nongnu.org; Wed, 28 Jun 2017 08:49:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQCP6-00018m-N0 for qemu-devel@nongnu.org; Wed, 28 Jun 2017 08:49:11 -0400 Received: from roura.ac.upc.es ([147.83.33.10]:54119) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCP6-00018a-9g for qemu-devel@nongnu.org; Wed, 28 Jun 2017 08:49:08 -0400 Received: from correu-2.ac.upc.es (correu-2.ac.upc.es [147.83.30.92]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5SCn37R026332; Wed, 28 Jun 2017 14:49:03 +0200 Received: from localhost (unknown [132.68.50.243]) by correu-2.ac.upc.es (Postfix) with ESMTPSA id DC2CC1C4; Wed, 28 Jun 2017 14:48:57 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Wed, 28 Jun 2017 15:48:56 +0300 Message-Id: <149865413649.17063.7416035795116708956.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149865219962.17063.10630533069463266646.stgit@frigg.lan> References: <149865219962.17063.10630533069463266646.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5SCn37R026332 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v11 08/29] target/i386: [tcg] Refactor insn_start X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Peter Crosthwaite , "Emilio G. Cota" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson --- target/i386/translate.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index d015ea73fa..ad57be2928 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8451,6 +8451,13 @@ static void i386_trblock_init_globals(DisasContextBa= se *dcbase, CPUState *cpu) cpu_cc_srcT =3D tcg_temp_local_new(); } =20 +static void i386_trblock_insn_start(DisasContextBase *dcbase, CPUState *cp= u) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { @@ -8480,7 +8487,7 @@ void gen_intermediate_code(CPUState *cpu, Translation= Block *tb) =20 gen_tb_start(tb); for(;;) { - tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); + i386_trblock_insn_start(&dc->base, cpu); num_insns++; =20 /* If RF is set, suppress an internally generated breakpoint. */ From nobody Sat May 4 11:44:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498654754368845.6372523533913; Wed, 28 Jun 2017 05:59:14 -0700 (PDT) Received: from localhost ([::1]:33234 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCYp-0003mj-6F for importer@patchew.org; Wed, 28 Jun 2017 08:59:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48511) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCT7-0006MM-SC for qemu-devel@nongnu.org; Wed, 28 Jun 2017 08:53:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQCT1-0003Ip-Uf for qemu-devel@nongnu.org; Wed, 28 Jun 2017 08:53:17 -0400 Received: from roura.ac.upc.es ([147.83.33.10]:54152) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCT1-0003IK-Hy for qemu-devel@nongnu.org; Wed, 28 Jun 2017 08:53:11 -0400 Received: from correu-1.ac.upc.es (correu-1.ac.upc.es [147.83.30.91]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5SCr5QZ026443; Wed, 28 Jun 2017 14:53:05 +0200 Received: from localhost (unknown [132.68.50.243]) by correu-1.ac.upc.es (Postfix) with ESMTPSA id 0FA4D17D; Wed, 28 Jun 2017 14:52:59 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Wed, 28 Jun 2017 15:52:58 +0300 Message-Id: <149865437871.17063.9119703949695421203.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149865219962.17063.10630533069463266646.stgit@frigg.lan> References: <149865219962.17063.10630533069463266646.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5SCr5QZ026443 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v11 09/29] target/i386: [tcg] Refactor breakpoint_check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Peter Crosthwaite , "Emilio G. Cota" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson --- target/i386/translate.c | 59 ++++++++++++++++++++++++++++++++++++++-----= ---- 1 file changed, 48 insertions(+), 11 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index ad57be2928..3eee348de7 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -18,6 +18,7 @@ */ #include "qemu/osdep.h" =20 +#include "qemu/error-report.h" #include "qemu/host-utils.h" #include "cpu.h" #include "disas/disas.h" @@ -8458,6 +8459,25 @@ static void i386_trblock_insn_start(DisasContextBase= *dcbase, CPUState *cpu) tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); } =20 +static BreakpointCheckType i386_trblock_breakpoint_check( + DisasContextBase *dcbase, CPUState *cpu, const CPUBreakpoint *bp) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + /* If RF is set, suppress an internally generated breakpoint. */ + int flags =3D dc->base.tb->flags & HF_RF_MASK ? BP_GDB : BP_ANY; + if (bp->flags & flags) { + gen_debug(dc, dc->base.pc_next - dc->cs_base); + /* The address covered by the breakpoint must be included in + [tb->pc, tb->pc + tb->size) in order to for it to be + properly cleared -- thus we increment the PC here so that + the logic setting tb->size below does the right thing. */ + dc->base.pc_next +=3D 1; + return BC_HIT_TB; + } else { + return BC_MISS; + } +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { @@ -8490,18 +8510,35 @@ void gen_intermediate_code(CPUState *cpu, Translati= onBlock *tb) i386_trblock_insn_start(&dc->base, cpu); num_insns++; =20 - /* If RF is set, suppress an internally generated breakpoint. */ - if (unlikely(cpu_breakpoint_test(cpu, dc->base.pc_next, - tb->flags & HF_RF_MASK - ? BP_GDB : BP_ANY))) { - gen_debug(dc, dc->base.pc_next - dc->cs_base); - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - dc->base.pc_next +=3D 1; - goto done_generating; + if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { + CPUBreakpoint *bp; + QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { + if (bp->pc =3D=3D dc->base.pc_next) { + BreakpointCheckType bp_check =3D + i386_trblock_breakpoint_check(&dc->base, cpu, bp); + switch (bp_check) { + case BC_MISS: + /* Target ignored this breakpoint, go to next */ + break; + case BC_HIT_INSN: + /* Hit, keep translating */ + /* + * TODO: if we're never going to have more than one + * BP in a single address, we can simply use= a + * bool here. + */ + goto done_breakpoints; + case BC_HIT_TB: + /* Hit, end TB */ + goto done_generating; + default: + g_assert_not_reached(); + } + } + } } + done_breakpoints: + if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } From nobody Sat May 4 11:44:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498655108528887.5929612534442; Wed, 28 Jun 2017 06:05:08 -0700 (PDT) Received: from localhost ([::1]:33276 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCeY-0000WB-5g for importer@patchew.org; Wed, 28 Jun 2017 09:05:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49604) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCWy-0001yY-Du for qemu-devel@nongnu.org; Wed, 28 Jun 2017 08:57:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQCWt-0005XA-Hy for qemu-devel@nongnu.org; Wed, 28 Jun 2017 08:57:16 -0400 Received: from roura.ac.upc.es ([147.83.33.10]:54527) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCWt-0005Wu-4z for qemu-devel@nongnu.org; Wed, 28 Jun 2017 08:57:11 -0400 Received: from correu-1.ac.upc.es (correu-1.ac.upc.es [147.83.30.91]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5SCv7cL026592; Wed, 28 Jun 2017 14:57:07 +0200 Received: from localhost (unknown [132.68.50.243]) by correu-1.ac.upc.es (Postfix) with ESMTPSA id 003901C4; Wed, 28 Jun 2017 14:57:01 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Wed, 28 Jun 2017 15:57:00 +0300 Message-Id: <149865462073.17063.17488435214703164893.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149865219962.17063.10630533069463266646.stgit@frigg.lan> References: <149865219962.17063.10630533069463266646.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5SCv7cL026592 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v11 10/29] target/i386: [tcg] Refactor translate_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Peter Crosthwaite , "Emilio G. Cota" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson --- target/i386/translate.c | 72 +++++++++++++++++++++++++++++++------------= ---- 1 file changed, 48 insertions(+), 24 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 3eee348de7..da4b409d97 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -4420,15 +4420,17 @@ static void gen_sse(CPUX86State *env, DisasContext = *s, int b, =20 /* convert one instruction. s->base.is_jmp is set if the translation must be stopped. Return the next pc value */ -static target_ulong disas_insn(CPUX86State *env, DisasContext *s, - target_ulong pc_start) +static target_ulong disas_insn(DisasContextBase *dcbase, CPUState *cpu) { + DisasContext *s =3D container_of(dcbase, DisasContext, base); + CPUX86State *env =3D cpu->env_ptr; int b, prefixes; int shift; TCGMemOp ot, aflag, dflag; int modrm, reg, rm, mod, op, opreg, val; target_ulong next_eip, tval; int rex_w, rex_r; + target_ulong pc_start =3D s->base.pc_next; =20 s->pc_start =3D s->pc =3D pc_start; prefixes =3D 0; @@ -8478,10 +8480,51 @@ static BreakpointCheckType i386_trblock_breakpoint_= check( } } =20 +static target_ulong i386_trblock_translate_insn(DisasContextBase *dcbase, + CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + target_ulong pc_next =3D disas_insn(&dc->base, cpu); + + if (dc->base.is_jmp) { + return pc_next; + } + + if (dc->tf || (dc->base.tb->flags & HF_INHIBIT_IRQ_MASK)) { + /* if single step mode, we generate only one instruction and + generate an exception */ + /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear + the flag and abort the translation to give the irqs a + change to be happen */ + gen_jmp_im(pc_next - dc->cs_base); + gen_eob(dc); + dc->base.is_jmp =3D DISAS_TOO_MANY; + } else if ((dc->base.tb->cflags & CF_USE_ICOUNT) + && ((dc->base.pc_next & TARGET_PAGE_MASK) + !=3D ((dc->base.pc_next + TARGET_MAX_INSN_SIZE - 1) + & TARGET_PAGE_MASK) + || (dc->base.pc_next & ~TARGET_PAGE_MASK) =3D=3D 0)) { + /* Do not cross the boundary of the pages in icount mode, + it can cause an exception. Do it only when boundary is + crossed by the first instruction in the block. + If current instruction already crossed the bound - it's ok, + because an exception hasn't stopped this code. + */ + gen_jmp_im(pc_next - dc->cs_base); + gen_eob(dc); + dc->base.is_jmp =3D DISAS_TOO_MANY; + } else if ((pc_next - dc->base.pc_first) >=3D (TARGET_PAGE_SIZE - 32))= { + gen_jmp_im(pc_next - dc->cs_base); + gen_eob(dc); + dc->base.is_jmp =3D DISAS_TOO_MANY; + } + + return pc_next; +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { - CPUX86State *env =3D cpu->env_ptr; DisasContext dc1, *dc =3D &dc1; int num_insns; int max_insns; @@ -8543,39 +8586,20 @@ void gen_intermediate_code(CPUState *cpu, Translati= onBlock *tb) gen_io_start(); } =20 - dc->base.pc_next =3D disas_insn(env, dc, dc->base.pc_next); + dc->base.pc_next =3D i386_trblock_translate_insn(&dc->base, cpu); /* stop translation if indicated */ if (dc->base.is_jmp) { break; } /* if single step mode, we generate only one instruction and generate an exception */ - /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear - the flag and abort the translation to give the irqs a - change to be happen */ - if (dc->tf || dc->base.singlestep_enabled || - (dc->base.tb->flags & HF_INHIBIT_IRQ_MASK)) { - gen_jmp_im(dc->base.pc_next - dc->cs_base); - gen_eob(dc); - break; - } - /* Do not cross the boundary of the pages in icount mode, - it can cause an exception. Do it only when boundary is - crossed by the first instruction in the block. - If current instruction already crossed the bound - it's ok, - because an exception hasn't stopped this code. - */ - if ((tb->cflags & CF_USE_ICOUNT) - && ((dc->base.pc_next & TARGET_PAGE_MASK) - !=3D ((dc->base.pc_next + TARGET_MAX_INSN_SIZE - 1) & TARG= ET_PAGE_MASK) - || (dc->base.pc_next & ~TARGET_PAGE_MASK) =3D=3D 0)) { + if (dc->base.singlestep_enabled) { gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); break; } /* if too long translation, stop generation too */ if (tcg_op_buf_full() || - (dc->base.pc_next - dc->base.pc_first) >=3D (TARGET_PAGE_SIZE = - 32) || num_insns >=3D max_insns) { gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); From nobody Sat May 4 11:44:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498655158763166.53514991647808; Wed, 28 Jun 2017 06:05:58 -0700 (PDT) Received: from localhost ([::1]:33287 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCfK-0001D4-ED for importer@patchew.org; Wed, 28 Jun 2017 09:05:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50678) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCb3-00065a-Tb for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:01:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQCaz-0007hE-3Q for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:01:29 -0400 Received: from roura.ac.upc.es ([147.83.33.10]:42935) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCay-0007gc-Mk for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:01:25 -0400 Received: from correu-1.ac.upc.es (correu-1.ac.upc.es [147.83.30.91]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5SD19Xc026742; Wed, 28 Jun 2017 15:01:18 +0200 Received: from localhost (unknown [132.68.50.243]) by correu-1.ac.upc.es (Postfix) with ESMTPSA id EC9D41C4; Wed, 28 Jun 2017 15:01:03 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Wed, 28 Jun 2017 16:01:02 +0300 Message-Id: <149865486266.17063.7032445527012069283.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149865219962.17063.10630533069463266646.stgit@frigg.lan> References: <149865219962.17063.10630533069463266646.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5SD19Xc026742 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v11 11/29] target/i386: [tcg] Refactor tb_stop X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Peter Crosthwaite , "Emilio G. Cota" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson --- target/i386/translate.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index da4b409d97..1ca40c2fe4 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8496,8 +8496,6 @@ static target_ulong i386_trblock_translate_insn(Disas= ContextBase *dcbase, /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear the flag and abort the translation to give the irqs a change to be happen */ - gen_jmp_im(pc_next - dc->cs_base); - gen_eob(dc); dc->base.is_jmp =3D DISAS_TOO_MANY; } else if ((dc->base.tb->cflags & CF_USE_ICOUNT) && ((dc->base.pc_next & TARGET_PAGE_MASK) @@ -8510,18 +8508,24 @@ static target_ulong i386_trblock_translate_insn(Dis= asContextBase *dcbase, If current instruction already crossed the bound - it's ok, because an exception hasn't stopped this code. */ - gen_jmp_im(pc_next - dc->cs_base); - gen_eob(dc); dc->base.is_jmp =3D DISAS_TOO_MANY; } else if ((pc_next - dc->base.pc_first) >=3D (TARGET_PAGE_SIZE - 32))= { - gen_jmp_im(pc_next - dc->cs_base); - gen_eob(dc); dc->base.is_jmp =3D DISAS_TOO_MANY; } =20 return pc_next; } =20 +static void i386_trblock_tb_stop(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + if (dc->base.is_jmp =3D=3D DISAS_TOO_MANY) { + gen_jmp_im(dc->base.pc_next - dc->cs_base); + gen_eob(dc); + } +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { @@ -8594,23 +8598,21 @@ void gen_intermediate_code(CPUState *cpu, Translati= onBlock *tb) /* if single step mode, we generate only one instruction and generate an exception */ if (dc->base.singlestep_enabled) { - gen_jmp_im(dc->base.pc_next - dc->cs_base); - gen_eob(dc); + dc->base.is_jmp =3D DISAS_TOO_MANY; break; } /* if too long translation, stop generation too */ if (tcg_op_buf_full() || num_insns >=3D max_insns) { - gen_jmp_im(dc->base.pc_next - dc->cs_base); - gen_eob(dc); + dc->base.is_jmp =3D DISAS_TOO_MANY; break; } if (singlestep) { - gen_jmp_im(dc->base.pc_next - dc->cs_base); - gen_eob(dc); + dc->base.is_jmp =3D DISAS_TOO_MANY; break; } } + i386_trblock_tb_stop(&dc->base, cpu); if (tb->cflags & CF_LAST_IO) gen_io_end(); done_generating: From nobody Sat May 4 11:44:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498655279235360.92615969651195; Wed, 28 Jun 2017 06:07:59 -0700 (PDT) Received: from localhost ([::1]:33298 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQChH-0002ig-U8 for importer@patchew.org; Wed, 28 Jun 2017 09:07:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51807) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCew-00019A-F7 for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:05:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQCer-0001tv-EK for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:05:30 -0400 Received: from roura.ac.upc.es ([147.83.33.10]:49431) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCer-0001qs-2M for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:05:25 -0400 Received: from correu-2.ac.upc.es (correu-2.ac.upc.es [147.83.30.92]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5SD5BdP026891; Wed, 28 Jun 2017 15:05:15 +0200 Received: from localhost (unknown [132.68.50.243]) by correu-2.ac.upc.es (Postfix) with ESMTPSA id C21541E0; Wed, 28 Jun 2017 15:05:05 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Wed, 28 Jun 2017 16:05:04 +0300 Message-Id: <149865510456.17063.14029858939919926288.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149865219962.17063.10630533069463266646.stgit@frigg.lan> References: <149865219962.17063.10630533069463266646.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5SD5BdP026891 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v11 12/29] target/i386: [tcg] Refactor disas_log X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Peter Crosthwaite , "Emilio G. Cota" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson --- target/i386/translate.c | 29 +++++++++++++++++++---------- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 1ca40c2fe4..3950fe95a4 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8526,6 +8526,24 @@ static void i386_trblock_tb_stop(DisasContextBase *d= cbase, CPUState *cpu) } } =20 +static void i386_trblock_disas_log(const DisasContextBase *dcbase, + CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + int disas_flags; + + qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); +#ifdef TARGET_X86_64 + if (dc->code64) + disas_flags =3D 2; + else +#endif + disas_flags =3D !dc->code32; + log_target_disas(cpu, dc->base.pc_first, dc->base.pc_next - dc->base.p= c_first, + disas_flags); + +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { @@ -8621,18 +8639,9 @@ done_generating: #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && qemu_log_in_addr_range(dc->base.pc_first)) { - int disas_flags; qemu_log_lock(); qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); -#ifdef TARGET_X86_64 - if (dc->code64) - disas_flags =3D 2; - else -#endif - disas_flags =3D !dc->code32; - log_target_disas(cpu, dc->base.pc_first, dc->base.pc_next - dc->ba= se.pc_first, - disas_flags); + i386_trblock_disas_log(&dc->base, cpu); qemu_log("\n"); qemu_log_unlock(); } From nobody Sat May 4 11:44:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498655606267468.4684950186913; Wed, 28 Jun 2017 06:13:26 -0700 (PDT) Received: from localhost ([::1]:33326 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCmY-0007sj-4Y for importer@patchew.org; Wed, 28 Jun 2017 09:13:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53025) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCih-0004Gz-Hv for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:09:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQCie-0005hW-C9 for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:09:23 -0400 Received: from roura.ac.upc.es ([147.83.33.10]:52550) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCid-0005gm-Qd for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:09:20 -0400 Received: from correu-1.ac.upc.es (correu-1.ac.upc.es [147.83.30.91]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5SD9DAF027007; Wed, 28 Jun 2017 15:09:13 +0200 Received: from localhost (unknown [132.68.50.243]) by correu-1.ac.upc.es (Postfix) with ESMTPSA id B208F13A; Wed, 28 Jun 2017 15:09:07 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Wed, 28 Jun 2017 16:09:06 +0300 Message-Id: <149865534644.17063.5754453204442221401.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149865219962.17063.10630533069463266646.stgit@frigg.lan> References: <149865219962.17063.10630533069463266646.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5SD9DAF027007 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v11 13/29] target/i386: [tcg] Port to generic translation framework X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Peter Crosthwaite , "Emilio G. Cota" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Tested-by: Emilio G. Cota --- target/i386/translate.c | 120 +++++++------------------------------------= ---- 1 file changed, 18 insertions(+), 102 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 3950fe95a4..295be26a95 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8454,6 +8454,10 @@ static void i386_trblock_init_globals(DisasContextBa= se *dcbase, CPUState *cpu) cpu_cc_srcT =3D tcg_temp_local_new(); } =20 +static void i386_trblock_tb_start(DisasContextBase *db, CPUState *cpu) +{ +} + static void i386_trblock_insn_start(DisasContextBase *dcbase, CPUState *cp= u) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); @@ -8472,7 +8476,7 @@ static BreakpointCheckType i386_trblock_breakpoint_ch= eck( /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ + the generic logic setting tb->size later does the right thing. = */ dc->base.pc_next +=3D 1; return BC_HIT_TB; } else { @@ -8544,111 +8548,23 @@ static void i386_trblock_disas_log(const DisasCont= extBase *dcbase, =20 } =20 +static const TranslatorOps i386_trblock_ops =3D { + .init_disas_context =3D i386_trblock_init_disas_context, + .init_globals =3D i386_trblock_init_globals, + .tb_start =3D i386_trblock_tb_start, + .insn_start =3D i386_trblock_insn_start, + .breakpoint_check =3D i386_trblock_breakpoint_check, + .translate_insn =3D i386_trblock_translate_insn, + .tb_stop =3D i386_trblock_tb_stop, + .disas_log =3D i386_trblock_disas_log, +}; + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { - DisasContext dc1, *dc =3D &dc1; - int num_insns; - int max_insns; - - /* generate intermediate code */ - dc->base.singlestep_enabled =3D cpu->singlestep_enabled; - dc->base.tb =3D tb; - dc->base.is_jmp =3D DISAS_NEXT; - dc->base.pc_first =3D tb->pc; - dc->base.pc_next =3D dc->base.pc_first; - i386_trblock_init_disas_context(&dc->base, cpu); - - i386_trblock_init_globals(&dc->base, cpu); - - num_insns =3D 0; - max_insns =3D tb->cflags & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } - - gen_tb_start(tb); - for(;;) { - i386_trblock_insn_start(&dc->base, cpu); - num_insns++; - - if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { - if (bp->pc =3D=3D dc->base.pc_next) { - BreakpointCheckType bp_check =3D - i386_trblock_breakpoint_check(&dc->base, cpu, bp); - switch (bp_check) { - case BC_MISS: - /* Target ignored this breakpoint, go to next */ - break; - case BC_HIT_INSN: - /* Hit, keep translating */ - /* - * TODO: if we're never going to have more than one - * BP in a single address, we can simply use= a - * bool here. - */ - goto done_breakpoints; - case BC_HIT_TB: - /* Hit, end TB */ - goto done_generating; - default: - g_assert_not_reached(); - } - } - } - } - done_breakpoints: - - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { - gen_io_start(); - } - - dc->base.pc_next =3D i386_trblock_translate_insn(&dc->base, cpu); - /* stop translation if indicated */ - if (dc->base.is_jmp) { - break; - } - /* if single step mode, we generate only one instruction and - generate an exception */ - if (dc->base.singlestep_enabled) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - break; - } - /* if too long translation, stop generation too */ - if (tcg_op_buf_full() || - num_insns >=3D max_insns) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - break; - } - if (singlestep) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - break; - } - } - i386_trblock_tb_stop(&dc->base, cpu); - if (tb->cflags & CF_LAST_IO) - gen_io_end(); -done_generating: - gen_tb_end(tb, num_insns); - -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(dc->base.pc_first)) { - qemu_log_lock(); - qemu_log("----------------\n"); - i386_trblock_disas_log(&dc->base, cpu); - qemu_log("\n"); - qemu_log_unlock(); - } -#endif + DisasContext dc1; =20 - tb->size =3D dc->base.pc_next - dc->base.pc_first; - tb->icount =3D num_insns; + translate_block(&i386_trblock_ops, &dc1.base, cpu, tb); } =20 void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb, From nobody Sat May 4 11:44:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 149865570596991.53101808308861; Wed, 28 Jun 2017 06:15:05 -0700 (PDT) Received: from localhost ([::1]:33337 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCoA-0000hX-Gq for importer@patchew.org; Wed, 28 Jun 2017 09:15:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54275) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCmc-00085T-T9 for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:13:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQCmZ-0008PR-Lh for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:13:26 -0400 Received: from roura.ac.upc.es ([147.83.33.10]:52584) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCmY-0008O7-Ty; Wed, 28 Jun 2017 09:13:23 -0400 Received: from correu-2.ac.upc.es (correu-2.ac.upc.es [147.83.30.92]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5SDDF7a027113; Wed, 28 Jun 2017 15:13:15 +0200 Received: from localhost (unknown [132.68.50.243]) by correu-2.ac.upc.es (Postfix) with ESMTPSA id A089F1E1; Wed, 28 Jun 2017 15:13:09 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Wed, 28 Jun 2017 16:13:08 +0300 Message-Id: <149865558836.17063.10744518168688659698.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149865219962.17063.10630533069463266646.stgit@frigg.lan> References: <149865219962.17063.10630533069463266646.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5SDDF7a027113 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v11 14/29] target/arm: [tcg] Port to DisasContextBase X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , "Emilio G. Cota" , "open list:ARM" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson --- target/arm/translate-a64.c | 119 ++++++++++++++++++++++------------------= ---- target/arm/translate.c | 114 +++++++++++++++++++++-------------------= -- target/arm/translate.h | 11 ++-- 3 files changed, 121 insertions(+), 123 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f9bd1a9679..4270ac3847 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -304,7 +304,7 @@ static void gen_exception_internal_insn(DisasContext *s= , int offset, int excp) { gen_a64_set_pc_im(s->pc - offset); gen_exception_internal(excp); - s->is_jmp =3D DISAS_EXC; + s->base.is_jmp =3D DISAS_EXC; } =20 static void gen_exception_insn(DisasContext *s, int offset, int excp, @@ -312,7 +312,7 @@ static void gen_exception_insn(DisasContext *s, int off= set, int excp, { gen_a64_set_pc_im(s->pc - offset); gen_exception(excp, syndrome, target_el); - s->is_jmp =3D DISAS_EXC; + s->base.is_jmp =3D DISAS_EXC; } =20 static void gen_ss_advance(DisasContext *s) @@ -340,7 +340,7 @@ static void gen_step_complete_exception(DisasContext *s) gen_ss_advance(s); gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex), default_exception_el(s)); - s->is_jmp =3D DISAS_EXC; + s->base.is_jmp =3D DISAS_EXC; } =20 static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest) @@ -348,13 +348,13 @@ static inline bool use_goto_tb(DisasContext *s, int n= , uint64_t dest) /* No direct tb linking with singlestep (either QEMU's or the ARM * debug architecture kind) or deterministic io */ - if (s->singlestep_enabled || s->ss_active || (s->tb->cflags & CF_LAST_= IO)) { + if (s->base.singlestep_enabled || s->ss_active || (s->base.tb->cflags = & CF_LAST_IO)) { return false; } =20 #ifndef CONFIG_USER_ONLY /* Only link tbs from inside the same guest page */ - if ((s->tb->pc & TARGET_PAGE_MASK) !=3D (dest & TARGET_PAGE_MASK)) { + if ((s->base.tb->pc & TARGET_PAGE_MASK) !=3D (dest & TARGET_PAGE_MASK)= ) { return false; } #endif @@ -366,21 +366,21 @@ static inline void gen_goto_tb(DisasContext *s, int n= , uint64_t dest) { TranslationBlock *tb; =20 - tb =3D s->tb; + tb =3D s->base.tb; if (use_goto_tb(s, n, dest)) { tcg_gen_goto_tb(n); gen_a64_set_pc_im(dest); tcg_gen_exit_tb((intptr_t)tb + n); - s->is_jmp =3D DISAS_TB_JUMP; + s->base.is_jmp =3D DISAS_TB_JUMP; } else { gen_a64_set_pc_im(dest); if (s->ss_active) { gen_step_complete_exception(s); - } else if (s->singlestep_enabled) { + } else if (s->base.singlestep_enabled) { gen_exception_internal(EXCP_DEBUG); } else { tcg_gen_lookup_and_goto_ptr(cpu_pc); - s->is_jmp =3D DISAS_TB_JUMP; + s->base.is_jmp =3D DISAS_TB_JUMP; } } } @@ -1331,16 +1331,16 @@ static void handle_hint(DisasContext *s, uint32_t i= nsn, case 0: /* NOP */ return; case 3: /* WFI */ - s->is_jmp =3D DISAS_WFI; + s->base.is_jmp =3D DISAS_WFI; return; case 1: /* YIELD */ if (!parallel_cpus) { - s->is_jmp =3D DISAS_YIELD; + s->base.is_jmp =3D DISAS_YIELD; } return; case 2: /* WFE */ if (!parallel_cpus) { - s->is_jmp =3D DISAS_WFE; + s->base.is_jmp =3D DISAS_WFE; } return; case 4: /* SEV */ @@ -1393,7 +1393,7 @@ static void handle_sync(DisasContext *s, uint32_t ins= n, * a self-modified code correctly and also to take * any pending interrupts immediately. */ - s->is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE; return; default: unallocated_encoding(s); @@ -1424,7 +1424,7 @@ static void handle_msr_i(DisasContext *s, uint32_t in= sn, tcg_temp_free_i32(tcg_op); /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. = */ gen_a64_set_pc_im(s->pc); - s->is_jmp =3D (op =3D=3D 0x1f ? DISAS_EXIT : DISAS_JUMP); + s->base.is_jmp =3D (op =3D=3D 0x1f ? DISAS_EXIT : DISAS_JUMP); break; } default: @@ -1559,7 +1559,7 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, break; } =20 - if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { + if ((s->base.tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { gen_io_start(); } =20 @@ -1590,16 +1590,16 @@ static void handle_sys(DisasContext *s, uint32_t in= sn, bool isread, } } =20 - if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { + if ((s->base.tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { /* I/O operations must end the TB here (whether read or write) */ gen_io_end(); - s->is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE; } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { /* We default to ending the TB on a coprocessor register write, * but allow this to be suppressed by the register definition * (usually only necessary to work around guest bugs). */ - s->is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE; } } =20 @@ -1788,7 +1788,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint3= 2_t insn) return; } gen_helper_exception_return(cpu_env); - s->is_jmp =3D DISAS_JUMP; + s->base.is_jmp =3D DISAS_JUMP; return; case 5: /* DRPS */ if (rn !=3D 0x1f) { @@ -1802,7 +1802,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint3= 2_t insn) return; } =20 - s->is_jmp =3D DISAS_JUMP; + s->base.is_jmp =3D DISAS_JUMP; } =20 /* C3.2 Branches, exception generating and system instructions */ @@ -11190,23 +11190,23 @@ static void disas_a64_insn(CPUARMState *env, Disa= sContext *s) free_tmp_a64(s); } =20 -void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb) +void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, + TranslationBlock *tb) { CPUARMState *env =3D cs->env_ptr; ARMCPU *cpu =3D arm_env_get_cpu(env); - DisasContext dc1, *dc =3D &dc1; - target_ulong pc_start; + DisasContext *dc =3D container_of(dcbase, DisasContext, base); target_ulong next_page_start; - int num_insns; int max_insns; =20 - pc_start =3D tb->pc; + dc->base.tb =3D tb; + dc->base.pc_first =3D dc->base.tb->pc; + dc->base.pc_next =3D dc->base.pc_first; + dc->base.is_jmp =3D DISAS_NEXT; + dc->base.num_insns =3D 0; + dc->base.singlestep_enabled =3D cs->singlestep_enabled; =20 - dc->tb =3D tb; - - dc->is_jmp =3D DISAS_NEXT; - dc->pc =3D pc_start; - dc->singlestep_enabled =3D cs->singlestep_enabled; + dc->pc =3D dc->base.pc_first; dc->condjmp =3D 0; =20 dc->aarch64 =3D 1; @@ -11217,17 +11217,17 @@ void gen_intermediate_code_a64(CPUState *cs, Tran= slationBlock *tb) !arm_el_is_aa64(env, 3); dc->thumb =3D 0; dc->sctlr_b =3D 0; - dc->be_data =3D ARM_TBFLAG_BE_DATA(tb->flags) ? MO_BE : MO_LE; + dc->be_data =3D ARM_TBFLAG_BE_DATA(dc->base.tb->flags) ? MO_BE : MO_LE; dc->condexec_mask =3D 0; dc->condexec_cond =3D 0; - dc->mmu_idx =3D core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(tb->flags)); - dc->tbi0 =3D ARM_TBFLAG_TBI0(tb->flags); - dc->tbi1 =3D ARM_TBFLAG_TBI1(tb->flags); + dc->mmu_idx =3D core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(dc->base.tb= ->flags)); + dc->tbi0 =3D ARM_TBFLAG_TBI0(dc->base.tb->flags); + dc->tbi1 =3D ARM_TBFLAG_TBI1(dc->base.tb->flags); dc->current_el =3D arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user =3D (dc->current_el =3D=3D 0); #endif - dc->fp_excp_el =3D ARM_TBFLAG_FPEXC_EL(tb->flags); + dc->fp_excp_el =3D ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags); dc->vec_len =3D 0; dc->vec_stride =3D 0; dc->cp_regs =3D cpu->cp_regs; @@ -11248,16 +11248,15 @@ void gen_intermediate_code_a64(CPUState *cs, Tran= slationBlock *tb) * emit code to generate a software step exception * end the TB */ - dc->ss_active =3D ARM_TBFLAG_SS_ACTIVE(tb->flags); - dc->pstate_ss =3D ARM_TBFLAG_PSTATE_SS(tb->flags); + dc->ss_active =3D ARM_TBFLAG_SS_ACTIVE(dc->base.tb->flags); + dc->pstate_ss =3D ARM_TBFLAG_PSTATE_SS(dc->base.tb->flags); dc->is_ldex =3D false; dc->ss_same_el =3D (arm_debug_target_el(env) =3D=3D dc->current_el); =20 init_tmp_a64_array(dc); =20 - next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; - num_insns =3D 0; - max_insns =3D tb->cflags & CF_COUNT_MASK; + next_page_start =3D (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PA= GE_SIZE; + max_insns =3D dc->base.tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } @@ -11270,9 +11269,9 @@ void gen_intermediate_code_a64(CPUState *cs, Transl= ationBlock *tb) tcg_clear_temp_count(); =20 do { + dc->base.num_insns++; dc->insn_start_idx =3D tcg_op_buf_count(); tcg_gen_insn_start(dc->pc, 0, 0); - num_insns++; =20 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; @@ -11282,14 +11281,14 @@ void gen_intermediate_code_a64(CPUState *cs, Tran= slationBlock *tb) gen_a64_set_pc_im(dc->pc); gen_helper_check_breakpoints(cpu_env); /* End the TB early; it likely won't be executed */ - dc->is_jmp =3D DISAS_UPDATE; + dc->base.is_jmp =3D DISAS_UPDATE; } else { gen_exception_internal_insn(dc, 0, EXCP_DEBUG); /* The address covered by the breakpoint must be - included in [tb->pc, tb->pc + tb->size) in order + included in [dc->base.tb->pc, dc->base.tb->pc += dc->base.tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that the logic setting - tb->size below does the right thing. */ + dc->base.tb->size below does the right thing. = */ dc->pc +=3D 4; goto done_generating; } @@ -11298,7 +11297,7 @@ void gen_intermediate_code_a64(CPUState *cs, Transl= ationBlock *tb) } } =20 - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (dc->base.num_insns =3D=3D max_insns && (dc->base.tb->cflags & = CF_LAST_IO)) { gen_io_start(); } =20 @@ -11313,10 +11312,10 @@ void gen_intermediate_code_a64(CPUState *cs, Tran= slationBlock *tb) * "did not step an insn" case, and so the syndrome ISV and EX * bits should be zero. */ - assert(num_insns =3D=3D 1); + assert(dc->base.num_insns =3D=3D 1); gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), default_exception_el(dc)); - dc->is_jmp =3D DISAS_EXC; + dc->base.is_jmp =3D DISAS_EXC; break; } =20 @@ -11332,26 +11331,26 @@ void gen_intermediate_code_a64(CPUState *cs, Tran= slationBlock *tb) * Also stop translation when a page boundary is reached. This * ensures prefetch aborts occur at the right place. */ - } while (!dc->is_jmp && !tcg_op_buf_full() && + } while (!dc->base.is_jmp && !tcg_op_buf_full() && !cs->singlestep_enabled && !singlestep && !dc->ss_active && dc->pc < next_page_start && - num_insns < max_insns); + dc->base.num_insns < max_insns); =20 - if (tb->cflags & CF_LAST_IO) { + if (dc->base.tb->cflags & CF_LAST_IO) { gen_io_end(); } =20 if (unlikely(cs->singlestep_enabled || dc->ss_active) - && dc->is_jmp !=3D DISAS_EXC) { + && dc->base.is_jmp !=3D DISAS_EXC) { /* Note that this means single stepping WFI doesn't halt the CPU. * For conditional branch insns this is harmless unreachable code = as * gen_goto_tb() has already handled emitting the debug exception * (and thus a tb-jump is not possible when singlestepping). */ - assert(dc->is_jmp !=3D DISAS_TB_JUMP); - if (dc->is_jmp !=3D DISAS_JUMP) { + assert(dc->base.is_jmp !=3D DISAS_TB_JUMP); + if (dc->base.is_jmp !=3D DISAS_JUMP) { gen_a64_set_pc_im(dc->pc); } if (cs->singlestep_enabled) { @@ -11360,7 +11359,7 @@ void gen_intermediate_code_a64(CPUState *cs, Transl= ationBlock *tb) gen_step_complete_exception(dc); } } else { - switch (dc->is_jmp) { + switch (dc->base.is_jmp) { case DISAS_NEXT: gen_goto_tb(dc, 1, dc->pc); break; @@ -11401,20 +11400,20 @@ void gen_intermediate_code_a64(CPUState *cs, Tran= slationBlock *tb) } =20 done_generating: - gen_tb_end(tb, num_insns); + gen_tb_end(tb, dc->base.num_insns); =20 #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && - qemu_log_in_addr_range(pc_start)) { + qemu_log_in_addr_range(dc->base.pc_first)) { qemu_log_lock(); qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, dc->pc - pc_start, + qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); + log_target_disas(cs, dc->base.pc_first, dc->pc - dc->base.pc_first, 4 | (bswap_code(dc->sctlr_b) ? 2 : 0)); qemu_log("\n"); qemu_log_unlock(); } #endif - tb->size =3D dc->pc - pc_start; - tb->icount =3D num_insns; + dc->base.tb->size =3D dc->pc - dc->base.pc_first; + dc->base.tb->icount =3D dc->base.num_insns; } diff --git a/target/arm/translate.c b/target/arm/translate.c index 032a263604..17bc9687b7 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -224,7 +224,7 @@ static void store_reg(DisasContext *s, int reg, TCGv_i3= 2 var) * We choose to ignore [1:0] in ARM mode for all architecture vers= ions. */ tcg_gen_andi_i32(var, var, s->thumb ? ~1 : ~3); - s->is_jmp =3D DISAS_JUMP; + s->base.is_jmp =3D DISAS_JUMP; } tcg_gen_mov_i32(cpu_R[reg], var); tcg_temp_free_i32(var); @@ -297,7 +297,7 @@ static void gen_step_complete_exception(DisasContext *s) gen_ss_advance(s); gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex), default_exception_el(s)); - s->is_jmp =3D DISAS_EXC; + s->base.is_jmp =3D DISAS_EXC; } =20 static void gen_singlestep_exception(DisasContext *s) @@ -321,7 +321,7 @@ static inline bool is_singlestepping(DisasContext *s) * misnamed as it only means "one instruction per TB" and doesn't * affect the code we generate. */ - return s->singlestep_enabled || s->ss_active; + return s->base.singlestep_enabled || s->ss_active; } =20 static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b) @@ -928,7 +928,7 @@ static inline void gen_bx_im(DisasContext *s, uint32_t = addr) { TCGv_i32 tmp; =20 - s->is_jmp =3D DISAS_JUMP; + s->base.is_jmp =3D DISAS_JUMP; if (s->thumb !=3D (addr & 1)) { tmp =3D tcg_temp_new_i32(); tcg_gen_movi_i32(tmp, addr & 1); @@ -941,7 +941,7 @@ static inline void gen_bx_im(DisasContext *s, uint32_t = addr) /* Set PC and Thumb state from var. var is marked as dead. */ static inline void gen_bx(DisasContext *s, TCGv_i32 var) { - s->is_jmp =3D DISAS_JUMP; + s->base.is_jmp =3D DISAS_JUMP; tcg_gen_andi_i32(cpu_R[15], var, ~1); tcg_gen_andi_i32(var, var, 1); store_cpu_field(var, thumb); @@ -955,11 +955,11 @@ static inline void gen_bx(DisasContext *s, TCGv_i32 v= ar) static inline void gen_bx_excret(DisasContext *s, TCGv_i32 var) { /* Generate the same code here as for a simple bx, but flag via - * s->is_jmp that we need to do the rest of the work later. + * s->base.is_jmp that we need to do the rest of the work later. */ gen_bx(s, var); if (s->v7m_handler_mode && arm_dc_feature(s, ARM_FEATURE_M)) { - s->is_jmp =3D DISAS_BX_EXCRET; + s->base.is_jmp =3D DISAS_BX_EXCRET; } } =20 @@ -1159,7 +1159,7 @@ static inline void gen_hvc(DisasContext *s, int imm16) */ s->svc_imm =3D imm16; gen_set_pc_im(s, s->pc); - s->is_jmp =3D DISAS_HVC; + s->base.is_jmp =3D DISAS_HVC; } =20 static inline void gen_smc(DisasContext *s) @@ -1174,7 +1174,7 @@ static inline void gen_smc(DisasContext *s) gen_helper_pre_smc(cpu_env, tmp); tcg_temp_free_i32(tmp); gen_set_pc_im(s, s->pc); - s->is_jmp =3D DISAS_SMC; + s->base.is_jmp =3D DISAS_SMC; } =20 static void gen_exception_internal_insn(DisasContext *s, int offset, int e= xcp) @@ -1182,7 +1182,7 @@ static void gen_exception_internal_insn(DisasContext = *s, int offset, int excp) gen_set_condexec(s); gen_set_pc_im(s, s->pc - offset); gen_exception_internal(excp); - s->is_jmp =3D DISAS_EXC; + s->base.is_jmp =3D DISAS_EXC; } =20 static void gen_exception_insn(DisasContext *s, int offset, int excp, @@ -1191,14 +1191,14 @@ static void gen_exception_insn(DisasContext *s, int= offset, int excp, gen_set_condexec(s); gen_set_pc_im(s, s->pc - offset); gen_exception(excp, syn, target_el); - s->is_jmp =3D DISAS_EXC; + s->base.is_jmp =3D DISAS_EXC; } =20 /* Force a TB lookup after an instruction that changes the CPU state. */ static inline void gen_lookup_tb(DisasContext *s) { tcg_gen_movi_i32(cpu_R[15], s->pc & ~1); - s->is_jmp =3D DISAS_EXIT; + s->base.is_jmp =3D DISAS_EXIT; } =20 static inline void gen_hlt(DisasContext *s, int imm) @@ -4143,7 +4143,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) static inline bool use_goto_tb(DisasContext *s, target_ulong dest) { #ifndef CONFIG_USER_ONLY - return (s->tb->pc & TARGET_PAGE_MASK) =3D=3D (dest & TARGET_PAGE_MASK)= || + return (s->base.tb->pc & TARGET_PAGE_MASK) =3D=3D (dest & TARGET_PAGE_= MASK) || ((s->pc - 1) & TARGET_PAGE_MASK) =3D=3D (dest & TARGET_PAGE_MAS= K); #else return true; @@ -4163,7 +4163,7 @@ static void gen_goto_tb(DisasContext *s, int n, targe= t_ulong dest) if (use_goto_tb(s, dest)) { tcg_gen_goto_tb(n); gen_set_pc_im(s, dest); - tcg_gen_exit_tb((uintptr_t)s->tb + n); + tcg_gen_exit_tb((uintptr_t)s->base.tb + n); } else { gen_set_pc_im(s, dest); gen_goto_ptr(); @@ -4179,7 +4179,7 @@ static inline void gen_jmp (DisasContext *s, uint32_t= dest) gen_bx_im(s, dest); } else { gen_goto_tb(s, 0, dest); - s->is_jmp =3D DISAS_TB_JUMP; + s->base.is_jmp =3D DISAS_TB_JUMP; } } =20 @@ -4430,7 +4430,7 @@ static void gen_msr_banked(DisasContext *s, int r, in= t sysm, int rn) tcg_temp_free_i32(tcg_tgtmode); tcg_temp_free_i32(tcg_regno); tcg_temp_free_i32(tcg_reg); - s->is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE; } =20 static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn) @@ -4452,7 +4452,7 @@ static void gen_mrs_banked(DisasContext *s, int r, in= t sysm, int rn) tcg_temp_free_i32(tcg_tgtmode); tcg_temp_free_i32(tcg_regno); store_reg(s, rn, tcg_reg); - s->is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE; } =20 /* Store value to PC as for an exception return (ie don't @@ -4475,7 +4475,7 @@ static void gen_rfe(DisasContext *s, TCGv_i32 pc, TCG= v_i32 cpsr) */ gen_helper_cpsr_write_eret(cpu_env, cpsr); tcg_temp_free_i32(cpsr); - s->is_jmp =3D DISAS_JUMP; + s->base.is_jmp =3D DISAS_JUMP; } =20 /* Generate an old-style exception return. Marks pc as dead. */ @@ -4498,17 +4498,17 @@ static void gen_nop_hint(DisasContext *s, int val) case 1: /* yield */ if (!parallel_cpus) { gen_set_pc_im(s, s->pc); - s->is_jmp =3D DISAS_YIELD; + s->base.is_jmp =3D DISAS_YIELD; } break; case 3: /* wfi */ gen_set_pc_im(s, s->pc); - s->is_jmp =3D DISAS_WFI; + s->base.is_jmp =3D DISAS_WFI; break; case 2: /* wfe */ if (!parallel_cpus) { gen_set_pc_im(s, s->pc); - s->is_jmp =3D DISAS_WFE; + s->base.is_jmp =3D DISAS_WFE; } break; case 4: /* sev */ @@ -7647,13 +7647,13 @@ static int disas_coproc_insn(DisasContext *s, uint3= 2_t insn) return 1; } gen_set_pc_im(s, s->pc); - s->is_jmp =3D DISAS_WFI; + s->base.is_jmp =3D DISAS_WFI; return 0; default: break; } =20 - if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { + if ((s->base.tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)= ) { gen_io_start(); } =20 @@ -7744,7 +7744,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_= t insn) } } =20 - if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { + if ((s->base.tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)= ) { /* I/O operations must end the TB here (whether read or write)= */ gen_io_end(); gen_lookup_tb(s); @@ -8058,7 +8058,7 @@ static void gen_srs(DisasContext *s, tcg_temp_free_i32(tmp); } tcg_temp_free_i32(addr); - s->is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE; } =20 static void disas_arm_insn(DisasContext *s, unsigned int insn) @@ -8146,7 +8146,7 @@ static void disas_arm_insn(DisasContext *s, unsigned = int insn) /* setend */ if (((insn >> 9) & 1) !=3D !!(s->be_data =3D=3D MO_BE)) { gen_helper_setend(cpu_env); - s->is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE; } return; } else if ((insn & 0x0fffff00) =3D=3D 0x057ff000) { @@ -9519,7 +9519,7 @@ static void disas_arm_insn(DisasContext *s, unsigned = int insn) tmp =3D load_cpu_field(spsr); gen_helper_cpsr_write_eret(cpu_env, tmp); tcg_temp_free_i32(tmp); - s->is_jmp =3D DISAS_JUMP; + s->base.is_jmp =3D DISAS_JUMP; } } break; @@ -9557,7 +9557,7 @@ static void disas_arm_insn(DisasContext *s, unsigned = int insn) /* swi */ gen_set_pc_im(s, s->pc); s->svc_imm =3D extract32(insn, 0, 24); - s->is_jmp =3D DISAS_SWI; + s->base.is_jmp =3D DISAS_SWI; break; default: illegal_op: @@ -11619,7 +11619,7 @@ static void disas_thumb_insn(CPUARMState *env, Disa= sContext *s) ARCH(6); if (((insn >> 3) & 1) !=3D !!(s->be_data =3D=3D MO_BE)) { gen_helper_setend(cpu_env); - s->is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE; } break; case 3: @@ -11713,7 +11713,7 @@ static void disas_thumb_insn(CPUARMState *env, Disa= sContext *s) /* swi */ gen_set_pc_im(s, s->pc); s->svc_imm =3D extract32(insn, 0, 8); - s->is_jmp =3D DISAS_SWI; + s->base.is_jmp =3D DISAS_SWI; break; } /* generate a conditional jump to next instruction */ @@ -11792,9 +11792,7 @@ void gen_intermediate_code(CPUState *cpu, Translati= onBlock *tb) CPUARMState *env =3D cpu->env_ptr; ARMCPU *arm_cpu =3D arm_env_get_cpu(env); DisasContext dc1, *dc =3D &dc1; - target_ulong pc_start; target_ulong next_page_start; - int num_insns; int max_insns; bool end_of_page; =20 @@ -11804,17 +11802,18 @@ void gen_intermediate_code(CPUState *cpu, Transla= tionBlock *tb) * the A32/T32 complexity to do with conditional execution/IT blocks/e= tc. */ if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { - gen_intermediate_code_a64(cpu, tb); + gen_intermediate_code_a64(&dc->base, cpu, tb); return; } =20 - pc_start =3D tb->pc; + dc->base.tb =3D tb; + dc->base.pc_first =3D tb->pc; + dc->base.pc_next =3D dc->base.pc_first; + dc->base.is_jmp =3D DISAS_NEXT; + dc->base.num_insns =3D 0; + dc->base.singlestep_enabled =3D cpu->singlestep_enabled; =20 - dc->tb =3D tb; - - dc->is_jmp =3D DISAS_NEXT; - dc->pc =3D pc_start; - dc->singlestep_enabled =3D cpu->singlestep_enabled; + dc->pc =3D dc->base.pc_first; dc->condjmp =3D 0; =20 dc->aarch64 =3D 0; @@ -11871,8 +11870,7 @@ void gen_intermediate_code(CPUState *cpu, Translati= onBlock *tb) cpu_V1 =3D cpu_F1d; /* FIXME: cpu_M0 can probably be the same as cpu_V0. */ cpu_M0 =3D tcg_temp_new_i64(); - next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; - num_insns =3D 0; + next_page_start =3D (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PA= GE_SIZE; max_insns =3D tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; @@ -11924,11 +11922,11 @@ void gen_intermediate_code(CPUState *cpu, Transla= tionBlock *tb) store_cpu_field(tmp, condexec_bits); } do { + dc->base.num_insns++; dc->insn_start_idx =3D tcg_op_buf_count(); tcg_gen_insn_start(dc->pc, (dc->condexec_cond << 4) | (dc->condexec_mask >= > 1), 0); - num_insns++; =20 #ifdef CONFIG_USER_ONLY /* Intercept jump to the magic kernel page. */ @@ -11936,7 +11934,7 @@ void gen_intermediate_code(CPUState *cpu, Translati= onBlock *tb) /* We always get here via a jump, so know we are not in a conditional execution block. */ gen_exception_internal(EXCP_KERNEL_TRAP); - dc->is_jmp =3D DISAS_EXC; + dc->base.is_jmp =3D DISAS_EXC; break; } #endif @@ -11950,7 +11948,7 @@ void gen_intermediate_code(CPUState *cpu, Translati= onBlock *tb) gen_set_pc_im(dc, dc->pc); gen_helper_check_breakpoints(cpu_env); /* End the TB early; it's likely not going to be e= xecuted */ - dc->is_jmp =3D DISAS_UPDATE; + dc->base.is_jmp =3D DISAS_UPDATE; } else { gen_exception_internal_insn(dc, 0, EXCP_DEBUG); /* The address covered by the breakpoint must be @@ -11968,7 +11966,7 @@ void gen_intermediate_code(CPUState *cpu, Translati= onBlock *tb) } } =20 - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (dc->base.num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_I= O)) { gen_io_start(); } =20 @@ -11983,7 +11981,7 @@ void gen_intermediate_code(CPUState *cpu, Translati= onBlock *tb) * "did not step an insn" case, and so the syndrome ISV and EX * bits should be zero. */ - assert(num_insns =3D=3D 1); + assert(dc->base.num_insns =3D=3D 1); gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), default_exception_el(dc)); goto done_generating; @@ -12005,7 +12003,7 @@ void gen_intermediate_code(CPUState *cpu, Translati= onBlock *tb) disas_arm_insn(dc, insn); } =20 - if (dc->condjmp && !dc->is_jmp) { + if (dc->condjmp && !dc->base.is_jmp) { gen_set_label(dc->condlabel); dc->condjmp =3D 0; } @@ -12032,11 +12030,11 @@ void gen_intermediate_code(CPUState *cpu, Transla= tionBlock *tb) end_of_page =3D (dc->pc >=3D next_page_start) || ((dc->pc >=3D next_page_start - 3) && insn_crosses_page(env, d= c)); =20 - } while (!dc->is_jmp && !tcg_op_buf_full() && + } while (!dc->base.is_jmp && !tcg_op_buf_full() && !is_singlestepping(dc) && !singlestep && !end_of_page && - num_insns < max_insns); + dc->base.num_insns < max_insns); =20 if (tb->cflags & CF_LAST_IO) { if (dc->condjmp) { @@ -12051,7 +12049,7 @@ void gen_intermediate_code(CPUState *cpu, Translati= onBlock *tb) instruction was a conditional branch or trap, and the PC has already been written. */ gen_set_condexec(dc); - if (dc->is_jmp =3D=3D DISAS_BX_EXCRET) { + if (dc->base.is_jmp =3D=3D DISAS_BX_EXCRET) { /* Exception return branches need some special case code at the * end of the TB, which is complex enough that it has to * handle the single-step vs not and the condition-failed @@ -12060,7 +12058,7 @@ void gen_intermediate_code(CPUState *cpu, Translati= onBlock *tb) gen_bx_excret_final_code(dc); } else if (unlikely(is_singlestepping(dc))) { /* Unconditional and "condition passed" instruction codepath. */ - switch (dc->is_jmp) { + switch (dc->base.is_jmp) { case DISAS_SWI: gen_ss_advance(dc); gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb), @@ -12091,7 +12089,7 @@ void gen_intermediate_code(CPUState *cpu, Translati= onBlock *tb) - Hardware watchpoints. Hardware breakpoints have already been handled and skip this co= de. */ - switch(dc->is_jmp) { + switch(dc->base.is_jmp) { case DISAS_NEXT: gen_goto_tb(dc, 1, dc->pc); break; @@ -12148,22 +12146,22 @@ void gen_intermediate_code(CPUState *cpu, Transla= tionBlock *tb) } =20 done_generating: - gen_tb_end(tb, num_insns); + gen_tb_end(tb, dc->base.num_insns); =20 #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && - qemu_log_in_addr_range(pc_start)) { + qemu_log_in_addr_range(dc->base.pc_first)) { qemu_log_lock(); qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cpu, pc_start, dc->pc - pc_start, + qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); + log_target_disas(cpu, dc->base.pc_first, dc->pc - dc->base.pc_firs= t, dc->thumb | (dc->sctlr_b << 1)); qemu_log("\n"); qemu_log_unlock(); } #endif - tb->size =3D dc->pc - pc_start; - tb->icount =3D num_insns; + tb->size =3D dc->pc - dc->base.pc_first; + tb->icount =3D dc->base.num_insns; } =20 static const char *cpu_mode_names[16] =3D { diff --git a/target/arm/translate.h b/target/arm/translate.h index aba3f44c9f..6fe40a344a 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -6,9 +6,10 @@ =20 /* internal defines */ typedef struct DisasContext { + DisasContextBase base; + target_ulong pc; uint32_t insn; - int is_jmp; /* Nonzero if this instruction has been conditionally skipped. */ int condjmp; /* The label that will be jumped to when the instruction is skipped. = */ @@ -16,8 +17,6 @@ typedef struct DisasContext { /* Thumb-2 conditional execution bits. */ int condexec_mask; int condexec_cond; - struct TranslationBlock *tb; - int singlestep_enabled; int thumb; int sctlr_b; TCGMemOp be_data; @@ -152,7 +151,8 @@ static void disas_set_insn_syndrome(DisasContext *s, ui= nt32_t syn) =20 #ifdef TARGET_AARCH64 void a64_translate_init(void); -void gen_intermediate_code_a64(CPUState *cpu, TranslationBlock *tb); +void gen_intermediate_code_a64(DisasContextBase *db, CPUState *cpu, + TranslationBlock *tb); void gen_a64_set_pc_im(uint64_t val); void aarch64_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags); @@ -161,7 +161,8 @@ static inline void a64_translate_init(void) { } =20 -static inline void gen_intermediate_code_a64(CPUState *cpu, TranslationBlo= ck *tb) +static inline void gen_intermediate_code_a64(DisasContextBase *db, CPUStat= e *cpu, + TranslationBlock *tb) { } =20 From nobody Sat May 4 11:44:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498655908117637.3456767183694; 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Wed, 28 Jun 2017 15:17:11 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Wed, 28 Jun 2017 16:17:10 +0300 Message-Id: <149865583044.17063.6916936084139965036.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149865219962.17063.10630533069463266646.stgit@frigg.lan> References: <149865219962.17063.10630533069463266646.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5SDHHVa027203 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v11 15/29] target/arm: [tcg] Port to init_disas_context X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , "Emilio G. Cota" , "open list:ARM" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson --- target/arm/translate.c | 85 +++++++++++++++++++++++++++-----------------= ---- 1 file changed, 47 insertions(+), 38 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 17bc9687b7..23a07fc2c6 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11786,32 +11786,12 @@ static bool insn_crosses_page(CPUARMState *env, D= isasContext *s) return false; } =20 -/* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) +static void arm_trblock_init_disas_context(DisasContextBase *dcbase, + CPUState *cpu) { + DisasContext *dc =3D container_of(dcbase, DisasContext, base); CPUARMState *env =3D cpu->env_ptr; ARMCPU *arm_cpu =3D arm_env_get_cpu(env); - DisasContext dc1, *dc =3D &dc1; - target_ulong next_page_start; - int max_insns; - bool end_of_page; - - /* generate intermediate code */ - - /* The A64 decoder has its own top level loop, because it doesn't need - * the A32/T32 complexity to do with conditional execution/IT blocks/e= tc. - */ - if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { - gen_intermediate_code_a64(&dc->base, cpu, tb); - return; - } - - dc->base.tb =3D tb; - dc->base.pc_first =3D tb->pc; - dc->base.pc_next =3D dc->base.pc_first; - dc->base.is_jmp =3D DISAS_NEXT; - dc->base.num_insns =3D 0; - dc->base.singlestep_enabled =3D cpu->singlestep_enabled; =20 dc->pc =3D dc->base.pc_first; dc->condjmp =3D 0; @@ -11822,23 +11802,23 @@ void gen_intermediate_code(CPUState *cpu, Transla= tionBlock *tb) */ dc->secure_routed_to_el3 =3D arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3); - dc->thumb =3D ARM_TBFLAG_THUMB(tb->flags); - dc->sctlr_b =3D ARM_TBFLAG_SCTLR_B(tb->flags); - dc->be_data =3D ARM_TBFLAG_BE_DATA(tb->flags) ? MO_BE : MO_LE; - dc->condexec_mask =3D (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1; - dc->condexec_cond =3D ARM_TBFLAG_CONDEXEC(tb->flags) >> 4; - dc->mmu_idx =3D core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(tb->flags)); + dc->thumb =3D ARM_TBFLAG_THUMB(dc->base.tb->flags); + dc->sctlr_b =3D ARM_TBFLAG_SCTLR_B(dc->base.tb->flags); + dc->be_data =3D ARM_TBFLAG_BE_DATA(dc->base.tb->flags) ? MO_BE : MO_LE; + dc->condexec_mask =3D (ARM_TBFLAG_CONDEXEC(dc->base.tb->flags) & 0xf) = << 1; + dc->condexec_cond =3D ARM_TBFLAG_CONDEXEC(dc->base.tb->flags) >> 4; + dc->mmu_idx =3D core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(dc->base.tb= ->flags)); dc->current_el =3D arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user =3D (dc->current_el =3D=3D 0); #endif - dc->ns =3D ARM_TBFLAG_NS(tb->flags); - dc->fp_excp_el =3D ARM_TBFLAG_FPEXC_EL(tb->flags); - dc->vfp_enabled =3D ARM_TBFLAG_VFPEN(tb->flags); - dc->vec_len =3D ARM_TBFLAG_VECLEN(tb->flags); - dc->vec_stride =3D ARM_TBFLAG_VECSTRIDE(tb->flags); - dc->c15_cpar =3D ARM_TBFLAG_XSCALE_CPAR(tb->flags); - dc->v7m_handler_mode =3D ARM_TBFLAG_HANDLER(tb->flags); + dc->ns =3D ARM_TBFLAG_NS(dc->base.tb->flags); + dc->fp_excp_el =3D ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags); + dc->vfp_enabled =3D ARM_TBFLAG_VFPEN(dc->base.tb->flags); + dc->vec_len =3D ARM_TBFLAG_VECLEN(dc->base.tb->flags); + dc->vec_stride =3D ARM_TBFLAG_VECSTRIDE(dc->base.tb->flags); + dc->c15_cpar =3D ARM_TBFLAG_XSCALE_CPAR(dc->base.tb->flags); + dc->v7m_handler_mode =3D ARM_TBFLAG_HANDLER(dc->base.tb->flags); dc->cp_regs =3D arm_cpu->cp_regs; dc->features =3D env->features; =20 @@ -11857,10 +11837,39 @@ void gen_intermediate_code(CPUState *cpu, Transla= tionBlock *tb) * emit code to generate a software step exception * end the TB */ - dc->ss_active =3D ARM_TBFLAG_SS_ACTIVE(tb->flags); - dc->pstate_ss =3D ARM_TBFLAG_PSTATE_SS(tb->flags); + dc->ss_active =3D ARM_TBFLAG_SS_ACTIVE(dc->base.tb->flags); + dc->pstate_ss =3D ARM_TBFLAG_PSTATE_SS(dc->base.tb->flags); dc->is_ldex =3D false; dc->ss_same_el =3D false; /* Can't be true since EL_d must be AArch64 = */ +} + +/* generate intermediate code for basic block 'tb'. */ +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) +{ + CPUARMState *env =3D cpu->env_ptr; + DisasContext dc1, *dc =3D &dc1; + target_ulong next_page_start; + int max_insns; + bool end_of_page; + + /* generate intermediate code */ + + /* The A64 decoder has its own top level loop, because it doesn't need + * the A32/T32 complexity to do with conditional execution/IT blocks/e= tc. + */ + if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { + gen_intermediate_code_a64(&dc->base, cpu, tb); + return; + } + + dc->base.tb =3D tb; + dc->base.pc_first =3D dc->base.tb->pc; + dc->base.pc_next =3D dc->base.pc_first; + dc->base.is_jmp =3D DISAS_NEXT; + dc->base.num_insns =3D 0; + dc->base.singlestep_enabled =3D cpu->singlestep_enabled; + arm_trblock_init_disas_context(&dc->base, cpu); + =20 cpu_F0s =3D tcg_temp_new_i32(); cpu_F1s =3D tcg_temp_new_i32(); From nobody Sat May 4 11:44:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498656171350338.0469245242664; Wed, 28 Jun 2017 06:22:51 -0700 (PDT) Received: from localhost ([::1]:33381 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCvd-0004LK-Pp for importer@patchew.org; Wed, 28 Jun 2017 09:22:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56372) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCuR-0003ir-GO for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:21:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQCuM-0005TG-JM for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:21:31 -0400 Received: from roura.ac.upc.es ([147.83.33.10]:60293) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCuM-0005So-6V; Wed, 28 Jun 2017 09:21:26 -0400 Received: from correu-2.ac.upc.es (correu-2.ac.upc.es [147.83.30.92]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5SDLJmS027342; Wed, 28 Jun 2017 15:21:19 +0200 Received: from localhost (unknown [132.68.50.243]) by correu-2.ac.upc.es (Postfix) with ESMTPSA id C3B511E0; Wed, 28 Jun 2017 15:21:13 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Wed, 28 Jun 2017 16:21:12 +0300 Message-Id: <149865607253.17063.18194249796068858104.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149865219962.17063.10630533069463266646.stgit@frigg.lan> References: <149865219962.17063.10630533069463266646.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5SDLJmS027342 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v11 16/29] target/arm: [tcg, a64] Port to init_disas_context X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , "Emilio G. Cota" , "open list:ARM" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson --- target/arm/translate-a64.c | 36 ++++++++++++++++++++++-------------- 1 file changed, 22 insertions(+), 14 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 4270ac3847..88624a726d 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11190,21 +11190,12 @@ static void disas_a64_insn(CPUARMState *env, Disa= sContext *s) free_tmp_a64(s); } =20 -void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, - TranslationBlock *tb) +static void aarch64_trblock_init_disas_context(DisasContextBase *dcbase, + CPUState *cpu) { - CPUARMState *env =3D cs->env_ptr; - ARMCPU *cpu =3D arm_env_get_cpu(env); DisasContext *dc =3D container_of(dcbase, DisasContext, base); - target_ulong next_page_start; - int max_insns; - - dc->base.tb =3D tb; - dc->base.pc_first =3D dc->base.tb->pc; - dc->base.pc_next =3D dc->base.pc_first; - dc->base.is_jmp =3D DISAS_NEXT; - dc->base.num_insns =3D 0; - dc->base.singlestep_enabled =3D cs->singlestep_enabled; + CPUARMState *env =3D cpu->env_ptr; + ARMCPU *arm_cpu =3D arm_env_get_cpu(env); =20 dc->pc =3D dc->base.pc_first; dc->condjmp =3D 0; @@ -11230,7 +11221,7 @@ void gen_intermediate_code_a64(DisasContextBase *dc= base, CPUState *cs, dc->fp_excp_el =3D ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags); dc->vec_len =3D 0; dc->vec_stride =3D 0; - dc->cp_regs =3D cpu->cp_regs; + dc->cp_regs =3D arm_cpu->cp_regs; dc->features =3D env->features; =20 /* Single step state. The code-generation logic here is: @@ -11254,6 +11245,23 @@ void gen_intermediate_code_a64(DisasContextBase *d= cbase, CPUState *cs, dc->ss_same_el =3D (arm_debug_target_el(env) =3D=3D dc->current_el); =20 init_tmp_a64_array(dc); +} + +void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, + TranslationBlock *tb) +{ + CPUARMState *env =3D cs->env_ptr; + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + target_ulong next_page_start; + int max_insns; + + dc->base.tb =3D tb; + dc->base.pc_first =3D dc->base.tb->pc; + dc->base.pc_next =3D dc->base.pc_first; + dc->base.is_jmp =3D DISAS_NEXT; + dc->base.num_insns =3D 0; + dc->base.singlestep_enabled =3D cs->singlestep_enabled; + aarch64_trblock_init_disas_context(&dc->base, cs); =20 next_page_start =3D (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PA= GE_SIZE; max_insns =3D dc->base.tb->cflags & CF_COUNT_MASK; From nobody Sat May 4 11:44:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498656383647228.7202031948989; Wed, 28 Jun 2017 06:26:23 -0700 (PDT) Received: from localhost ([::1]:33405 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCz7-0006Mf-GX for importer@patchew.org; Wed, 28 Jun 2017 09:26:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57582) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCyN-000627-HO for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:25:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQCyI-0007mc-I2 for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:25:35 -0400 Received: from roura.ac.upc.es ([147.83.33.10]:56132) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCyI-0007mA-6T; Wed, 28 Jun 2017 09:25:30 -0400 Received: from correu-2.ac.upc.es (correu-2.ac.upc.es [147.83.30.92]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5SDPL7r027456; Wed, 28 Jun 2017 15:25:21 +0200 Received: from localhost (unknown [132.68.50.243]) by correu-2.ac.upc.es (Postfix) with ESMTPSA id CBA081E3; Wed, 28 Jun 2017 15:25:15 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Wed, 28 Jun 2017 16:25:14 +0300 Message-Id: <149865631443.17063.7093785957776924619.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149865219962.17063.10630533069463266646.stgit@frigg.lan> References: <149865219962.17063.10630533069463266646.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5SDPL7r027456 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v11 17/29] target/arm: [tcg] Port to init_globals X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , "Emilio G. Cota" , "open list:ARM" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson --- target/arm/translate.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 23a07fc2c6..fc28cd45f7 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11843,6 +11843,18 @@ static void arm_trblock_init_disas_context(DisasCo= ntextBase *dcbase, dc->ss_same_el =3D false; /* Can't be true since EL_d must be AArch64 = */ } =20 +static void arm_trblock_init_globals(DisasContextBase *dcbase, CPUState *c= pu) +{ + cpu_F0s =3D tcg_temp_new_i32(); + cpu_F1s =3D tcg_temp_new_i32(); + cpu_F0d =3D tcg_temp_new_i64(); + cpu_F1d =3D tcg_temp_new_i64(); + cpu_V0 =3D cpu_F0d; + cpu_V1 =3D cpu_F1d; + /* FIXME: cpu_M0 can probably be the same as cpu_V0. */ + cpu_M0 =3D tcg_temp_new_i64(); +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { @@ -11871,14 +11883,7 @@ void gen_intermediate_code(CPUState *cpu, Translat= ionBlock *tb) arm_trblock_init_disas_context(&dc->base, cpu); =20 =20 - cpu_F0s =3D tcg_temp_new_i32(); - cpu_F1s =3D tcg_temp_new_i32(); - cpu_F0d =3D tcg_temp_new_i64(); - cpu_F1d =3D tcg_temp_new_i64(); - cpu_V0 =3D cpu_F0d; - cpu_V1 =3D cpu_F1d; - /* FIXME: cpu_M0 can probably be the same as cpu_V0. */ - cpu_M0 =3D tcg_temp_new_i64(); + arm_trblock_init_globals(&dc->base, cpu); next_page_start =3D (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PA= GE_SIZE; max_insns =3D tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { From nobody Sat May 4 11:44:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498656657173864.8204704049547; Wed, 28 Jun 2017 06:30:57 -0700 (PDT) Received: from localhost ([::1]:33421 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQD3T-00087E-W3 for importer@patchew.org; Wed, 28 Jun 2017 09:30:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58481) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQD2R-0007Qg-Uk for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:29:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQD2M-00021L-Va for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:29:47 -0400 Received: from roura.ac.upc.es ([147.83.33.10]:42529) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQD2M-00020e-ES; Wed, 28 Jun 2017 09:29:42 -0400 Received: from correu-2.ac.upc.es (correu-2.ac.upc.es [147.83.30.92]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5SDTZ0w027561; Wed, 28 Jun 2017 15:29:35 +0200 Received: from localhost (unknown [132.68.50.243]) by correu-2.ac.upc.es (Postfix) with ESMTPSA id C7C751E3; Wed, 28 Jun 2017 15:29:17 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Wed, 28 Jun 2017 16:29:16 +0300 Message-Id: <149865655643.17063.11835076868609448555.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149865219962.17063.10630533069463266646.stgit@frigg.lan> References: <149865219962.17063.10630533069463266646.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5SDTZ0w027561 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v11 18/29] target/arm: [tcg] Port to tb_start X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , "Emilio G. Cota" , "open list:ARM" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson --- target/arm/translate.c | 82 ++++++++++++++++++++++++++------------------= ---- 1 file changed, 44 insertions(+), 38 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index fc28cd45f7..029c4d3550 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11855,6 +11855,49 @@ static void arm_trblock_init_globals(DisasContextB= ase *dcbase, CPUState *cpu) cpu_M0 =3D tcg_temp_new_i64(); } =20 +static void arm_trblock_tb_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + /* A note on handling of the condexec (IT) bits: + * + * We want to avoid the overhead of having to write the updated condex= ec + * bits back to the CPUARMState for every instruction in an IT block. = So: + * (1) if the condexec bits are not already zero then we write + * zero back into the CPUARMState now. This avoids complications trying + * to do it at the end of the block. (For example if we don't do this + * it's hard to identify whether we can safely skip writing condexec + * at the end of the TB, which we definitely want to do for the case + * where a TB doesn't do anything with the IT state at all.) + * (2) if we are going to leave the TB then we call gen_set_condexec() + * which will write the correct value into CPUARMState if zero is wron= g. + * This is done both for leaving the TB at the end, and for leaving + * it because of an exception we know will happen, which is done in + * gen_exception_insn(). The latter is necessary because we need to + * leave the TB with the PC/IT state just prior to execution of the + * instruction which caused the exception. + * (3) if we leave the TB unexpectedly (eg a data abort on a load) + * then the CPUARMState will be wrong and we need to reset it. + * This is handled in the same way as restoration of the + * PC in these situations; we save the value of the condexec bits + * for each PC via tcg_gen_insn_start(), and restore_state_to_opc() + * then uses this to restore them after an exception. + * + * Note that there are no instructions which can read the condexec + * bits, and none which can write non-static values to them, so + * we don't need to care about whether CPUARMState is correct in the + * middle of a TB. + */ + + /* Reset the conditional execution bits immediately. This avoids + complications trying to do it at the end of the block. */ + if (dc->condexec_mask || dc->condexec_cond) { + TCGv_i32 tmp =3D tcg_temp_new_i32(); + tcg_gen_movi_i32(tmp, 0); + store_cpu_field(tmp, condexec_bits); + } +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { @@ -11896,45 +11939,8 @@ void gen_intermediate_code(CPUState *cpu, Translat= ionBlock *tb) gen_tb_start(tb); =20 tcg_clear_temp_count(); + arm_trblock_tb_start(&dc->base, cpu); =20 - /* A note on handling of the condexec (IT) bits: - * - * We want to avoid the overhead of having to write the updated condex= ec - * bits back to the CPUARMState for every instruction in an IT block. = So: - * (1) if the condexec bits are not already zero then we write - * zero back into the CPUARMState now. This avoids complications trying - * to do it at the end of the block. (For example if we don't do this - * it's hard to identify whether we can safely skip writing condexec - * at the end of the TB, which we definitely want to do for the case - * where a TB doesn't do anything with the IT state at all.) - * (2) if we are going to leave the TB then we call gen_set_condexec() - * which will write the correct value into CPUARMState if zero is wron= g. - * This is done both for leaving the TB at the end, and for leaving - * it because of an exception we know will happen, which is done in - * gen_exception_insn(). The latter is necessary because we need to - * leave the TB with the PC/IT state just prior to execution of the - * instruction which caused the exception. - * (3) if we leave the TB unexpectedly (eg a data abort on a load) - * then the CPUARMState will be wrong and we need to reset it. - * This is handled in the same way as restoration of the - * PC in these situations; we save the value of the condexec bits - * for each PC via tcg_gen_insn_start(), and restore_state_to_opc() - * then uses this to restore them after an exception. - * - * Note that there are no instructions which can read the condexec - * bits, and none which can write non-static values to them, so - * we don't need to care about whether CPUARMState is correct in the - * middle of a TB. - */ - - /* Reset the conditional execution bits immediately. This avoids - complications trying to do it at the end of the block. */ - if (dc->condexec_mask || dc->condexec_cond) - { - TCGv_i32 tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - store_cpu_field(tmp, condexec_bits); - } do { dc->base.num_insns++; dc->insn_start_idx =3D tcg_op_buf_count(); From nobody Sat May 4 11:44:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 14986569294399.691934699211515; Wed, 28 Jun 2017 06:35:29 -0700 (PDT) Received: from localhost ([::1]:33437 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQD7r-0001VX-6p for importer@patchew.org; Wed, 28 Jun 2017 09:35:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59453) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQD6C-0000ks-KV for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:33:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQD67-0004Nl-Ng for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:33:40 -0400 Received: from roura.ac.upc.es ([147.83.33.10]:42566) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQD67-0004N9-B4; Wed, 28 Jun 2017 09:33:35 -0400 Received: from correu-2.ac.upc.es (correu-2.ac.upc.es [147.83.30.92]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5SDXShi027675; Wed, 28 Jun 2017 15:33:28 +0200 Received: from localhost (unknown [132.68.50.243]) by correu-2.ac.upc.es (Postfix) with ESMTPSA id 23C851C4; Wed, 28 Jun 2017 15:33:23 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Wed, 28 Jun 2017 16:33:22 +0300 Message-Id: <149865680190.17063.16072451312204148936.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149865219962.17063.10630533069463266646.stgit@frigg.lan> References: <149865219962.17063.10630533069463266646.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5SDXShi027675 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v11 19/29] target/arm: [tcg] Port to insn_start X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , "Emilio G. Cota" , "open list:ARM" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson --- target/arm/translate.c | 34 ++++++++++++++++++++++------------ 1 file changed, 22 insertions(+), 12 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 029c4d3550..c7e188b50e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11898,6 +11898,26 @@ static void arm_trblock_tb_start(DisasContextBase = *dcbase, CPUState *cpu) } } =20 +static void arm_trblock_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + dc->insn_start_idx =3D tcg_op_buf_count(); + tcg_gen_insn_start(dc->pc, + (dc->condexec_cond << 4) | (dc->condexec_mask >> 1), + 0); + +#ifdef CONFIG_USER_ONLY + /* Intercept jump to the magic kernel page. */ + if (dc->pc >=3D 0xffff0000) { + /* We always get here via a jump, so know we are not in a + conditional execution block. */ + gen_exception_internal(EXCP_KERNEL_TRAP); + dc->base.is_jmp =3D DISAS_EXC; + } +#endif +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { @@ -11943,21 +11963,11 @@ void gen_intermediate_code(CPUState *cpu, Transla= tionBlock *tb) =20 do { dc->base.num_insns++; - dc->insn_start_idx =3D tcg_op_buf_count(); - tcg_gen_insn_start(dc->pc, - (dc->condexec_cond << 4) | (dc->condexec_mask >= > 1), - 0); + arm_trblock_insn_start(&dc->base, cpu); =20 -#ifdef CONFIG_USER_ONLY - /* Intercept jump to the magic kernel page. */ - if (dc->pc >=3D 0xffff0000) { - /* We always get here via a jump, so know we are not in a - conditional execution block. */ - gen_exception_internal(EXCP_KERNEL_TRAP); - dc->base.is_jmp =3D DISAS_EXC; + if (unlikely(dc->base.is_jmp > DISAS_NEXT)) { break; } -#endif =20 if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { CPUBreakpoint *bp; From nobody Sat May 4 11:44:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498657133346252.79236803038293; Wed, 28 Jun 2017 06:38:53 -0700 (PDT) Received: from localhost ([::1]:33456 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQDBC-0003kb-7m for importer@patchew.org; Wed, 28 Jun 2017 09:38:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60818) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQDA9-00038c-4g for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:37:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQDA5-0007I1-7d for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:37:45 -0400 Received: from roura.ac.upc.es ([147.83.33.10]:42347) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQDA4-0007Hg-QR; Wed, 28 Jun 2017 09:37:41 -0400 Received: from correu-2.ac.upc.es (correu-2.ac.upc.es [147.83.30.92]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5SDbVuA027772; Wed, 28 Jun 2017 15:37:36 +0200 Received: from localhost (unknown [132.68.50.243]) by correu-2.ac.upc.es (Postfix) with ESMTPSA id 201791E0; Wed, 28 Jun 2017 15:37:25 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Wed, 28 Jun 2017 16:37:23 +0300 Message-Id: <149865704378.17063.12646195470292499503.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149865219962.17063.10630533069463266646.stgit@frigg.lan> References: <149865219962.17063.10630533069463266646.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5SDbVuA027772 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v11 20/29] target/arm: [tcg, a64] Port to insn_start X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , "Emilio G. Cota" , "open list:ARM" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson --- target/arm/translate-a64.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 88624a726d..5784620642 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11247,6 +11247,14 @@ static void aarch64_trblock_init_disas_context(Dis= asContextBase *dcbase, init_tmp_a64_array(dc); } =20 +static void aarch64_trblock_insn_start(DisasContextBase *dcbase, CPUState = *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + dc->insn_start_idx =3D tcg_op_buf_count(); + tcg_gen_insn_start(dc->pc, 0, 0); +} + void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, TranslationBlock *tb) { @@ -11278,8 +11286,7 @@ void gen_intermediate_code_a64(DisasContextBase *dc= base, CPUState *cs, =20 do { dc->base.num_insns++; - dc->insn_start_idx =3D tcg_op_buf_count(); - tcg_gen_insn_start(dc->pc, 0, 0); + aarch64_trblock_insn_start(&dc->base, cs); =20 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; From nobody Sat May 4 11:44:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498657353203484.40450899381426; Wed, 28 Jun 2017 06:42:33 -0700 (PDT) Received: from localhost ([::1]:33474 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQDEj-00052B-Km for importer@patchew.org; Wed, 28 Jun 2017 09:42:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33537) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQDDw-0004iU-Qb for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:41:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQDDs-0000ag-RY for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:41:40 -0400 Received: from roura.ac.upc.es ([147.83.33.10]:35141) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQDDs-0000aP-El; Wed, 28 Jun 2017 09:41:36 -0400 Received: from correu-1.ac.upc.es (correu-1.ac.upc.es [147.83.30.91]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5SDfWei027919; Wed, 28 Jun 2017 15:41:32 +0200 Received: from localhost (unknown [132.68.50.243]) by correu-1.ac.upc.es (Postfix) with ESMTPSA id 0EBE6165; Wed, 28 Jun 2017 15:41:26 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Wed, 28 Jun 2017 16:41:26 +0300 Message-Id: <149865728578.17063.13455172137587126808.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149865219962.17063.10630533069463266646.stgit@frigg.lan> References: <149865219962.17063.10630533069463266646.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5SDfWei027919 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v11 21/29] target/arm: [tcg] Port to breakpoint_check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , "Emilio G. Cota" , "open list:ARM" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson --- target/arm/translate.c | 68 ++++++++++++++++++++++++++++++++------------= ---- 1 file changed, 46 insertions(+), 22 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index c7e188b50e..790eaa2164 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11918,6 +11918,32 @@ static void arm_trblock_insn_start(DisasContextBas= e *dcbase, CPUState *cpu) #endif } =20 +static BreakpointCheckType arm_trblock_breakpoint_check( + DisasContextBase *dcbase, CPUState *cpu, const CPUBreakpoint *bp) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + if (bp->flags & BP_CPU) { + gen_set_condexec(dc); + gen_set_pc_im(dc, dc->pc); + gen_helper_check_breakpoints(cpu_env); + /* End the TB early; it's likely not going to be executed */ + dc->base.is_jmp =3D DISAS_UPDATE; + return BC_HIT_INSN; + } else { + gen_exception_internal_insn(dc, 0, EXCP_DEBUG); + /* The address covered by the breakpoint must be + included in [tb->pc, tb->pc + tb->size) in order + to for it to be properly cleared -- thus we + increment the PC here so that the logic setting + tb->size below does the right thing. */ + /* TODO: Advance PC by correct instruction length to + * avoid disassembler error messages */ + dc->pc +=3D 2; + return BC_HIT_TB; + } +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { @@ -11965,36 +11991,34 @@ void gen_intermediate_code(CPUState *cpu, Transla= tionBlock *tb) dc->base.num_insns++; arm_trblock_insn_start(&dc->base, cpu); =20 - if (unlikely(dc->base.is_jmp > DISAS_NEXT)) { - break; - } - if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { CPUBreakpoint *bp; QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { - if (bp->pc =3D=3D dc->pc) { - if (bp->flags & BP_CPU) { - gen_set_condexec(dc); - gen_set_pc_im(dc, dc->pc); - gen_helper_check_breakpoints(cpu_env); - /* End the TB early; it's likely not going to be e= xecuted */ - dc->base.is_jmp =3D DISAS_UPDATE; - } else { - gen_exception_internal_insn(dc, 0, EXCP_DEBUG); - /* The address covered by the breakpoint must be - included in [tb->pc, tb->pc + tb->size) in order - to for it to be properly cleared -- thus we - increment the PC here so that the logic setting - tb->size below does the right thing. */ - /* TODO: Advance PC by correct instruction length = to - * avoid disassembler error messages */ - dc->pc +=3D 2; + if (bp->pc =3D=3D dc->base.pc_next) { + BreakpointCheckType bp_check =3D + arm_trblock_breakpoint_check(&dc->base, cpu, bp); + switch (bp_check) { + case BC_MISS: + /* Target ignored this breakpoint, go to next */ + break; + case BC_HIT_INSN: + /* Hit, keep translating */ + /* + * TODO: if we're never going to have more than one + * BP in a single address, we can simply use= a + * bool here. + */ + goto done_breakpoints; + case BC_HIT_TB: + /* Hit, end TB */ goto done_generating; + default: + g_assert_not_reached(); } - break; } } } + done_breakpoints: =20 if (dc->base.num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_I= O)) { gen_io_start(); From nobody Sat May 4 11:44:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498657592879914.6424532760273; Wed, 28 Jun 2017 06:46:32 -0700 (PDT) Received: from localhost ([::1]:33491 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQDIc-0007WR-Ks for importer@patchew.org; Wed, 28 Jun 2017 09:46:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34453) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQDHq-0007Cc-Og for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:45:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQDHm-0002K2-RZ for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:45:42 -0400 Received: from roura.ac.upc.es ([147.83.33.10]:32916) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQDHm-0002Je-FN; Wed, 28 Jun 2017 09:45:38 -0400 Received: from correu-2.ac.upc.es (correu-2.ac.upc.es [147.83.30.92]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5SDjYYI028020; Wed, 28 Jun 2017 15:45:34 +0200 Received: from localhost (unknown [132.68.50.243]) by correu-2.ac.upc.es (Postfix) with ESMTPSA id 087EB1E1; Wed, 28 Jun 2017 15:45:28 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Wed, 28 Jun 2017 16:45:27 +0300 Message-Id: <149865752773.17063.5160701222440538985.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149865219962.17063.10630533069463266646.stgit@frigg.lan> References: <149865219962.17063.10630533069463266646.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5SDjYYI028020 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v11 22/29] target/arm: [tcg, a64] Port to breakpoint_check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , "Emilio G. Cota" , "open list:ARM" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson --- target/arm/translate-a64.c | 58 +++++++++++++++++++++++++++++++++-------= ---- 1 file changed, 43 insertions(+), 15 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 5784620642..9c870f6d07 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11255,6 +11255,29 @@ static void aarch64_trblock_insn_start(DisasContex= tBase *dcbase, CPUState *cpu) tcg_gen_insn_start(dc->pc, 0, 0); } =20 +static BreakpointCheckType aarch64_trblock_breakpoint_check( + DisasContextBase *dcbase, CPUState *cpu, const CPUBreakpoint *bp) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + if (bp->flags & BP_CPU) { + gen_a64_set_pc_im(dc->pc); + gen_helper_check_breakpoints(cpu_env); + /* End the TB early; it likely won't be executed */ + dc->base.is_jmp =3D DISAS_UPDATE; + return BC_HIT_INSN; + } else { + gen_exception_internal_insn(dc, 0, EXCP_DEBUG); + /* The address covered by the breakpoint must be + included in [tb->pc, tb->pc + tb->size) in order + to for it to be properly cleared -- thus we + increment the PC here so that the logic setting + tb->size below does the right thing. */ + dc->pc +=3D 4; + return BC_HIT_TB; + } +} + void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, TranslationBlock *tb) { @@ -11291,26 +11314,31 @@ void gen_intermediate_code_a64(DisasContextBase *= dcbase, CPUState *cs, if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc =3D=3D dc->pc) { - if (bp->flags & BP_CPU) { - gen_a64_set_pc_im(dc->pc); - gen_helper_check_breakpoints(cpu_env); - /* End the TB early; it likely won't be executed */ - dc->base.is_jmp =3D DISAS_UPDATE; - } else { - gen_exception_internal_insn(dc, 0, EXCP_DEBUG); - /* The address covered by the breakpoint must be - included in [dc->base.tb->pc, dc->base.tb->pc += dc->base.tb->size) in order - to for it to be properly cleared -- thus we - increment the PC here so that the logic setting - dc->base.tb->size below does the right thing. = */ - dc->pc +=3D 4; + if (bp->pc =3D=3D dc->base.pc_next) { + BreakpointCheckType bp_check =3D + aarch64_trblock_breakpoint_check(&dc->base, cs, bp= ); + switch (bp_check) { + case BC_MISS: + /* Target ignored this breakpoint, go to next */ + break; + case BC_HIT_INSN: + /* Hit, keep translating */ + /* + * TODO: if we're never going to have more than one + * BP in a single address, we can simply use= a + * bool here. + */ + goto done_breakpoints; + case BC_HIT_TB: + /* Hit, end TB */ goto done_generating; + default: + g_assert_not_reached(); } - break; } } } + done_breakpoints: =20 if (dc->base.num_insns =3D=3D max_insns && (dc->base.tb->cflags & = CF_LAST_IO)) { gen_io_start(); From nobody Sat May 4 11:44:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 149865784753586.49011049351782; Wed, 28 Jun 2017 06:50:47 -0700 (PDT) Received: from localhost ([::1]:33505 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQDMi-0000al-7F for importer@patchew.org; Wed, 28 Jun 2017 09:50:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35676) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQDLo-0008Uv-4B for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:49:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQDLk-0004fP-0i for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:49:48 -0400 Received: from roura.ac.upc.es ([147.83.33.10]:49086) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQDLj-0004ev-ED; Wed, 28 Jun 2017 09:49:43 -0400 Received: from correu-2.ac.upc.es (correu-2.ac.upc.es [147.83.30.92]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5SDnac1028129; Wed, 28 Jun 2017 15:49:36 +0200 Received: from localhost (unknown [132.68.50.243]) by correu-2.ac.upc.es (Postfix) with ESMTPSA id D3CD91C4; Wed, 28 Jun 2017 15:49:30 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Wed, 28 Jun 2017 16:49:29 +0300 Message-Id: <149865776960.17063.4875279139522061160.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149865219962.17063.10630533069463266646.stgit@frigg.lan> References: <149865219962.17063.10630533069463266646.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5SDnac1028129 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v11 23/29] target/arm: [tcg] Port to translate_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , "Emilio G. Cota" , "open list:ARM" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova --- target/arm/translate.c | 147 +++++++++++++++++++++++++++-----------------= ---- target/arm/translate.h | 4 + 2 files changed, 88 insertions(+), 63 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 790eaa2164..7ab09a7e5f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11841,6 +11841,9 @@ static void arm_trblock_init_disas_context(DisasCon= textBase *dcbase, dc->pstate_ss =3D ARM_TBFLAG_PSTATE_SS(dc->base.tb->flags); dc->is_ldex =3D false; dc->ss_same_el =3D false; /* Can't be true since EL_d must be AArch64 = */ + + dc->next_page_start =3D + (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; } =20 static void arm_trblock_init_globals(DisasContextBase *dcbase, CPUState *c= pu) @@ -11944,14 +11947,82 @@ static BreakpointCheckType arm_trblock_breakpoint= _check( } } =20 +static target_ulong arm_trblock_translate_insn(DisasContextBase *dcbase, + CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + CPUARMState *env =3D cpu->env_ptr; + + if (dc->ss_active && !dc->pstate_ss) { + /* Singlestep state is Active-pending. + * If we're in this state at the start of a TB then either + * a) we just took an exception to an EL which is being debugged + * and this is the first insn in the exception handler + * b) debug exceptions were masked and we just unmasked them + * without changing EL (eg by clearing PSTATE.D) + * In either case we're going to take a swstep exception in the + * "did not step an insn" case, and so the syndrome ISV and EX + * bits should be zero. + */ + assert(dc->base.num_insns =3D=3D 1); + gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), + default_exception_el(dc)); + dc->base.is_jmp =3D DISAS_SKIP; + return dc->pc; + } + + if (dc->thumb) { + disas_thumb_insn(env, dc); + if (dc->condexec_mask) { + dc->condexec_cond =3D (dc->condexec_cond & 0xe) + | ((dc->condexec_mask >> 4) & 1); + dc->condexec_mask =3D (dc->condexec_mask << 1) & 0x1f; + if (dc->condexec_mask =3D=3D 0) { + dc->condexec_cond =3D 0; + } + } + } else { + unsigned int insn =3D arm_ldl_code(env, dc->pc, dc->sctlr_b); + dc->pc +=3D 4; + disas_arm_insn(dc, insn); + } + + if (dc->condjmp && !dc->base.is_jmp) { + gen_set_label(dc->condlabel); + dc->condjmp =3D 0; + } + + + /* Translation stops when a conditional branch is encountered. + * Otherwise the subsequent code could get translated several times. + * Also stop translation when a page boundary is reached. This + * ensures prefetch aborts occur at the right place. */ + + if (is_singlestepping(dc)) { + dc->base.is_jmp =3D DISAS_SS; + } else if ((dc->pc >=3D dc->next_page_start) || + ((dc->pc >=3D dc->next_page_start - 3) && + insn_crosses_page(env, dc))) { + /* We want to stop the TB if the next insn starts in a new page, + * or if it spans between this page and the next. This means that + * if we're looking at the last halfword in the page we need to + * see if it's a 16-bit Thumb insn (which will fit in this TB) + * or a 32-bit Thumb insn (which won't). + * This is to avoid generating a silly TB with a single 16-bit insn + * in it at the end of this page (which would execute correctly + * but isn't very efficient). + */ + return DISAS_PAGE_CROSS; + } + + return dc->pc; +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { - CPUARMState *env =3D cpu->env_ptr; DisasContext dc1, *dc =3D &dc1; - target_ulong next_page_start; int max_insns; - bool end_of_page; =20 /* generate intermediate code */ =20 @@ -11973,7 +12044,6 @@ void gen_intermediate_code(CPUState *cpu, Translati= onBlock *tb) =20 =20 arm_trblock_init_globals(&dc->base, cpu); - next_page_start =3D (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PA= GE_SIZE; max_insns =3D tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; @@ -12024,72 +12094,20 @@ void gen_intermediate_code(CPUState *cpu, Transla= tionBlock *tb) gen_io_start(); } =20 - if (dc->ss_active && !dc->pstate_ss) { - /* Singlestep state is Active-pending. - * If we're in this state at the start of a TB then either - * a) we just took an exception to an EL which is being debug= ged - * and this is the first insn in the exception handler - * b) debug exceptions were masked and we just unmasked them - * without changing EL (eg by clearing PSTATE.D) - * In either case we're going to take a swstep exception in the - * "did not step an insn" case, and so the syndrome ISV and EX - * bits should be zero. - */ - assert(dc->base.num_insns =3D=3D 1); - gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), - default_exception_el(dc)); - goto done_generating; - } - - if (dc->thumb) { - disas_thumb_insn(env, dc); - if (dc->condexec_mask) { - dc->condexec_cond =3D (dc->condexec_cond & 0xe) - | ((dc->condexec_mask >> 4) & 1); - dc->condexec_mask =3D (dc->condexec_mask << 1) & 0x1f; - if (dc->condexec_mask =3D=3D 0) { - dc->condexec_cond =3D 0; - } - } - } else { - unsigned int insn =3D arm_ldl_code(env, dc->pc, dc->sctlr_b); - dc->pc +=3D 4; - disas_arm_insn(dc, insn); - } - - if (dc->condjmp && !dc->base.is_jmp) { - gen_set_label(dc->condlabel); - dc->condjmp =3D 0; - } + dc->base.pc_next =3D arm_trblock_translate_insn(&dc->base, cpu); =20 if (tcg_check_temp_count()) { fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", dc->pc); } =20 - /* Translation stops when a conditional branch is encountered. - * Otherwise the subsequent code could get translated several time= s. - * Also stop translation when a page boundary is reached. This - * ensures prefetch aborts occur at the right place. */ - - /* We want to stop the TB if the next insn starts in a new page, - * or if it spans between this page and the next. This means that - * if we're looking at the last halfword in the page we need to - * see if it's a 16-bit Thumb insn (which will fit in this TB) - * or a 32-bit Thumb insn (which won't). - * This is to avoid generating a silly TB with a single 16-bit insn - * in it at the end of this page (which would execute correctly - * but isn't very efficient). - */ - end_of_page =3D (dc->pc >=3D next_page_start) || - ((dc->pc >=3D next_page_start - 3) && insn_crosses_page(env, d= c)); - - } while (!dc->base.is_jmp && !tcg_op_buf_full() && - !is_singlestepping(dc) && - !singlestep && - !end_of_page && - dc->base.num_insns < max_insns); + if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep || + dc->base.num_insns >=3D max_insns)) { + dc->base.is_jmp =3D DISAS_TOO_MANY; + } + } while (!dc->base.is_jmp); =20 + if (dc->base.is_jmp !=3D DISAS_SKIP) { if (tb->cflags & CF_LAST_IO) { if (dc->condjmp) { /* FIXME: This can theoretically happen with self-modifying @@ -12127,6 +12145,7 @@ void gen_intermediate_code(CPUState *cpu, Translati= onBlock *tb) gen_exception(EXCP_SMC, syn_aa32_smc(), 3); break; case DISAS_NEXT: + case DISAS_TOO_MANY: case DISAS_UPDATE: gen_set_pc_im(dc, dc->pc); /* fall through */ @@ -12145,6 +12164,7 @@ void gen_intermediate_code(CPUState *cpu, Translati= onBlock *tb) */ switch(dc->base.is_jmp) { case DISAS_NEXT: + case DISAS_TOO_MANY: gen_goto_tb(dc, 1, dc->pc); break; case DISAS_UPDATE: @@ -12198,6 +12218,7 @@ void gen_intermediate_code(CPUState *cpu, Translati= onBlock *tb) gen_goto_tb(dc, 1, dc->pc); } } + } =20 done_generating: gen_tb_end(tb, dc->base.num_insns); diff --git a/target/arm/translate.h b/target/arm/translate.h index 6fe40a344a..f830775540 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -9,6 +9,7 @@ typedef struct DisasContext { DisasContextBase base; =20 target_ulong pc; + target_ulong next_page_start; uint32_t insn; /* Nonzero if this instruction has been conditionally skipped. */ int condjmp; @@ -148,6 +149,9 @@ static void disas_set_insn_syndrome(DisasContext *s, ui= nt32_t syn) * as opposed to attempting to use lookup_and_goto_ptr. */ #define DISAS_EXIT DISAS_TARGET_11 +#define DISAS_SS DISAS_TARGET_12 +#define DISAS_PAGE_CROSS DISAS_TARGET_13 +#define DISAS_SKIP DISAS_TARGET_14 =20 #ifdef TARGET_AARCH64 void a64_translate_init(void); From nobody Sat May 4 11:44:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498658090365821.2037150329127; Wed, 28 Jun 2017 06:54:50 -0700 (PDT) Received: from localhost ([::1]:33518 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQDQa-0001en-0K for importer@patchew.org; Wed, 28 Jun 2017 09:54:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36788) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQDPe-0001B5-Tu for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:53:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQDPb-0006qn-OQ for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:53:46 -0400 Received: from roura.ac.upc.es ([147.83.33.10]:33999) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQDPb-0006qV-BR; Wed, 28 Jun 2017 09:53:43 -0400 Received: from correu-2.ac.upc.es (correu-2.ac.upc.es [147.83.30.92]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5SDrcYv028225; Wed, 28 Jun 2017 15:53:38 +0200 Received: from localhost (unknown [132.68.50.243]) by correu-2.ac.upc.es (Postfix) with ESMTPSA id E18761E1; Wed, 28 Jun 2017 15:53:32 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Wed, 28 Jun 2017 16:53:31 +0300 Message-Id: <149865801156.17063.15618379976159104550.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149865219962.17063.10630533069463266646.stgit@frigg.lan> References: <149865219962.17063.10630533069463266646.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5SDrcYv028225 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v11 24/29] target/arm: [tcg, a64] Port to translate_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , "Emilio G. Cota" , "open list:ARM" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova --- target/arm/translate-a64.c | 74 +++++++++++++++++++++++++++-------------= ---- 1 file changed, 46 insertions(+), 28 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9c870f6d07..586a01a2de 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11244,6 +11244,9 @@ static void aarch64_trblock_init_disas_context(Disa= sContextBase *dcbase, dc->is_ldex =3D false; dc->ss_same_el =3D (arm_debug_target_el(env) =3D=3D dc->current_el); =20 + dc->next_page_start =3D + (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; + init_tmp_a64_array(dc); } =20 @@ -11278,12 +11281,45 @@ static BreakpointCheckType aarch64_trblock_breakp= oint_check( } } =20 +static target_ulong aarch64_trblock_translate_insn(DisasContextBase *dcbas= e, + CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + CPUARMState *env =3D cpu->env_ptr; + + + if (dc->ss_active && !dc->pstate_ss) { + /* Singlestep state is Active-pending. + * If we're in this state at the start of a TB then either + * a) we just took an exception to an EL which is being debugged + * and this is the first insn in the exception handler + * b) debug exceptions were masked and we just unmasked them + * without changing EL (eg by clearing PSTATE.D) + * In either case we're going to take a swstep exception in the + * "did not step an insn" case, and so the syndrome ISV and EX + * bits should be zero. + */ + assert(dc->base.num_insns =3D=3D 1); + gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), + default_exception_el(dc)); + dc->base.is_jmp =3D DISAS_EXC; + } else { + disas_a64_insn(env, dc); + } + + if (dc->ss_active) { + dc->base.is_jmp =3D DISAS_SS; + } else if (dc->pc >=3D dc->next_page_start) { + dc->base.is_jmp =3D DISAS_PAGE_CROSS; + } + + return dc->pc; +} + void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, TranslationBlock *tb) { - CPUARMState *env =3D cs->env_ptr; DisasContext *dc =3D container_of(dcbase, DisasContext, base); - target_ulong next_page_start; int max_insns; =20 dc->base.tb =3D tb; @@ -11294,7 +11330,6 @@ void gen_intermediate_code_a64(DisasContextBase *dc= base, CPUState *cs, dc->base.singlestep_enabled =3D cs->singlestep_enabled; aarch64_trblock_init_disas_context(&dc->base, cs); =20 - next_page_start =3D (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PA= GE_SIZE; max_insns =3D dc->base.tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; @@ -11344,42 +11379,24 @@ void gen_intermediate_code_a64(DisasContextBase *= dcbase, CPUState *cs, gen_io_start(); } =20 - if (dc->ss_active && !dc->pstate_ss) { - /* Singlestep state is Active-pending. - * If we're in this state at the start of a TB then either - * a) we just took an exception to an EL which is being debug= ged - * and this is the first insn in the exception handler - * b) debug exceptions were masked and we just unmasked them - * without changing EL (eg by clearing PSTATE.D) - * In either case we're going to take a swstep exception in the - * "did not step an insn" case, and so the syndrome ISV and EX - * bits should be zero. - */ - assert(dc->base.num_insns =3D=3D 1); - gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), - default_exception_el(dc)); - dc->base.is_jmp =3D DISAS_EXC; - break; - } - - disas_a64_insn(env, dc); + dc->base.pc_next =3D aarch64_trblock_translate_insn(&dc->base, cs); =20 if (tcg_check_temp_count()) { fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", dc->pc); } =20 + if (!dc->base.is_jmp && (tcg_op_buf_full() || cs->singlestep_enabl= ed || + singlestep || dc->base.num_insns >=3D max_insn= s)) { + dc->base.is_jmp =3D DISAS_TOO_MANY; + } + /* Translation stops when a conditional branch is encountered. * Otherwise the subsequent code could get translated several time= s. * Also stop translation when a page boundary is reached. This * ensures prefetch aborts occur at the right place. */ - } while (!dc->base.is_jmp && !tcg_op_buf_full() && - !cs->singlestep_enabled && - !singlestep && - !dc->ss_active && - dc->pc < next_page_start && - dc->base.num_insns < max_insns); + } while (!dc->base.is_jmp); =20 if (dc->base.tb->cflags & CF_LAST_IO) { gen_io_end(); @@ -11404,6 +11421,7 @@ void gen_intermediate_code_a64(DisasContextBase *dc= base, CPUState *cs, } else { switch (dc->base.is_jmp) { case DISAS_NEXT: + case DISAS_TOO_MANY: gen_goto_tb(dc, 1, dc->pc); break; default: From nobody Sat May 4 11:44:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498658319557194.22981540647106; Wed, 28 Jun 2017 06:58:39 -0700 (PDT) Received: from localhost ([::1]:33535 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQDUL-0003k8-CX for importer@patchew.org; Wed, 28 Jun 2017 09:58:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38244) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQDTY-0003MI-27 for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:57:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQDTU-0001gu-Ul for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:57:48 -0400 Received: from roura.ac.upc.es ([147.83.33.10]:34005) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQDTU-0001gI-Fh; Wed, 28 Jun 2017 09:57:44 -0400 Received: from correu-1.ac.upc.es (correu-1.ac.upc.es [147.83.30.91]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5SDveuC028318; Wed, 28 Jun 2017 15:57:40 +0200 Received: from localhost (unknown [132.68.50.243]) by correu-1.ac.upc.es (Postfix) with ESMTPSA id E65CA165; Wed, 28 Jun 2017 15:57:34 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Wed, 28 Jun 2017 16:57:33 +0300 Message-Id: <149865825357.17063.13113603039704787150.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149865219962.17063.10630533069463266646.stgit@frigg.lan> References: <149865219962.17063.10630533069463266646.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5SDveuC028318 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v11 25/29] target/arm: [tcg] Port to tb_stop X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , "Emilio G. Cota" , "open list:ARM" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova --- target/arm/translate.c | 195 ++++++++++++++++++++++++++------------------= ---- 1 file changed, 104 insertions(+), 91 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 7ab09a7e5f..ef0b870a2f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -12018,103 +12018,21 @@ static target_ulong arm_trblock_translate_insn(D= isasContextBase *dcbase, return dc->pc; } =20 -/* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) +static void arm_trblock_tb_stop(DisasContextBase *dcbase, CPUState *cpu) { - DisasContext dc1, *dc =3D &dc1; - int max_insns; - - /* generate intermediate code */ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); =20 - /* The A64 decoder has its own top level loop, because it doesn't need - * the A32/T32 complexity to do with conditional execution/IT blocks/e= tc. - */ - if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { - gen_intermediate_code_a64(&dc->base, cpu, tb); + if (dc->base.is_jmp =3D=3D DISAS_SKIP) { return; } =20 - dc->base.tb =3D tb; - dc->base.pc_first =3D dc->base.tb->pc; - dc->base.pc_next =3D dc->base.pc_first; - dc->base.is_jmp =3D DISAS_NEXT; - dc->base.num_insns =3D 0; - dc->base.singlestep_enabled =3D cpu->singlestep_enabled; - arm_trblock_init_disas_context(&dc->base, cpu); - - - arm_trblock_init_globals(&dc->base, cpu); - max_insns =3D tb->cflags & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; + if ((dc->base.tb->cflags & CF_LAST_IO) && dc->condjmp) { + /* FIXME: This can theoretically happen with self-modifying code. = */ + cpu_abort(cpu, "IO on conditional branch instruction"); } - - gen_tb_start(tb); - - tcg_clear_temp_count(); - arm_trblock_tb_start(&dc->base, cpu); - - do { - dc->base.num_insns++; - arm_trblock_insn_start(&dc->base, cpu); - - if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { - if (bp->pc =3D=3D dc->base.pc_next) { - BreakpointCheckType bp_check =3D - arm_trblock_breakpoint_check(&dc->base, cpu, bp); - switch (bp_check) { - case BC_MISS: - /* Target ignored this breakpoint, go to next */ - break; - case BC_HIT_INSN: - /* Hit, keep translating */ - /* - * TODO: if we're never going to have more than one - * BP in a single address, we can simply use= a - * bool here. - */ - goto done_breakpoints; - case BC_HIT_TB: - /* Hit, end TB */ - goto done_generating; - default: - g_assert_not_reached(); - } - } - } - } - done_breakpoints: - - if (dc->base.num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_I= O)) { - gen_io_start(); - } - - dc->base.pc_next =3D arm_trblock_translate_insn(&dc->base, cpu); - - if (tcg_check_temp_count()) { - fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", - dc->pc); - } - - if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep || - dc->base.num_insns >=3D max_insns)) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - } - } while (!dc->base.is_jmp); - - if (dc->base.is_jmp !=3D DISAS_SKIP) { - if (tb->cflags & CF_LAST_IO) { - if (dc->condjmp) { - /* FIXME: This can theoretically happen with self-modifying - code. */ - cpu_abort(cpu, "IO on conditional branch instruction"); - } - gen_io_end(); + if (dc->base.tb->cflags & CF_LAST_IO && dc->condjmp) { + /* FIXME: This can theoretically happen with self-modifying code. = */ + cpu_abort(cpu, "IO on conditional branch instruction"); } =20 /* At this stage dc->condjmp will only be set when the skipped @@ -12218,6 +12136,101 @@ void gen_intermediate_code(CPUState *cpu, Transla= tionBlock *tb) gen_goto_tb(dc, 1, dc->pc); } } +} + +/* generate intermediate code for basic block 'tb'. */ +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) +{ + DisasContext dc1, *dc =3D &dc1; + int max_insns; + + /* generate intermediate code */ + + /* The A64 decoder has its own top level loop, because it doesn't need + * the A32/T32 complexity to do with conditional execution/IT blocks/e= tc. + */ + if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { + gen_intermediate_code_a64(&dc->base, cpu, tb); + return; + } + + dc->base.tb =3D tb; + dc->base.pc_first =3D dc->base.tb->pc; + dc->base.pc_next =3D dc->base.pc_first; + dc->base.is_jmp =3D DISAS_NEXT; + dc->base.num_insns =3D 0; + dc->base.singlestep_enabled =3D cpu->singlestep_enabled; + arm_trblock_init_disas_context(&dc->base, cpu); + + + arm_trblock_init_globals(&dc->base, cpu); + max_insns =3D tb->cflags & CF_COUNT_MASK; + if (max_insns =3D=3D 0) { + max_insns =3D CF_COUNT_MASK; + } + if (max_insns > TCG_MAX_INSNS) { + max_insns =3D TCG_MAX_INSNS; + } + + gen_tb_start(tb); + + tcg_clear_temp_count(); + arm_trblock_tb_start(&dc->base, cpu); + + do { + dc->base.num_insns++; + arm_trblock_insn_start(&dc->base, cpu); + + if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { + CPUBreakpoint *bp; + QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { + if (bp->pc =3D=3D dc->base.pc_next) { + BreakpointCheckType bp_check =3D + arm_trblock_breakpoint_check(&dc->base, cpu, bp); + switch (bp_check) { + case BC_MISS: + /* Target ignored this breakpoint, go to next */ + break; + case BC_HIT_INSN: + /* Hit, keep translating */ + /* + * TODO: if we're never going to have more than one + * BP in a single address, we can simply use= a + * bool here. + */ + goto done_breakpoints; + case BC_HIT_TB: + /* Hit, end TB */ + goto done_generating; + default: + g_assert_not_reached(); + } + } + } + } + done_breakpoints: + + if (dc->base.num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_I= O)) { + gen_io_start(); + } + + dc->base.pc_next =3D arm_trblock_translate_insn(&dc->base, cpu); + + if (tcg_check_temp_count()) { + fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", + dc->pc); + } + + if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep || + dc->base.num_insns >=3D max_insns)) { + dc->base.is_jmp =3D DISAS_TOO_MANY; + } + } while (!dc->base.is_jmp); + + arm_trblock_tb_stop(&dc->base, cpu); + + if (dc->base.tb->cflags & CF_LAST_IO) { + gen_io_end(); } =20 done_generating: From nobody Sat May 4 11:44:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498658599221692.1764983506419; Wed, 28 Jun 2017 07:03:19 -0700 (PDT) Received: from localhost ([::1]:33558 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQDYk-0006G1-OZ for importer@patchew.org; Wed, 28 Jun 2017 10:03:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39147) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQDXW-0005dn-2Z for qemu-devel@nongnu.org; Wed, 28 Jun 2017 10:02:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQDXS-0004UY-Sw for qemu-devel@nongnu.org; Wed, 28 Jun 2017 10:01:54 -0400 Received: from roura.ac.upc.es ([147.83.33.10]:40773) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQDXS-0004UB-C7; Wed, 28 Jun 2017 10:01:50 -0400 Received: from correu-1.ac.upc.es (correu-1.ac.upc.es [147.83.30.91]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5SE1gxu028441; Wed, 28 Jun 2017 16:01:42 +0200 Received: from localhost (unknown [132.68.50.243]) by correu-1.ac.upc.es (Postfix) with ESMTPSA id E0EAE165; Wed, 28 Jun 2017 16:01:36 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Wed, 28 Jun 2017 17:01:35 +0300 Message-Id: <149865849564.17063.5123403029688828196.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149865219962.17063.10630533069463266646.stgit@frigg.lan> References: <149865219962.17063.10630533069463266646.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5SE1gxu028441 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v11 26/29] target/arm: [tcg, a64] Port to tb_stop X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , "Emilio G. Cota" , "open list:ARM" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson --- target/arm/translate-a64.c | 123 +++++++++++++++++++++++-----------------= ---- 1 file changed, 65 insertions(+), 58 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 586a01a2de..c57f475dc0 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11316,6 +11316,69 @@ static target_ulong aarch64_trblock_translate_insn= (DisasContextBase *dcbase, return dc->pc; } =20 +static void aarch64_trblock_tb_stop(DisasContextBase *dcbase, CPUState *cp= u) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + if (unlikely(dc->base.singlestep_enabled || dc->ss_active) + && dc->base.is_jmp !=3D DISAS_EXC) { + /* Note that this means single stepping WFI doesn't halt the CPU. + * For conditional branch insns this is harmless unreachable code = as + * gen_goto_tb() has already handled emitting the debug exception + * (and thus a tb-jump is not possible when singlestepping). + */ + assert(dc->base.is_jmp !=3D DISAS_TB_JUMP); + if (dc->base.is_jmp !=3D DISAS_JUMP) { + gen_a64_set_pc_im(dc->pc); + } + if (dc->base.singlestep_enabled) { + gen_exception_internal(EXCP_DEBUG); + } else { + gen_step_complete_exception(dc); + } + } else { + switch (dc->base.is_jmp) { + case DISAS_NEXT: + case DISAS_TOO_MANY: + gen_goto_tb(dc, 1, dc->pc); + break; + default: + case DISAS_UPDATE: + gen_a64_set_pc_im(dc->pc); + /* fall through */ + case DISAS_JUMP: + tcg_gen_lookup_and_goto_ptr(cpu_pc); + break; + case DISAS_EXIT: + tcg_gen_exit_tb(0); + break; + case DISAS_TB_JUMP: + case DISAS_EXC: + case DISAS_SWI: + break; + case DISAS_WFE: + gen_a64_set_pc_im(dc->pc); + gen_helper_wfe(cpu_env); + break; + case DISAS_YIELD: + gen_a64_set_pc_im(dc->pc); + gen_helper_yield(cpu_env); + break; + case DISAS_WFI: + /* This is a special case because we don't want to just halt t= he CPU + * if trying to debug across a WFI. + */ + gen_a64_set_pc_im(dc->pc); + gen_helper_wfi(cpu_env); + /* The helper doesn't necessarily throw an exception, but we + * must go back to the main loop to check for interrupts anywa= y. + */ + tcg_gen_exit_tb(0); + break; + } + } +} + void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, TranslationBlock *tb) { @@ -11398,68 +11461,12 @@ void gen_intermediate_code_a64(DisasContextBase *= dcbase, CPUState *cs, */ } while (!dc->base.is_jmp); =20 + aarch64_trblock_tb_stop(&dc->base, cs); + if (dc->base.tb->cflags & CF_LAST_IO) { gen_io_end(); } =20 - if (unlikely(cs->singlestep_enabled || dc->ss_active) - && dc->base.is_jmp !=3D DISAS_EXC) { - /* Note that this means single stepping WFI doesn't halt the CPU. - * For conditional branch insns this is harmless unreachable code = as - * gen_goto_tb() has already handled emitting the debug exception - * (and thus a tb-jump is not possible when singlestepping). - */ - assert(dc->base.is_jmp !=3D DISAS_TB_JUMP); - if (dc->base.is_jmp !=3D DISAS_JUMP) { - gen_a64_set_pc_im(dc->pc); - } - if (cs->singlestep_enabled) { - gen_exception_internal(EXCP_DEBUG); - } else { - gen_step_complete_exception(dc); - } - } else { - switch (dc->base.is_jmp) { - case DISAS_NEXT: - case DISAS_TOO_MANY: - gen_goto_tb(dc, 1, dc->pc); - break; - default: - case DISAS_UPDATE: - gen_a64_set_pc_im(dc->pc); - /* fall through */ - case DISAS_JUMP: - tcg_gen_lookup_and_goto_ptr(cpu_pc); - break; - case DISAS_EXIT: - tcg_gen_exit_tb(0); - break; - case DISAS_TB_JUMP: - case DISAS_EXC: - case DISAS_SWI: - break; - case DISAS_WFE: - gen_a64_set_pc_im(dc->pc); - gen_helper_wfe(cpu_env); - break; - case DISAS_YIELD: - gen_a64_set_pc_im(dc->pc); - gen_helper_yield(cpu_env); - break; - case DISAS_WFI: - /* This is a special case because we don't want to just halt t= he CPU - * if trying to debug across a WFI. - */ - gen_a64_set_pc_im(dc->pc); - gen_helper_wfi(cpu_env); - /* The helper doesn't necessarily throw an exception, but we - * must go back to the main loop to check for interrupts anywa= y. - */ - tcg_gen_exit_tb(0); - break; - } - } - done_generating: gen_tb_end(tb, dc->base.num_insns); =20 From nobody Sat May 4 11:44:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 149865881878847.44456989150581; Wed, 28 Jun 2017 07:06:58 -0700 (PDT) Received: from localhost ([::1]:33580 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQDcI-0008Vk-CT for importer@patchew.org; Wed, 28 Jun 2017 10:06:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40134) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQDbS-00083r-E3 for qemu-devel@nongnu.org; Wed, 28 Jun 2017 10:05:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQDbM-0006OX-Nj for qemu-devel@nongnu.org; Wed, 28 Jun 2017 10:05:56 -0400 Received: from roura.ac.upc.es ([147.83.33.10]:35442) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQDbM-0006KK-AN; Wed, 28 Jun 2017 10:05:52 -0400 Received: from correu-1.ac.upc.es (correu-1.ac.upc.es [147.83.30.91]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5SE5iBO028609; Wed, 28 Jun 2017 16:05:44 +0200 Received: from localhost (unknown [132.68.50.243]) by correu-1.ac.upc.es (Postfix) with ESMTPSA id D541C17D; Wed, 28 Jun 2017 16:05:38 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Wed, 28 Jun 2017 17:05:37 +0300 Message-Id: <149865873757.17063.9995919085229011280.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149865219962.17063.10630533069463266646.stgit@frigg.lan> References: <149865219962.17063.10630533069463266646.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5SE5iBO028609 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v11 27/29] target/arm: [tcg] Port to disas_log X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , "Emilio G. Cota" , "open list:ARM" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson --- target/arm/translate.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index ef0b870a2f..30dacee139 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -12138,6 +12138,15 @@ static void arm_trblock_tb_stop(DisasContextBase *= dcbase, CPUState *cpu) } } =20 +static void arm_trblock_disas_log(const DisasContextBase *dcbase, CPUState= *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); + log_target_disas(cpu, dc->base.pc_first, dc->pc - dc->base.pc_first, + dc->thumb | (dc->sctlr_b << 1)); +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { @@ -12241,9 +12250,7 @@ done_generating: qemu_log_in_addr_range(dc->base.pc_first)) { qemu_log_lock(); qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); - log_target_disas(cpu, dc->base.pc_first, dc->pc - dc->base.pc_firs= t, - dc->thumb | (dc->sctlr_b << 1)); + arm_trblock_disas_log(&dc->base, cpu); qemu_log("\n"); qemu_log_unlock(); } From nobody Sat May 4 11:44:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498659111401405.9504418805153; Wed, 28 Jun 2017 07:11:51 -0700 (PDT) Received: from localhost ([::1]:33604 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQDh3-0004Ww-65 for importer@patchew.org; Wed, 28 Jun 2017 10:11:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41191) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQDfI-00036C-Cb for qemu-devel@nongnu.org; Wed, 28 Jun 2017 10:09:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQDfC-0008O0-AN for qemu-devel@nongnu.org; Wed, 28 Jun 2017 10:09:56 -0400 Received: from roura.ac.upc.es ([147.83.33.10]:49969) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQDfB-0008Nk-UG; Wed, 28 Jun 2017 10:09:50 -0400 Received: from correu-1.ac.upc.es (correu-1.ac.upc.es [147.83.30.91]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5SE9k5k028755; Wed, 28 Jun 2017 16:09:46 +0200 Received: from localhost (unknown [132.68.50.243]) by correu-1.ac.upc.es (Postfix) with ESMTPSA id B62CD1C4; Wed, 28 Jun 2017 16:09:40 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Wed, 28 Jun 2017 17:09:39 +0300 Message-Id: <149865897948.17063.7243731047242702451.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149865219962.17063.10630533069463266646.stgit@frigg.lan> References: <149865219962.17063.10630533069463266646.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5SE9k5k028755 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v11 28/29] target/arm: [tcg, a64] Port to disas_log X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , "Emilio G. Cota" , "open list:ARM" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson --- target/arm/translate-a64.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c57f475dc0..cc8bbb2b44 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11379,6 +11379,16 @@ static void aarch64_trblock_tb_stop(DisasContextBa= se *dcbase, CPUState *cpu) } } =20 +static void aarch64_trblock_disas_log(const DisasContextBase *dcbase, + CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); + log_target_disas(cpu, dc->base.pc_first, dc->pc - dc->base.pc_first, + 4 | (bswap_code(dc->sctlr_b) ? 2 : 0)); +} + void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, TranslationBlock *tb) { @@ -11475,9 +11485,7 @@ done_generating: qemu_log_in_addr_range(dc->base.pc_first)) { qemu_log_lock(); qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); - log_target_disas(cs, dc->base.pc_first, dc->pc - dc->base.pc_first, - 4 | (bswap_code(dc->sctlr_b) ? 2 : 0)); + aarch64_trblock_disas_log(&dc->base, cs); qemu_log("\n"); qemu_log_unlock(); } From nobody Sat May 4 11:44:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498659327181942.8326321048386; Wed, 28 Jun 2017 07:15:27 -0700 (PDT) Received: from localhost ([::1]:33626 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQDkU-0003FR-NI for importer@patchew.org; Wed, 28 Jun 2017 10:15:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42494) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQDj9-0001OO-Qo for qemu-devel@nongnu.org; Wed, 28 Jun 2017 10:14:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQDj6-0001uf-Ka for qemu-devel@nongnu.org; Wed, 28 Jun 2017 10:13:55 -0400 Received: from roura.ac.upc.es ([147.83.33.10]:58096) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQDj6-0001uO-4G; Wed, 28 Jun 2017 10:13:52 -0400 Received: from correu-1.ac.upc.es (correu-1.ac.upc.es [147.83.30.91]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5SEDmSA028906; Wed, 28 Jun 2017 16:13:48 +0200 Received: from localhost (unknown [132.68.50.243]) by correu-1.ac.upc.es (Postfix) with ESMTPSA id B792117D; Wed, 28 Jun 2017 16:13:42 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Wed, 28 Jun 2017 17:13:41 +0300 Message-Id: <149865922142.17063.17637554632892697681.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149865219962.17063.10630533069463266646.stgit@frigg.lan> References: <149865219962.17063.10630533069463266646.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5SEDmSA028906 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v11 29/29] target/arm: [tcg] Port to generic translation framework X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , "Emilio G. Cota" , "open list:ARM" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Signed-off-by: Llu=C3=ADs Vilanova --- target/arm/translate-a64.c | 125 +++++++---------------------------------= ---- target/arm/translate.c | 124 +++++++---------------------------------= ---- target/arm/translate.h | 8 --- 3 files changed, 42 insertions(+), 215 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index cc8bbb2b44..84d32ca547 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11250,6 +11250,14 @@ static void aarch64_trblock_init_disas_context(Dis= asContextBase *dcbase, init_tmp_a64_array(dc); } =20 +static void aarch64_trblock_init_globals(DisasContextBase *db, CPUState *c= pu) +{ +} + +static void aarch64_trblock_tb_start(DisasContextBase *db, CPUState *cpu) +{ +} + static void aarch64_trblock_insn_start(DisasContextBase *dcbase, CPUState = *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); @@ -11377,6 +11385,9 @@ static void aarch64_trblock_tb_stop(DisasContextBas= e *dcbase, CPUState *cpu) break; } } + + /* Functions above can change dc->pc, so re-align db->pc_next */ + dc->base.pc_next =3D dc->pc; } =20 static void aarch64_trblock_disas_log(const DisasContextBase *dcbase, @@ -11389,107 +11400,13 @@ static void aarch64_trblock_disas_log(const Disa= sContextBase *dcbase, 4 | (bswap_code(dc->sctlr_b) ? 2 : 0)); } =20 -void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, - TranslationBlock *tb) -{ - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - int max_insns; - - dc->base.tb =3D tb; - dc->base.pc_first =3D dc->base.tb->pc; - dc->base.pc_next =3D dc->base.pc_first; - dc->base.is_jmp =3D DISAS_NEXT; - dc->base.num_insns =3D 0; - dc->base.singlestep_enabled =3D cs->singlestep_enabled; - aarch64_trblock_init_disas_context(&dc->base, cs); - - max_insns =3D dc->base.tb->cflags & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } - - gen_tb_start(tb); - - tcg_clear_temp_count(); - - do { - dc->base.num_insns++; - aarch64_trblock_insn_start(&dc->base, cs); - - if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc =3D=3D dc->base.pc_next) { - BreakpointCheckType bp_check =3D - aarch64_trblock_breakpoint_check(&dc->base, cs, bp= ); - switch (bp_check) { - case BC_MISS: - /* Target ignored this breakpoint, go to next */ - break; - case BC_HIT_INSN: - /* Hit, keep translating */ - /* - * TODO: if we're never going to have more than one - * BP in a single address, we can simply use= a - * bool here. - */ - goto done_breakpoints; - case BC_HIT_TB: - /* Hit, end TB */ - goto done_generating; - default: - g_assert_not_reached(); - } - } - } - } - done_breakpoints: - - if (dc->base.num_insns =3D=3D max_insns && (dc->base.tb->cflags & = CF_LAST_IO)) { - gen_io_start(); - } - - dc->base.pc_next =3D aarch64_trblock_translate_insn(&dc->base, cs); - - if (tcg_check_temp_count()) { - fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", - dc->pc); - } - - if (!dc->base.is_jmp && (tcg_op_buf_full() || cs->singlestep_enabl= ed || - singlestep || dc->base.num_insns >=3D max_insn= s)) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - } - - /* Translation stops when a conditional branch is encountered. - * Otherwise the subsequent code could get translated several time= s. - * Also stop translation when a page boundary is reached. This - * ensures prefetch aborts occur at the right place. - */ - } while (!dc->base.is_jmp); - - aarch64_trblock_tb_stop(&dc->base, cs); - - if (dc->base.tb->cflags & CF_LAST_IO) { - gen_io_end(); - } - -done_generating: - gen_tb_end(tb, dc->base.num_insns); - -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && - qemu_log_in_addr_range(dc->base.pc_first)) { - qemu_log_lock(); - qemu_log("----------------\n"); - aarch64_trblock_disas_log(&dc->base, cs); - qemu_log("\n"); - qemu_log_unlock(); - } -#endif - dc->base.tb->size =3D dc->pc - dc->base.pc_first; - dc->base.tb->icount =3D dc->base.num_insns; -} +const TranslatorOps aarch64_translator_ops =3D { + .init_disas_context =3D aarch64_trblock_init_disas_context, + .init_globals =3D aarch64_trblock_init_globals, + .tb_start =3D aarch64_trblock_tb_start, + .insn_start =3D aarch64_trblock_insn_start, + .breakpoint_check =3D aarch64_trblock_breakpoint_check, + .translate_insn =3D aarch64_trblock_translate_insn, + .tb_stop =3D aarch64_trblock_tb_stop, + .disas_log =3D aarch64_trblock_disas_log, +}; diff --git a/target/arm/translate.c b/target/arm/translate.c index 30dacee139..323cbac672 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -12136,6 +12136,9 @@ static void arm_trblock_tb_stop(DisasContextBase *d= cbase, CPUState *cpu) gen_goto_tb(dc, 1, dc->pc); } } + + /* Functions above can change dc->pc, so re-align db->pc_next */ + dc->base.pc_next =3D dc->pc; } =20 static void arm_trblock_disas_log(const DisasContextBase *dcbase, CPUState= *cpu) @@ -12147,116 +12150,29 @@ static void arm_trblock_disas_log(const DisasCon= textBase *dcbase, CPUState *cpu) dc->thumb | (dc->sctlr_b << 1)); } =20 +static const TranslatorOps arm_translator_ops =3D { + .init_disas_context =3D arm_trblock_init_disas_context, + .init_globals =3D arm_trblock_init_globals, + .tb_start =3D arm_trblock_tb_start, + .insn_start =3D arm_trblock_insn_start, + .breakpoint_check =3D arm_trblock_breakpoint_check, + .translate_insn =3D arm_trblock_translate_insn, + .tb_stop =3D arm_trblock_tb_stop, + .disas_log =3D arm_trblock_disas_log, +}; + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { DisasContext dc1, *dc =3D &dc1; - int max_insns; - - /* generate intermediate code */ - - /* The A64 decoder has its own top level loop, because it doesn't need - * the A32/T32 complexity to do with conditional execution/IT blocks/e= tc. - */ - if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { - gen_intermediate_code_a64(&dc->base, cpu, tb); - return; - } - - dc->base.tb =3D tb; - dc->base.pc_first =3D dc->base.tb->pc; - dc->base.pc_next =3D dc->base.pc_first; - dc->base.is_jmp =3D DISAS_NEXT; - dc->base.num_insns =3D 0; - dc->base.singlestep_enabled =3D cpu->singlestep_enabled; - arm_trblock_init_disas_context(&dc->base, cpu); - =20 - arm_trblock_init_globals(&dc->base, cpu); - max_insns =3D tb->cflags & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } - - gen_tb_start(tb); - - tcg_clear_temp_count(); - arm_trblock_tb_start(&dc->base, cpu); - - do { - dc->base.num_insns++; - arm_trblock_insn_start(&dc->base, cpu); - - if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { - if (bp->pc =3D=3D dc->base.pc_next) { - BreakpointCheckType bp_check =3D - arm_trblock_breakpoint_check(&dc->base, cpu, bp); - switch (bp_check) { - case BC_MISS: - /* Target ignored this breakpoint, go to next */ - break; - case BC_HIT_INSN: - /* Hit, keep translating */ - /* - * TODO: if we're never going to have more than one - * BP in a single address, we can simply use= a - * bool here. - */ - goto done_breakpoints; - case BC_HIT_TB: - /* Hit, end TB */ - goto done_generating; - default: - g_assert_not_reached(); - } - } - } - } - done_breakpoints: - - if (dc->base.num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_I= O)) { - gen_io_start(); - } - - dc->base.pc_next =3D arm_trblock_translate_insn(&dc->base, cpu); - - if (tcg_check_temp_count()) { - fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", - dc->pc); - } - - if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep || - dc->base.num_insns >=3D max_insns)) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - } - } while (!dc->base.is_jmp); - - arm_trblock_tb_stop(&dc->base, cpu); - - if (dc->base.tb->cflags & CF_LAST_IO) { - gen_io_end(); - } - -done_generating: - gen_tb_end(tb, dc->base.num_insns); - -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && - qemu_log_in_addr_range(dc->base.pc_first)) { - qemu_log_lock(); - qemu_log("----------------\n"); - arm_trblock_disas_log(&dc->base, cpu); - qemu_log("\n"); - qemu_log_unlock(); - } + translate_block( +#ifdef TARGET_AARCH64 + ARM_TBFLAG_AARCH64_STATE(tb->flags) ? + &aarch64_translator_ops : #endif - tb->size =3D dc->pc - dc->base.pc_first; - tb->icount =3D dc->base.num_insns; + &arm_translator_ops, + &dc->base, cpu, tb); } =20 static const char *cpu_mode_names[16] =3D { diff --git a/target/arm/translate.h b/target/arm/translate.h index f830775540..f0912ecc96 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -155,21 +155,15 @@ static void disas_set_insn_syndrome(DisasContext *s, = uint32_t syn) =20 #ifdef TARGET_AARCH64 void a64_translate_init(void); -void gen_intermediate_code_a64(DisasContextBase *db, CPUState *cpu, - TranslationBlock *tb); void gen_a64_set_pc_im(uint64_t val); void aarch64_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags); +extern const TranslatorOps aarch64_translator_ops; #else static inline void a64_translate_init(void) { } =20 -static inline void gen_intermediate_code_a64(DisasContextBase *db, CPUStat= e *cpu, - TranslationBlock *tb) -{ -} - static inline void gen_a64_set_pc_im(uint64_t val) { }