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[81.231.233.234]) by smtp.gmail.com with ESMTPSA id r82sm947342lfr.57.2017.06.27.08.37.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 27 Jun 2017 08:37:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=QvXEltXh/ZglI7u5Yo0ZgVnp1pMhE7HR1CxBe8mqsDs=; b=DE2fjHmI7ye/z4lkWf9THi4AcmbLSO5gDzLo0RAGyhzFFsZ9wOJFnSf6kxM4SEfR+L rGt3g3UjEeLXLI5DJOo9QVC7HxeBF50cvo+dUwyMeHGRXq+iiSV5m78dhrtt4V+V/ONY HCbfk+J9fhOepd01Y527zrLgRdkiaURiX1onxRTDtFipCJ4RYXWAWbYXEiNHxWum5zQQ gS1IZaBnKxh/6RQcvulBSuT/xAg4WzrSpLwNVHpYU36JAu3t0rNRhya1mwqCOg82oyue 1wc0P9JTrxiUF4kE5ZyjFjJmb5uq7YWE2KTBgLJCyWTU2C7bdb6TIvWqAMwDhk61PFmD iIMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QvXEltXh/ZglI7u5Yo0ZgVnp1pMhE7HR1CxBe8mqsDs=; b=Fa9lp7q8MR9d//BVrVATKSGSWkEh1YS3Lrb9xvX8fUcexvSE4xdAYpjPYIgIFyIk3x soeDXb1VV+66er1x1SeekZs/GRPthMQir6rKJvdxG2FgKUuVcjQatbKNRm3/Y9d/Vsw2 5DaBtJOtOwClbh8m/hqZyMN9Mco2oGMDENuwVfVumOPxOBkYusnqZ2+Jj5xhfddIcY2C 20BywSHJtchCVxmb006kILAJZvGJXedSVNmhMPXjcipn3um9IEVeUu/48Oboa33KM3Gs wK5ZzB1AffHaBsXhmggL1mPNwi2zYFpxgSrPFPmtxd/7TGp7wsIpD4nf8iwrZaFa/AZv y8iQ== X-Gm-Message-State: AKS2vOzoAVNw4SHIhkPCmOXOP/yBt0RGQE3SDVcpAF+IqDYASYgTeux6 5zNm7p8U5zrYNQya X-Received: by 10.25.19.201 with SMTP id 70mr1864584lft.17.1498577839132; Tue, 27 Jun 2017 08:37:19 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Tue, 27 Jun 2017 17:37:10 +0200 Message-Id: <1498577836-25883-2-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1498577836-25883-1-git-send-email-edgar.iglesias@gmail.com> References: <1498577836-25883-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::244 Subject: [Qemu-devel] [PULL v2 1/7] cputlb: cleanup get_page_addr_code to use VICTIM_TLB_HIT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, pbonzini@redhat.com, frederic.konrad@adacore.com, rth@twiddle.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: KONRAD Frederic This replaces env1 and page_index variables by env and index so we can use VICTIM_TLB_HIT macro later. Reviewed-by: Richard Henderson Reviewed-by: Edgar E. Iglesias Signed-off-by: KONRAD Frederic Signed-off-by: Edgar E. Iglesias --- accel/tcg/cputlb.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 743776a..1cc382d 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -751,21 +751,21 @@ static inline ram_addr_t qemu_ram_addr_from_host_nofa= il(void *ptr) * is actually a ram_addr_t (in system mode; the user mode emulation * version of this function returns a guest virtual address). */ -tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr) +tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr) { - int mmu_idx, page_index, pd; + int mmu_idx, index, pd; void *p; MemoryRegion *mr; - CPUState *cpu =3D ENV_GET_CPU(env1); + CPUState *cpu =3D ENV_GET_CPU(env); CPUIOTLBEntry *iotlbentry; =20 - page_index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - mmu_idx =3D cpu_mmu_index(env1, true); - if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=3D + index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + mmu_idx =3D cpu_mmu_index(env, true); + if (unlikely(env->tlb_table[mmu_idx][index].addr_code !=3D (addr & TARGET_PAGE_MASK))) { - cpu_ldub_code(env1, addr); + cpu_ldub_code(env, addr); } - iotlbentry =3D &env1->iotlb[mmu_idx][page_index]; + iotlbentry =3D &env->iotlb[mmu_idx][index]; pd =3D iotlbentry->addr & ~TARGET_PAGE_MASK; mr =3D iotlb_to_region(cpu, pd, iotlbentry->attrs); if (memory_region_is_unassigned(mr)) { @@ -777,7 +777,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1, t= arget_ulong addr) report_bad_exec(cpu, addr); exit(1); } - p =3D (void *)((uintptr_t)addr + env1->tlb_table[mmu_idx][page_index].= addend); + p =3D (void *)((uintptr_t)addr + env->tlb_table[mmu_idx][index].addend= ); return qemu_ram_addr_from_host_nofail(p); } =20 --=20 2.7.4 From nobody Mon May 6 17:56:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498583682456406.7195798789721; Tue, 27 Jun 2017 10:14:42 -0700 (PDT) Received: from localhost ([::1]:57219 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dPu4U-0001GW-Kc for importer@patchew.org; Tue, 27 Jun 2017 13:14:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52451) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dPtlh-000719-RC for qemu-devel@nongnu.org; Tue, 27 Jun 2017 12:55:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dPsYM-0006DV-CD for qemu-devel@nongnu.org; Tue, 27 Jun 2017 11:37:23 -0400 Received: from mail-lf0-x242.google.com ([2a00:1450:4010:c07::242]:34815) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dPsYM-00068y-4M for qemu-devel@nongnu.org; Tue, 27 Jun 2017 11:37:22 -0400 Received: by mail-lf0-x242.google.com with SMTP id g21so3065759lfk.1 for ; Tue, 27 Jun 2017 08:37:21 -0700 (PDT) Received: from localhost (81-231-233-234-no56.tbcn.telia.com. [81.231.233.234]) by smtp.gmail.com with ESMTPSA id c200sm960502lfe.32.2017.06.27.08.37.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 27 Jun 2017 08:37:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ERkupXM5fT81C1PDUZJodlAGss2LolaZ3fKlJXR8CBk=; b=rBsKUffOkRHFVsFIIIMCZ6W5p5/G40w9pRuP53h90DJPfen/pvCJkkqwvj87MIoKuQ +E0+CvD9+NRUZPnk3Uf5fml93heJht+EPN81t3aj2rHiJbThkGKZutW6gA3SaViYahAc eWEjLItToJpx1lM9TQ3AkNZi+7yEjjBmjJROAUBpdXgVJnZ3Wts1v976QSOokxQgV9Wz 5+FzRXdO7qVRu6tUxxh9tiVEFNuGi3qOgGZd0SNpuSj5imsKGTTjEziSI0zs7EKoE2kN PtgcoD1+feF/lmjR5IBhMfOgtIaEfsXPkk2xbrU8D2FsiczP9p9ei9u0hYwFcB0P6iP8 d4OQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ERkupXM5fT81C1PDUZJodlAGss2LolaZ3fKlJXR8CBk=; b=JA49KJCH2sLRNtNIBTKMHn1Ntr+cuqwvpY9y/ppOX9WhHlLebTcXI4J5Lci1IhdAJX D3mSFCWcQe8p4pynH/gKq3xBVmdjATCf8fGjzwlXZbT54T328Rq070WzTcyRytb/x9/u 0bO3N5/7gHDfaRlFFOTCGON4X4FhOaame7junMcRw7HXG70hCKTFvXXWTSNI1to61cID a+3OEteEX3yXgnveqsnrB50UbcsmqiUKKLZzRz1w9tS9OieFafZuFaWbxtU1yiUcV9md ap/bgjPh2//wFU87jW7Dh+L3/JcgXjnvj9I3R7h3qqSJXSeqi5KzRLqvr7Moeyn3TPw5 Irjg== X-Gm-Message-State: AKS2vOwaCwVM6roncX2XCDulmtdTLgyk3w5iPcd10zjjLaxTzVe9fhwy rVtUZNqXuRatyvGN X-Received: by 10.46.21.84 with SMTP id 20mr331234ljv.121.1498577840515; Tue, 27 Jun 2017 08:37:20 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Tue, 27 Jun 2017 17:37:11 +0200 Message-Id: <1498577836-25883-3-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1498577836-25883-1-git-send-email-edgar.iglesias@gmail.com> References: <1498577836-25883-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::242 Subject: [Qemu-devel] [PULL v2 2/7] cputlb: move get_page_addr_code X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, pbonzini@redhat.com, frederic.konrad@adacore.com, rth@twiddle.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: KONRAD Frederic This just moves the code before VICTIM_TLB_HIT macro definition so we can use it. Reviewed-by: Richard Henderson Reviewed-by: Edgar E. Iglesias Signed-off-by: KONRAD Frederic Signed-off-by: Edgar E. Iglesias --- accel/tcg/cputlb.c | 70 +++++++++++++++++++++++++++-----------------------= ---- 1 file changed, 35 insertions(+), 35 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 1cc382d..5d6c755 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -746,41 +746,6 @@ static inline ram_addr_t qemu_ram_addr_from_host_nofai= l(void *ptr) return ram_addr; } =20 -/* NOTE: this function can trigger an exception */ -/* NOTE2: the returned address is not exactly the physical address: it - * is actually a ram_addr_t (in system mode; the user mode emulation - * version of this function returns a guest virtual address). - */ -tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr) -{ - int mmu_idx, index, pd; - void *p; - MemoryRegion *mr; - CPUState *cpu =3D ENV_GET_CPU(env); - CPUIOTLBEntry *iotlbentry; - - index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - mmu_idx =3D cpu_mmu_index(env, true); - if (unlikely(env->tlb_table[mmu_idx][index].addr_code !=3D - (addr & TARGET_PAGE_MASK))) { - cpu_ldub_code(env, addr); - } - iotlbentry =3D &env->iotlb[mmu_idx][index]; - pd =3D iotlbentry->addr & ~TARGET_PAGE_MASK; - mr =3D iotlb_to_region(cpu, pd, iotlbentry->attrs); - if (memory_region_is_unassigned(mr)) { - cpu_unassigned_access(cpu, addr, false, true, 0, 4); - /* The CPU's unassigned access hook might have longjumped out - * with an exception. If it didn't (or there was no hook) then - * we can't proceed further. - */ - report_bad_exec(cpu, addr); - exit(1); - } - p =3D (void *)((uintptr_t)addr + env->tlb_table[mmu_idx][index].addend= ); - return qemu_ram_addr_from_host_nofail(p); -} - static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, target_ulong addr, uintptr_t retaddr, int size) { @@ -868,6 +833,41 @@ static bool victim_tlb_hit(CPUArchState *env, size_t m= mu_idx, size_t index, victim_tlb_hit(env, mmu_idx, index, offsetof(CPUTLBEntry, TY), \ (ADDR) & TARGET_PAGE_MASK) =20 +/* NOTE: this function can trigger an exception */ +/* NOTE2: the returned address is not exactly the physical address: it + * is actually a ram_addr_t (in system mode; the user mode emulation + * version of this function returns a guest virtual address). + */ +tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr) +{ + int mmu_idx, index, pd; + void *p; + MemoryRegion *mr; + CPUState *cpu =3D ENV_GET_CPU(env); + CPUIOTLBEntry *iotlbentry; + + index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + mmu_idx =3D cpu_mmu_index(env, true); + if (unlikely(env->tlb_table[mmu_idx][index].addr_code !=3D + (addr & TARGET_PAGE_MASK))) { + cpu_ldub_code(env, addr); + } + iotlbentry =3D &env->iotlb[mmu_idx][index]; + pd =3D iotlbentry->addr & ~TARGET_PAGE_MASK; + mr =3D iotlb_to_region(cpu, pd, iotlbentry->attrs); + if (memory_region_is_unassigned(mr)) { + cpu_unassigned_access(cpu, addr, false, true, 0, 4); + /* The CPU's unassigned access hook might have longjumped out + * with an exception. If it didn't (or there was no hook) then + * we can't proceed further. + */ + report_bad_exec(cpu, addr); + exit(1); + } + p =3D (void *)((uintptr_t)addr + env->tlb_table[mmu_idx][index].addend= ); + return qemu_ram_addr_from_host_nofail(p); +} + /* Probe for whether the specified guest write access is permitted. * If it is not permitted then an exception will be taken in the same * way as if this were a real write access (and we will not return). --=20 2.7.4 From nobody Mon May 6 17:56:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498585211355760.9368969212611; Tue, 27 Jun 2017 10:40:11 -0700 (PDT) Received: from localhost ([::1]:57379 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dPuTB-0006uT-Rj for importer@patchew.org; Tue, 27 Jun 2017 13:40:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54476) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dPtlh-0000HQ-Oo for qemu-devel@nongnu.org; Tue, 27 Jun 2017 12:55:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dPsYN-0006HP-AS for qemu-devel@nongnu.org; Tue, 27 Jun 2017 11:37:24 -0400 Received: from mail-lf0-x242.google.com ([2a00:1450:4010:c07::242]:33792) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dPsYN-0006DE-3R for qemu-devel@nongnu.org; Tue, 27 Jun 2017 11:37:23 -0400 Received: by mail-lf0-x242.google.com with SMTP id g21so3065798lfk.1 for ; Tue, 27 Jun 2017 08:37:22 -0700 (PDT) Received: from localhost (81-231-233-234-no56.tbcn.telia.com. [81.231.233.234]) by smtp.gmail.com with ESMTPSA id 88sm744113lja.19.2017.06.27.08.37.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 27 Jun 2017 08:37:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BtkpttOw44uLmPHMoGxaJSvJocKE4rPJ9xX7HFfX4kA=; b=akmOy2+Yn2/nFzyItGpcd4bx6ojE8aHUWWNdeJVY4i8+ikinULJjegzjDFp6ENTqib SLm4cEoiC/wMaX7PX9WKwdoVkUm2MA3jdaPD3GTfDPKI2x0djXpof3Jmn8iSsYN4L+HR 40dSdJtFwmvxED1Bwm1WRPkJ0ScCG1TqLiZXTKivnhdr9dt1RMBrv2InAYRj1gSheSuk n2s/OMf3FNPYulu5xuUVKqF3q2+JmbLAwJ1C7DX7O/Lq08kquHkY5bzF5lAGcm+8i+l1 Lh8wyfBmn8/iLVs5gkELfF+n3y0QbmIM+C39FxnCgRIs2R/gtpcSzzWZq0hMwTdkXqkS n9ZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BtkpttOw44uLmPHMoGxaJSvJocKE4rPJ9xX7HFfX4kA=; b=DCP4iRdcbSn0Xnxoa4RWuB2jxN+7MtVQqYVeBOuNzMtnWKA+k9y/++YJMNR2Woz/oT VhI5xKgPDnAPafRogsQFJyR2bef/G4acJ9NrWrAHIQaeFpXVJp+qDNjgmbJbqBXER43N rluGUy7khFEYQYT8Nr/4mZcbbq0YDilD8Ojqa7Rb9idW1ryD7zfd+DNTkAE9r7yQgqQ4 /gE3KwJCsEkPFCD8mSzEedFkM3GNNSKbjLrwJp8xuzXy4EXWNFJgwIRdjmGX/J8bkJet 4hZOahcugSudpB+OluSTAdotLo6ZjwwtLy151PTcxiYEu8HV2CLySDSF3/DJQwI/UNYU k3Kw== X-Gm-Message-State: AKS2vOwJRQgoVf/NMv8g2Fc3eBq9mxYN7mir2UdkyRbYi8UDMWkHAe6s L+UtBokJti3ptcfQ X-Received: by 10.46.71.129 with SMTP id u123mr1869583lja.115.1498577841710; Tue, 27 Jun 2017 08:37:21 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Tue, 27 Jun 2017 17:37:12 +0200 Message-Id: <1498577836-25883-4-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1498577836-25883-1-git-send-email-edgar.iglesias@gmail.com> References: <1498577836-25883-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::242 Subject: [Qemu-devel] [PULL v2 3/7] cputlb: fix the way get_page_addr_code fills the tlb X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, pbonzini@redhat.com, frederic.konrad@adacore.com, rth@twiddle.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: KONRAD Frederic get_page_addr_code(..) does a cpu_ldub_code to fill the tlb: This can lead to some side effects if a device is mapped at this address. So this patch replaces the cpu_memory_ld by a tlb_fill. Reviewed-by: Richard Henderson Reviewed-by: Edgar E. Iglesias Signed-off-by: KONRAD Frederic Signed-off-by: Edgar E. Iglesias --- accel/tcg/cputlb.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 5d6c755..95265a0 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -849,8 +849,10 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, t= arget_ulong addr) index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); mmu_idx =3D cpu_mmu_index(env, true); if (unlikely(env->tlb_table[mmu_idx][index].addr_code !=3D - (addr & TARGET_PAGE_MASK))) { - cpu_ldub_code(env, addr); + (addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK)))) { + if (!VICTIM_TLB_HIT(addr_read, addr)) { + tlb_fill(ENV_GET_CPU(env), addr, MMU_INST_FETCH, mmu_idx, 0); + } } iotlbentry =3D &env->iotlb[mmu_idx][index]; pd =3D iotlbentry->addr & ~TARGET_PAGE_MASK; --=20 2.7.4 From nobody Mon May 6 17:56:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498583855330263.4147849626597; Tue, 27 Jun 2017 10:17:35 -0700 (PDT) Received: from localhost ([::1]:57233 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dPu7G-0003ro-UB for importer@patchew.org; Tue, 27 Jun 2017 13:17:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54533) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dPtlh-0000JY-Lp for qemu-devel@nongnu.org; Tue, 27 Jun 2017 12:55:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dPsYO-0006Mu-Jt for qemu-devel@nongnu.org; Tue, 27 Jun 2017 11:37:25 -0400 Received: from mail-lf0-x242.google.com ([2a00:1450:4010:c07::242]:33794) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dPsYO-0006Ic-Cf for qemu-devel@nongnu.org; Tue, 27 Jun 2017 11:37:24 -0400 Received: by mail-lf0-x242.google.com with SMTP id g21so3065838lfk.1 for ; Tue, 27 Jun 2017 08:37:24 -0700 (PDT) Received: from localhost (81-231-233-234-no56.tbcn.telia.com. [81.231.233.234]) by smtp.gmail.com with ESMTPSA id x74sm943804lfd.64.2017.06.27.08.37.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 27 Jun 2017 08:37:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ot0MVa1NO+SULyzvcNjSqIEw4W0lP9PdVIe/1/hT3H0=; b=b2OJAJ1wTh37Oec6QMZUYfhZyM8/ZNbR37QoYgyblsPnkW4ukCXZVpahTDKoJcrrVm xJmejG5FYC+7S2ilP0/sakjJgSuXMxl8zZOg8ydk+1y6rOOtrbwtSDILm/lhumJya/XE 6tMRj3p44VbIQbMuTWXBCsOS4ZR48OKuxXHVObWnd2Lt+KzF4asvuRwUuWde2e9suUUm dg9gXi1iGdcMRDc8sA7jcfymZOopdoE5BdRq72UfYhP4n91JwPO6ouYtJWjf8LfQCs7f xj+sRfYbcUaen6WS+MNJktYdzGO45AKSVuykFSInL1gFH3Nfp5gYPytX4bBVCgG34Tic PeIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ot0MVa1NO+SULyzvcNjSqIEw4W0lP9PdVIe/1/hT3H0=; b=GFIgP9XaDm+Pzejq7i92/rALjiOTUNaE5uUd3hjD7BU3YqniwOqAv5FXdXeoUL+Cdy y8O2m+IuYiOHx0rND8xjdU4TvTJo5X/BiyvhUjZi1ZOsRPvAv5U2ARhSr2HKHvI85EY6 V2Qdf94OQvsrWtOyJEx+rz4jr1dJvP1VfWlh0PAE07e8TninHKZ3PUVIltnSrBHnjUFf o/37aQNnSS5WvQnM8syNSzOOwj6RoOR7KOvv66rzuS9VHDujL5/vB72fnKJ+Nj6R3iZs 9d7GiJJXYE2jueiWrCrJ6xLoV7p91f7Q/ywfVANssbLHX+iPwDIUuvAN+wPoNxQBZuHP Ks1A== X-Gm-Message-State: AKS2vOyvG0k8KY+23qu0EYmpDjsH+0JmEbxTe9s2Tbm1kQjSkrpOkMZm DZSWOlkAB4HJk6Mz X-Received: by 10.46.74.25 with SMTP id x25mr1823516lja.127.1498577842925; Tue, 27 Jun 2017 08:37:22 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Tue, 27 Jun 2017 17:37:13 +0200 Message-Id: <1498577836-25883-5-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1498577836-25883-1-git-send-email-edgar.iglesias@gmail.com> References: <1498577836-25883-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::242 Subject: [Qemu-devel] [PULL v2 4/7] qdev: add MemoryRegion property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, pbonzini@redhat.com, frederic.konrad@adacore.com, rth@twiddle.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: KONRAD Frederic We need to pass a pointer to a MemoryRegion for mmio_interface. So this just adds that. Reviewed-by: Edgar E. Iglesias Signed-off-by: KONRAD Frederic Signed-off-by: Edgar E. Iglesias --- include/hw/qdev-properties.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h index 1e5c928..39bf4b2 100644 --- a/include/hw/qdev-properties.h +++ b/include/hw/qdev-properties.h @@ -177,6 +177,8 @@ extern PropertyInfo qdev_prop_arraylen; DEFINE_PROP_UNSIGNED(_n, _s, _f, 0, qdev_prop_blocksize, uint16_t) #define DEFINE_PROP_PCI_HOST_DEVADDR(_n, _s, _f) \ DEFINE_PROP(_n, _s, _f, qdev_prop_pci_host_devaddr, PCIHostDeviceAddre= ss) +#define DEFINE_PROP_MEMORY_REGION(_n, _s, _f) \ + DEFINE_PROP(_n, _s, _f, qdev_prop_ptr, MemoryRegion *) =20 #define DEFINE_PROP_END_OF_LIST() \ {} --=20 2.7.4 From nobody Mon May 6 17:56:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498583730757145.52686453999866; Tue, 27 Jun 2017 10:15:30 -0700 (PDT) Received: from localhost ([::1]:57224 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dPu5J-00020h-8F for importer@patchew.org; Tue, 27 Jun 2017 13:15:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53576) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dPtlh-00084h-Jk for qemu-devel@nongnu.org; Tue, 27 Jun 2017 12:55:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dPsYQ-0006T8-6j for qemu-devel@nongnu.org; Tue, 27 Jun 2017 11:37:27 -0400 Received: from mail-lf0-x232.google.com ([2a00:1450:4010:c07::232]:35548) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dPsYP-0006OM-Qr for qemu-devel@nongnu.org; Tue, 27 Jun 2017 11:37:26 -0400 Received: by mail-lf0-x232.google.com with SMTP id b207so19458468lfg.2 for ; Tue, 27 Jun 2017 08:37:25 -0700 (PDT) Received: from localhost (81-231-233-234-no56.tbcn.telia.com. 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Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Tue, 27 Jun 2017 17:37:14 +0200 Message-Id: <1498577836-25883-6-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1498577836-25883-1-git-send-email-edgar.iglesias@gmail.com> References: <1498577836-25883-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::232 Subject: [Qemu-devel] [PULL v2 5/7] introduce mmio_interface X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, pbonzini@redhat.com, frederic.konrad@adacore.com, rth@twiddle.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: KONRAD Frederic This introduces mmio_interface object which contains a MemoryRegion and can be hotplugged/hotunplugged. Reviewed-by: Edgar E. Iglesias Signed-off-by: KONRAD Frederic Signed-off-by: Edgar E. Iglesias --- hw/misc/Makefile.objs | 1 + hw/misc/mmio_interface.c | 128 +++++++++++++++++++++++++++++++++++= ++++ include/hw/misc/mmio_interface.h | 49 +++++++++++++++ 3 files changed, 178 insertions(+) create mode 100644 hw/misc/mmio_interface.c create mode 100644 include/hw/misc/mmio_interface.h diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index 2019846..08a79c3 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -57,3 +57,4 @@ obj-$(CONFIG_EDU) +=3D edu.o obj-$(CONFIG_HYPERV_TESTDEV) +=3D hyperv_testdev.o obj-$(CONFIG_AUX) +=3D auxbus.o obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_scu.o aspeed_sdmc.o +obj-y +=3D mmio_interface.o diff --git a/hw/misc/mmio_interface.c b/hw/misc/mmio_interface.c new file mode 100644 index 0000000..6f004d2 --- /dev/null +++ b/hw/misc/mmio_interface.c @@ -0,0 +1,128 @@ +/* + * mmio_interface.c + * + * Copyright (C) 2017 : GreenSocs + * http://www.greensocs.com/ , email: info@greensocs.com + * + * Developed by : + * Frederic Konrad + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option)any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + * + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "trace.h" +#include "hw/qdev-properties.h" +#include "hw/misc/mmio_interface.h" +#include "qapi/error.h" + +#ifndef DEBUG_MMIO_INTERFACE +#define DEBUG_MMIO_INTERFACE 0 +#endif + +static uint64_t mmio_interface_counter; + +#define DPRINTF(fmt, ...) do { = \ + if (DEBUG_MMIO_INTERFACE) { = \ + qemu_log("mmio_interface: 0x%" PRIX64 ": " fmt, s->id, ## __VA_ARG= S__);\ + } = \ +} while (0); + +static void mmio_interface_init(Object *obj) +{ + MMIOInterface *s =3D MMIO_INTERFACE(obj); + + if (DEBUG_MMIO_INTERFACE) { + s->id =3D mmio_interface_counter++; + } + + DPRINTF("interface created\n"); + s->host_ptr =3D 0; + s->subregion =3D 0; +} + +static void mmio_interface_realize(DeviceState *dev, Error **errp) +{ + MMIOInterface *s =3D MMIO_INTERFACE(dev); + + DPRINTF("realize from 0x%" PRIX64 " to 0x%" PRIX64 " map host pointer" + " %p\n", s->start, s->end, s->host_ptr); + + if (!s->host_ptr) { + error_setg(errp, "host_ptr property must be set"); + } + + if (!s->subregion) { + error_setg(errp, "subregion property must be set"); + } + + memory_region_init_ram_ptr(&s->ram_mem, OBJECT(s), "ram", + s->end - s->start + 1, s->host_ptr); + memory_region_set_readonly(&s->ram_mem, s->ro); + memory_region_add_subregion(s->subregion, s->start, &s->ram_mem); +} + +static void mmio_interface_unrealize(DeviceState *dev, Error **errp) +{ + MMIOInterface *s =3D MMIO_INTERFACE(dev); + + DPRINTF("unrealize from 0x%" PRIX64 " to 0x%" PRIX64 " map host pointe= r" + " %p\n", s->start, s->end, s->host_ptr); + memory_region_del_subregion(s->subregion, &s->ram_mem); +} + +static void mmio_interface_finalize(Object *obj) +{ + MMIOInterface *s =3D MMIO_INTERFACE(obj); + + DPRINTF("finalize from 0x%" PRIX64 " to 0x%" PRIX64 " map host pointer" + " %p\n", s->start, s->end, s->host_ptr); + object_unparent(OBJECT(&s->ram_mem)); +} + +static Property mmio_interface_properties[] =3D { + DEFINE_PROP_UINT64("start", MMIOInterface, start, 0), + DEFINE_PROP_UINT64("end", MMIOInterface, end, 0), + DEFINE_PROP_PTR("host_ptr", MMIOInterface, host_ptr), + DEFINE_PROP_BOOL("ro", MMIOInterface, ro, false), + DEFINE_PROP_MEMORY_REGION("subregion", MMIOInterface, subregion), + DEFINE_PROP_END_OF_LIST(), +}; + +static void mmio_interface_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D mmio_interface_realize; + dc->unrealize =3D mmio_interface_unrealize; + dc->props =3D mmio_interface_properties; +} + +static const TypeInfo mmio_interface_info =3D { + .name =3D TYPE_MMIO_INTERFACE, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(MMIOInterface), + .instance_init =3D mmio_interface_init, + .instance_finalize =3D mmio_interface_finalize, + .class_init =3D mmio_interface_class_init, +}; + +static void mmio_interface_register_types(void) +{ + type_register_static(&mmio_interface_info); +} + +type_init(mmio_interface_register_types) diff --git a/include/hw/misc/mmio_interface.h b/include/hw/misc/mmio_interf= ace.h new file mode 100644 index 0000000..90d34fb --- /dev/null +++ b/include/hw/misc/mmio_interface.h @@ -0,0 +1,49 @@ +/* + * mmio_interface.h + * + * Copyright (C) 2017 : GreenSocs + * http://www.greensocs.com/ , email: info@greensocs.com + * + * Developed by : + * Frederic Konrad + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option)any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + * + */ + +#ifndef MMIO_INTERFACE_H +#define MMIO_INTERFACE_H + +#include "exec/memory.h" + +#define TYPE_MMIO_INTERFACE "mmio_interface" +#define MMIO_INTERFACE(obj) OBJECT_CHECK(MMIOInterface, (obj), = \ + TYPE_MMIO_INTERFACE) + +typedef struct MMIOInterface { + DeviceState parent_obj; + + MemoryRegion *subregion; + MemoryRegion ram_mem; + uint64_t start; + uint64_t end; + bool ro; + uint64_t id; + void *host_ptr; +} MMIOInterface; + +void mmio_interface_map(MMIOInterface *s); +void mmio_interface_unmap(MMIOInterface *s); + +#endif /* MMIO_INTERFACE_H */ --=20 2.7.4 From nobody Mon May 6 17:56:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498583403118369.49562795096995; Tue, 27 Jun 2017 10:10:03 -0700 (PDT) Received: from localhost ([::1]:57196 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dPtzx-0005wJ-Er for importer@patchew.org; Tue, 27 Jun 2017 13:09:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52896) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dPtlh-0007PJ-Ff for qemu-devel@nongnu.org; Tue, 27 Jun 2017 12:55:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dPsYR-0006Xc-Cb for qemu-devel@nongnu.org; Tue, 27 Jun 2017 11:37:28 -0400 Received: from mail-lf0-x244.google.com ([2a00:1450:4010:c07::244]:35838) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dPsYR-0006TZ-0q for qemu-devel@nongnu.org; Tue, 27 Jun 2017 11:37:27 -0400 Received: by mail-lf0-x244.google.com with SMTP id n136so3050724lfn.2 for ; Tue, 27 Jun 2017 08:37:26 -0700 (PDT) Received: from localhost (81-231-233-234-no56.tbcn.telia.com. [81.231.233.234]) by smtp.gmail.com with ESMTPSA id o142sm933537lff.59.2017.06.27.08.37.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 27 Jun 2017 08:37:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Cs6i/GX278twAioDsI+/JwQf4BcDpVIQfDa7lSmtRZ4=; b=N60K+/5jSoMNB7MMPpnejyrtj7hdnNTuxt7f/IMkIwufQK8HJJ3W4rkoVcceL/t1gW 0k72W5t2uMIUC/Kw+NRJvY9Gl9dEGvgPRNuuR4pg7L9o2r45QN3hYnu7x3Ui8dodPGno LVeYEuzIJhcNNXpBRwkSfmyNCMW11NLwg1BSAJ99wUPUKnb9mq+fXZ03XlcFiubwMS/G YKSe1wdJD7nwSkt9xPnZ9vhaj/eG38wgWOgRbx1JkcVJbeWpZHaDcO7ZGf1xEh885LAs hoBJ4r9RLxLRVYwQOATzMmrDGVB8ebkeOMDi6uEl0+v6Uip1TlDLnGuAc7gbPIvlCLNb aU/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Cs6i/GX278twAioDsI+/JwQf4BcDpVIQfDa7lSmtRZ4=; b=nG3T4xs/c61wvCR76ePlKAx57U9QANC9dwnaoh0sH94ArQzXZfU6SygcZxajt8cLYJ RRqXTIdak0KpBevewBhZr8ppq70icsUHO+9ezryvlgpxgnrozB+QeQcbu/rwJC37XR7i HcQ4RtDeHUfuQB5rED/68HWrAgxG92fq+BFjnDWqYQ0RMLqjK/vxwatfA1rHSHl8zNXG aArXPKVARjaUnAciM/zSfE3F+5XbkOm9aD2XouHmyb8kSA9Qoirzhi+BfaH/iblneS4J 0+IHhSVue3UNDmfEcQ1rQohhqVS09tjUeG3TQLYiYiVstkpsN/KZFfV2LM4nGVupfnvU eoug== X-Gm-Message-State: AKS2vOzekeEw9ZzsGakUXHoXcQ9Aw6vpC9JtYXUBzA5Ej9lxiWqf0fxH NBFd7LCPiC8dyX/V X-Received: by 10.46.0.163 with SMTP id e35mr1745724lji.20.1498577845472; Tue, 27 Jun 2017 08:37:25 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Tue, 27 Jun 2017 17:37:15 +0200 Message-Id: <1498577836-25883-7-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1498577836-25883-1-git-send-email-edgar.iglesias@gmail.com> References: <1498577836-25883-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::244 Subject: [Qemu-devel] [PULL v2 6/7] exec: allow to get a pointer for some mmio memory region X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, pbonzini@redhat.com, frederic.konrad@adacore.com, rth@twiddle.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: KONRAD Frederic This introduces a special callback which allows to run code from some MMIO devices. SysBusDevice with a MemoryRegion which implements the request_ptr callback = will be notified when the guest try to execute code from their offset. Then it w= ill be able to eg: pre-load some code from an SPI device or ask a pointer from = an external simulator, etc.. When the pointer or the data in it are no longer valid the device has to invalidate it. Reviewed-by: Edgar E. Iglesias Signed-off-by: KONRAD Frederic Signed-off-by: Edgar E. Iglesias --- accel/tcg/cputlb.c | 10 +++++ include/exec/memory.h | 35 ++++++++++++++++ memory.c | 111 ++++++++++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 156 insertions(+) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 95265a0..1900936 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -858,6 +858,16 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, t= arget_ulong addr) pd =3D iotlbentry->addr & ~TARGET_PAGE_MASK; mr =3D iotlb_to_region(cpu, pd, iotlbentry->attrs); if (memory_region_is_unassigned(mr)) { + qemu_mutex_lock_iothread(); + if (memory_region_request_mmio_ptr(mr, addr)) { + qemu_mutex_unlock_iothread(); + /* A MemoryRegion is potentially added so re-run the + * get_page_addr_code. + */ + return get_page_addr_code(env, addr); + } + qemu_mutex_unlock_iothread(); + cpu_unassigned_access(cpu, addr, false, true, 0, 4); /* The CPU's unassigned access hook might have longjumped out * with an exception. If it didn't (or there was no hook) then diff --git a/include/exec/memory.h b/include/exec/memory.h index 37f8e78..8503685 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -137,6 +137,15 @@ struct MemoryRegionOps { uint64_t data, unsigned size, MemTxAttrs attrs); + /* Instruction execution pre-callback: + * @addr is the address of the access relative to the @mr. + * @size is the size of the area returned by the callback. + * @offset is the location of the pointer inside @mr. + * + * Returns a pointer to a location which contains guest code. + */ + void *(*request_ptr)(void *opaque, hwaddr addr, unsigned *size, + unsigned *offset); =20 enum device_endian endianness; /* Guest-visible constraints: */ @@ -1363,6 +1372,32 @@ void memory_global_dirty_log_stop(void); void mtree_info(fprintf_function mon_printf, void *f, bool flatview); =20 /** + * memory_region_request_mmio_ptr: request a pointer to an mmio + * MemoryRegion. If it is possible map a RAM MemoryRegion with this pointe= r. + * When the device wants to invalidate the pointer it will call + * memory_region_invalidate_mmio_ptr. + * + * @mr: #MemoryRegion to check + * @addr: address within that region + * + * Returns true on success, false otherwise. + */ +bool memory_region_request_mmio_ptr(MemoryRegion *mr, hwaddr addr); + +/** + * memory_region_invalidate_mmio_ptr: invalidate the pointer to an mmio + * previously requested. + * In the end that means that if something wants to execute from this area= it + * will need to request the pointer again. + * + * @mr: #MemoryRegion associated to the pointer. + * @addr: address within that region + * @size: size of that area. + */ +void memory_region_invalidate_mmio_ptr(MemoryRegion *mr, hwaddr offset, + unsigned size); + +/** * memory_region_dispatch_read: perform a read directly to the specified * MemoryRegion. * diff --git a/memory.c b/memory.c index e08fa0a..1044bba 100644 --- a/memory.c +++ b/memory.c @@ -30,6 +30,8 @@ #include "exec/ram_addr.h" #include "sysemu/kvm.h" #include "sysemu/sysemu.h" +#include "hw/misc/mmio_interface.h" +#include "hw/qdev-properties.h" =20 //#define DEBUG_UNASSIGNED =20 @@ -2430,6 +2432,115 @@ void memory_listener_unregister(MemoryListener *lis= tener) listener->address_space =3D NULL; } =20 +bool memory_region_request_mmio_ptr(MemoryRegion *mr, hwaddr addr) +{ + void *host; + unsigned size =3D 0; + unsigned offset =3D 0; + Object *new_interface; + + if (!mr || !mr->ops->request_ptr) { + return false; + } + + /* + * Avoid an update if the request_ptr call + * memory_region_invalidate_mmio_ptr which seems to be likely when we = use + * a cache. + */ + memory_region_transaction_begin(); + + host =3D mr->ops->request_ptr(mr->opaque, addr - mr->addr, &size, &off= set); + + if (!host || !size) { + memory_region_transaction_commit(); + return false; + } + + new_interface =3D object_new("mmio_interface"); + qdev_prop_set_uint64(DEVICE(new_interface), "start", offset); + qdev_prop_set_uint64(DEVICE(new_interface), "end", offset + size - 1); + qdev_prop_set_bit(DEVICE(new_interface), "ro", true); + qdev_prop_set_ptr(DEVICE(new_interface), "host_ptr", host); + qdev_prop_set_ptr(DEVICE(new_interface), "subregion", mr); + object_property_set_bool(OBJECT(new_interface), true, "realized", NULL= ); + + memory_region_transaction_commit(); + return true; +} + +typedef struct MMIOPtrInvalidate { + MemoryRegion *mr; + hwaddr offset; + unsigned size; + int busy; + int allocated; +} MMIOPtrInvalidate; + +#define MAX_MMIO_INVALIDATE 10 +static MMIOPtrInvalidate mmio_ptr_invalidate_list[MAX_MMIO_INVALIDATE]; + +static void memory_region_do_invalidate_mmio_ptr(CPUState *cpu, + run_on_cpu_data data) +{ + MMIOPtrInvalidate *invalidate_data =3D (MMIOPtrInvalidate *)data.host_= ptr; + MemoryRegion *mr =3D invalidate_data->mr; + hwaddr offset =3D invalidate_data->offset; + unsigned size =3D invalidate_data->size; + MemoryRegionSection section =3D memory_region_find(mr, offset, size); + + qemu_mutex_lock_iothread(); + + /* Reset dirty so this doesn't happen later. */ + cpu_physical_memory_test_and_clear_dirty(offset, size, 1); + + if (section.mr !=3D mr) { + /* memory_region_find add a ref on section.mr */ + memory_region_unref(section.mr); + if (MMIO_INTERFACE(section.mr->owner)) { + /* We found the interface just drop it. */ + object_property_set_bool(section.mr->owner, false, "realized", + NULL); + object_unref(section.mr->owner); + object_unparent(section.mr->owner); + } + } + + qemu_mutex_unlock_iothread(); + + if (invalidate_data->allocated) { + g_free(invalidate_data); + } else { + invalidate_data->busy =3D 0; + } +} + +void memory_region_invalidate_mmio_ptr(MemoryRegion *mr, hwaddr offset, + unsigned size) +{ + size_t i; + MMIOPtrInvalidate *invalidate_data =3D NULL; + + for (i =3D 0; i < MAX_MMIO_INVALIDATE; i++) { + if (atomic_cmpxchg(&(mmio_ptr_invalidate_list[i].busy), 0, 1) =3D= =3D 0) { + invalidate_data =3D &mmio_ptr_invalidate_list[i]; + break; + } + } + + if (!invalidate_data) { + invalidate_data =3D g_malloc0(sizeof(MMIOPtrInvalidate)); + invalidate_data->allocated =3D 1; + } + + invalidate_data->mr =3D mr; + invalidate_data->offset =3D offset; + invalidate_data->size =3D size; + + async_safe_run_on_cpu(first_cpu, memory_region_do_invalidate_mmio_ptr, + RUN_ON_CPU_HOST_PTR(invalidate_data)); +} + void address_space_init(AddressSpace *as, MemoryRegion *root, const char *= name) { memory_region_ref(root); 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Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Tue, 27 Jun 2017 17:37:16 +0200 Message-Id: <1498577836-25883-8-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1498577836-25883-1-git-send-email-edgar.iglesias@gmail.com> References: <1498577836-25883-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::244 Subject: [Qemu-devel] [PULL v2 7/7] xilinx_spips: allow mmio execution X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, pbonzini@redhat.com, frederic.konrad@adacore.com, rth@twiddle.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: KONRAD Frederic This allows to execute from the lqspi area. When the request_ptr is called the device loads 1024bytes from the SPI devi= ce. Then this code can be executed by the guest. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: KONRAD Frederic Signed-off-by: Edgar E. Iglesias --- hw/ssi/xilinx_spips.c | 74 ++++++++++++++++++++++++++++++++++++++---------= ---- 1 file changed, 55 insertions(+), 19 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index da8adfa..e833028 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -496,6 +496,18 @@ static const MemoryRegionOps spips_ops =3D { .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 +static void xilinx_qspips_invalidate_mmio_ptr(XilinxQSPIPS *q) +{ + XilinxSPIPS *s =3D &q->parent_obj; + + if (q->lqspi_cached_addr !=3D ~0ULL) { + /* Invalidate the current mapped mmio */ + memory_region_invalidate_mmio_ptr(&s->mmlqspi, q->lqspi_cached_add= r, + LQSPI_CACHE_SIZE); + q->lqspi_cached_addr =3D ~0ULL; + } +} + static void xilinx_qspips_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { @@ -505,7 +517,7 @@ static void xilinx_qspips_write(void *opaque, hwaddr ad= dr, addr >>=3D 2; =20 if (addr =3D=3D R_LQSPI_CFG) { - q->lqspi_cached_addr =3D ~0ULL; + xilinx_qspips_invalidate_mmio_ptr(q); } } =20 @@ -517,27 +529,20 @@ static const MemoryRegionOps qspips_ops =3D { =20 #define LQSPI_CACHE_SIZE 1024 =20 -static uint64_t -lqspi_read(void *opaque, hwaddr addr, unsigned int size) +static void lqspi_load_cache(void *opaque, hwaddr addr) { - int i; XilinxQSPIPS *q =3D opaque; XilinxSPIPS *s =3D opaque; - uint32_t ret; - - if (addr >=3D q->lqspi_cached_addr && - addr <=3D q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { - uint8_t *retp =3D &q->lqspi_buf[addr - q->lqspi_cached_addr]; - ret =3D cpu_to_le32(*(uint32_t *)retp); - DB_PRINT_L(1, "addr: %08x, data: %08x\n", (unsigned)addr, - (unsigned)ret); - return ret; - } else { - int flash_addr =3D (addr / num_effective_busses(s)); - int slave =3D flash_addr >> LQSPI_ADDRESS_BITS; - int cache_entry =3D 0; - uint32_t u_page_save =3D s->regs[R_LQSPI_STS] & ~LQSPI_CFG_U_PAGE; - + int i; + int flash_addr =3D ((addr & ~(LQSPI_CACHE_SIZE - 1)) + / num_effective_busses(s)); + int slave =3D flash_addr >> LQSPI_ADDRESS_BITS; + int cache_entry =3D 0; + uint32_t u_page_save =3D s->regs[R_LQSPI_STS] & ~LQSPI_CFG_U_PAGE; + + if (addr < q->lqspi_cached_addr || + addr > q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { + xilinx_qspips_invalidate_mmio_ptr(q); s->regs[R_LQSPI_STS] &=3D ~LQSPI_CFG_U_PAGE; s->regs[R_LQSPI_STS] |=3D slave ? LQSPI_CFG_U_PAGE : 0; =20 @@ -589,12 +594,43 @@ lqspi_read(void *opaque, hwaddr addr, unsigned int si= ze) xilinx_spips_update_cs_lines(s); =20 q->lqspi_cached_addr =3D flash_addr * num_effective_busses(s); + } +} + +static void *lqspi_request_mmio_ptr(void *opaque, hwaddr addr, unsigned *s= ize, + unsigned *offset) +{ + XilinxQSPIPS *q =3D opaque; + hwaddr offset_within_the_region =3D addr & ~(LQSPI_CACHE_SIZE - 1); + + lqspi_load_cache(opaque, offset_within_the_region); + *size =3D LQSPI_CACHE_SIZE; + *offset =3D offset_within_the_region; + return q->lqspi_buf; +} + +static uint64_t +lqspi_read(void *opaque, hwaddr addr, unsigned int size) +{ + XilinxQSPIPS *q =3D opaque; + uint32_t ret; + + if (addr >=3D q->lqspi_cached_addr && + addr <=3D q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { + uint8_t *retp =3D &q->lqspi_buf[addr - q->lqspi_cached_addr]; + ret =3D cpu_to_le32(*(uint32_t *)retp); + DB_PRINT_L(1, "addr: %08x, data: %08x\n", (unsigned)addr, + (unsigned)ret); + return ret; + } else { + lqspi_load_cache(opaque, addr); return lqspi_read(opaque, addr, size); } } =20 static const MemoryRegionOps lqspi_ops =3D { .read =3D lqspi_read, + .request_ptr =3D lqspi_request_mmio_ptr, .endianness =3D DEVICE_NATIVE_ENDIAN, .valid =3D { .min_access_size =3D 1, --=20 2.7.4