From nobody Tue Feb 10 02:44:05 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498385620431562.1359800884774; Sun, 25 Jun 2017 03:13:40 -0700 (PDT) Received: from localhost ([::1]:41945 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dP4Xy-0005OQ-H5 for importer@patchew.org; Sun, 25 Jun 2017 06:13:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37462) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dP4X7-0004pp-Kn for qemu-devel@nongnu.org; Sun, 25 Jun 2017 06:12:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dP4X2-0004rM-KJ for qemu-devel@nongnu.org; Sun, 25 Jun 2017 06:12:45 -0400 Received: from roura.ac.upc.edu ([147.83.33.10]:38241 helo=roura.ac.upc.es) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dP4X2-0004rA-3s; Sun, 25 Jun 2017 06:12:40 -0400 Received: from correu-1.ac.upc.es (correu-1.ac.upc.es [147.83.30.91]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5PACcJD020515; Sun, 25 Jun 2017 12:12:38 +0200 Received: from localhost (unknown [132.68.53.125]) by correu-1.ac.upc.es (Postfix) with ESMTPSA id 1F40313BC; Sun, 25 Jun 2017 12:12:33 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Sun, 25 Jun 2017 13:12:32 +0300 Message-Id: <149838555190.6497.14794381660566656791.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149838022308.6497.2104916050645246693.stgit@frigg.lan> References: <149838022308.6497.2104916050645246693.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5PACcJD020515 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v9 22/26] target: [tcg, arm] Port to breakpoint_check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , "open list:ARM" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova --- target/arm/translate-a64.c | 59 ++++++++++++++++++++++++++------------- target/arm/translate.c | 66 +++++++++++++++++++++++++++++-----------= ---- 2 files changed, 82 insertions(+), 43 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index bfc2cdabb5..4321767355 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11267,6 +11267,29 @@ static void aarch64_trblock_insn_start(DisasContex= tBase *db, CPUState *cpu) tcg_gen_insn_start(dc->pc, 0, 0); } =20 +static BreakpointCheckType aarch64_trblock_breakpoint_check( + DisasContextBase *db, CPUState *cpu, const CPUBreakpoint *bp) +{ + DisasContext *dc =3D container_of(db, DisasContext, base); + + if (bp->flags & BP_CPU) { + gen_a64_set_pc_im(dc->pc); + gen_helper_check_breakpoints(cpu_env); + /* End the TB early; it likely won't be executed */ + db->is_jmp =3D DJ_UPDATE; + return BC_HIT_INSN; + } else { + gen_exception_internal_insn(dc, 0, EXCP_DEBUG); + /* The address covered by the breakpoint must be + included in [tb->pc, tb->pc + tb->size) in order + to for it to be properly cleared -- thus we + increment the PC here so that the logic setting + tb->size below does the right thing. */ + dc->pc +=3D 4; + return BC_HIT_TB; + } +} + void gen_intermediate_code_a64(DisasContextBase *db, ARMCPU *cpu, TranslationBlock *tb) { @@ -11275,6 +11298,7 @@ void gen_intermediate_code_a64(DisasContextBase *db= , ARMCPU *cpu, DisasContext *dc =3D container_of(db, DisasContext, base); target_ulong next_page_start; int max_insns; + CPUBreakpoint *bp; =20 db->tb =3D tb; db->pc_first =3D tb->pc; @@ -11301,29 +11325,24 @@ void gen_intermediate_code_a64(DisasContextBase *= db, ARMCPU *cpu, db->num_insns++; aarch64_trblock_insn_start(db, cs); =20 - if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc =3D=3D dc->pc) { - if (bp->flags & BP_CPU) { - gen_a64_set_pc_im(dc->pc); - gen_helper_check_breakpoints(cpu_env); - /* End the TB early; it likely won't be executed */ - db->is_jmp =3D DJ_UPDATE; - } else { - gen_exception_internal_insn(dc, 0, EXCP_DEBUG); - /* The address covered by the breakpoint must be - included in [tb->pc, tb->pc + tb->size) in order - to for it to be properly cleared -- thus we - increment the PC here so that the logic setting - tb->size below does the right thing. */ - dc->pc +=3D 4; - goto done_generating; - } + bp =3D NULL; + do { + bp =3D cpu_breakpoint_get(cs, db->pc_next, bp); + if (unlikely(bp)) { + BreakpointCheckType bp_check =3D + aarch64_trblock_breakpoint_check(db, cs, bp); + if (bp_check =3D=3D BC_HIT_INSN) { + /* Hit, keep translating */ + /* + * TODO: if we're never going to have more than one BP= in a + * single address, we can simply use a bool here. + */ break; + } else { + goto done_generating; } } - } + } while (bp !=3D NULL); =20 if (db->num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(cpu_env); diff --git a/target/arm/translate.c b/target/arm/translate.c index 18b0e8fbb6..a7fcaf2a21 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11954,6 +11954,33 @@ static void arm_trblock_insn_start(DisasContextBas= e *db, CPUState *cpu) #endif } =20 +static BreakpointCheckType arm_trblock_breakpoint_check(DisasContextBase *= db, + CPUState *cpu, + const CPUBreakpoin= t *bp) +{ + DisasContext *dc =3D container_of(db, DisasContext, base); + + if (bp->flags & BP_CPU) { + gen_set_condexec(dc); + gen_set_pc_im(dc, dc->pc); + gen_helper_check_breakpoints(cpu_env); + /* End the TB early; it's likely not going to be executed */ + db->is_jmp =3D DJ_UPDATE; + return BC_HIT_INSN; + } else { + gen_exception_internal_insn(dc, 0, EXCP_DEBUG); + /* The address covered by the breakpoint must be + included in [tb->pc, tb->pc + tb->size) in order + to for it to be properly cleared -- thus we + increment the PC here so that the logic setting + tb->size below does the right thing. */ + /* TODO: Advance PC by correct instruction length to + * avoid disassembler error messages */ + dc->pc +=3D 2; + return BC_HIT_TB; + } +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { @@ -11964,6 +11991,7 @@ void gen_intermediate_code(CPUState *cpu, Translati= onBlock *tb) target_ulong next_page_start; int max_insns; bool end_of_page; + CPUBreakpoint *bp; =20 /* generate intermediate code */ =20 @@ -12003,32 +12031,24 @@ void gen_intermediate_code(CPUState *cpu, Transla= tionBlock *tb) db->num_insns++; arm_trblock_insn_start(db, cpu); =20 - if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { - if (bp->pc =3D=3D dc->pc) { - if (bp->flags & BP_CPU) { - gen_set_condexec(dc); - gen_set_pc_im(dc, dc->pc); - gen_helper_check_breakpoints(cpu_env); - /* End the TB early; it's likely not going to be e= xecuted */ - db->is_jmp =3D DJ_UPDATE; - } else { - gen_exception_internal_insn(dc, 0, EXCP_DEBUG); - /* The address covered by the breakpoint must be - included in [tb->pc, tb->pc + tb->size) in order - to for it to be properly cleared -- thus we - increment the PC here so that the logic setting - tb->size below does the right thing. */ - /* TODO: Advance PC by correct instruction length = to - * avoid disassembler error messages */ - dc->pc +=3D 2; - goto done_generating; - } + bp =3D NULL; + do { + bp =3D cpu_breakpoint_get(cpu, db->pc_next, bp); + if (unlikely(bp)) { + BreakpointCheckType bp_check =3D arm_trblock_breakpoint_ch= eck( + db, cpu, bp); + if (bp_check =3D=3D BC_HIT_INSN) { + /* Hit, keep translating */ + /* + * TODO: if we're never going to have more than one BP= in a + * single address, we can simply use a bool here. + */ break; + } else { + goto done_generating; } } - } + } while (bp !=3D NULL); =20 if (db->num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(cpu_env);