From nobody Mon Feb 9 19:30:09 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 149838538077869.6046951732452; Sun, 25 Jun 2017 03:09:40 -0700 (PDT) Received: from localhost ([::1]:41932 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dP4U7-0003oC-8a for importer@patchew.org; Sun, 25 Jun 2017 06:09:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36856) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dP4TG-0003Ui-EF for qemu-devel@nongnu.org; Sun, 25 Jun 2017 06:08:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dP4TB-0003gB-Dl for qemu-devel@nongnu.org; Sun, 25 Jun 2017 06:08:46 -0400 Received: from roura.ac.upc.edu ([147.83.33.10]:55612 helo=roura.ac.upc.es) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dP4TB-0003g2-1D; Sun, 25 Jun 2017 06:08:41 -0400 Received: from correu-1.ac.upc.es (correu-1.ac.upc.es [147.83.30.91]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5PA8amZ020432; Sun, 25 Jun 2017 12:08:36 +0200 Received: from localhost (unknown [132.68.53.125]) by correu-1.ac.upc.es (Postfix) with ESMTPSA id 445B712B4; Sun, 25 Jun 2017 12:08:31 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Sun, 25 Jun 2017 13:08:30 +0300 Message-Id: <149838531005.6497.12362377034456580175.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149838022308.6497.2104916050645246693.stgit@frigg.lan> References: <149838022308.6497.2104916050645246693.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5PA8amZ020432 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v9 21/26] target: [tcg, arm] Port to insn_start X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , "open list:ARM" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova --- target/arm/translate-a64.c | 11 +++++++++-- target/arm/translate.c | 36 +++++++++++++++++++++--------------- 2 files changed, 30 insertions(+), 17 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 1959f27377..bfc2cdabb5 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11259,6 +11259,14 @@ static void aarch64_trblock_init_disas_context(Dis= asContextBase *db, init_tmp_a64_array(dc); } =20 +static void aarch64_trblock_insn_start(DisasContextBase *db, CPUState *cpu) +{ + DisasContext *dc =3D container_of(db, DisasContext, base); + + dc->insn_start_idx =3D tcg_op_buf_count(); + tcg_gen_insn_start(dc->pc, 0, 0); +} + void gen_intermediate_code_a64(DisasContextBase *db, ARMCPU *cpu, TranslationBlock *tb) { @@ -11291,8 +11299,7 @@ void gen_intermediate_code_a64(DisasContextBase *db= , ARMCPU *cpu, =20 do { db->num_insns++; - dc->insn_start_idx =3D tcg_op_buf_count(); - tcg_gen_insn_start(dc->pc, 0, 0); + aarch64_trblock_insn_start(db, cs); =20 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; diff --git a/target/arm/translate.c b/target/arm/translate.c index ae3f772446..18b0e8fbb6 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11934,6 +11934,26 @@ static void arm_trblock_tb_start(DisasContextBase = *db, CPUState *cpu) } } =20 +static void arm_trblock_insn_start(DisasContextBase *db, CPUState *cpu) +{ + DisasContext *dc =3D container_of(db, DisasContext, base); + + dc->insn_start_idx =3D tcg_op_buf_count(); + tcg_gen_insn_start(dc->pc, + (dc->condexec_cond << 4) | (dc->condexec_mask >> 1), + 0); + +#ifdef CONFIG_USER_ONLY + /* Intercept jump to the magic kernel page. */ + if (dc->pc >=3D 0xffff0000) { + /* We always get here via a jump, so know we are not in a + conditional execution block. */ + gen_exception_internal(EXCP_KERNEL_TRAP); + dc->is_jmp =3D DJ_EXC; + } +#endif +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { @@ -11981,21 +12001,7 @@ void gen_intermediate_code(CPUState *cpu, Translat= ionBlock *tb) =20 do { db->num_insns++; - dc->insn_start_idx =3D tcg_op_buf_count(); - tcg_gen_insn_start(dc->pc, - (dc->condexec_cond << 4) | (dc->condexec_mask >= > 1), - 0); - -#ifdef CONFIG_USER_ONLY - /* Intercept jump to the magic kernel page. */ - if (dc->pc >=3D 0xffff0000) { - /* We always get here via a jump, so know we are not in a - conditional execution block. */ - gen_exception_internal(EXCP_KERNEL_TRAP); - dc->is_jmp =3D DJ_EXC; - break; - } -#endif + arm_trblock_insn_start(db, cpu); =20 if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { CPUBreakpoint *bp;