From nobody Sun Feb 8 18:29:09 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1497628423328926.1729989588723; Fri, 16 Jun 2017 08:53:43 -0700 (PDT) Received: from localhost ([::1]:59518 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dLtZ6-00060A-Rx for importer@patchew.org; Fri, 16 Jun 2017 11:53:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45288) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dLtVW-0002sn-Sa for qemu-devel@nongnu.org; Fri, 16 Jun 2017 11:50:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dLtVV-0002uJ-PN for qemu-devel@nongnu.org; Fri, 16 Jun 2017 11:49:58 -0400 Received: from mx1.redhat.com ([209.132.183.28]:39766) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dLtVV-0002u0-FB for qemu-devel@nongnu.org; Fri, 16 Jun 2017 11:49:57 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 5AA70C04B948; Fri, 16 Jun 2017 15:49:56 +0000 (UTC) Received: from redhat.com (ovpn-123-69.rdu2.redhat.com [10.10.123.69]) by smtp.corp.redhat.com (Postfix) with SMTP id 211ED7D4C9; Fri, 16 Jun 2017 15:49:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 5AA70C04B948 Authentication-Results: ext-mx07.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx07.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=mst@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com 5AA70C04B948 Date: Fri, 16 Jun 2017 18:49:51 +0300 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Message-ID: <1497628168-30489-4-git-send-email-mst@redhat.com> References: <1497628168-30489-1-git-send-email-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1497628168-30489-1-git-send-email-mst@redhat.com> X-Mutt-Fcc: =sent X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.31]); Fri, 16 Jun 2017 15:49:56 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL 3/7] tests/q35-test: add TSEG size checks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Greg Kurz , Gerd Hoffmann , Paolo Bonzini , =?utf-8?Q?Marc-Andr=C3=A9?= Lureau , Laszlo Ersek , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Laszlo Ersek These checks verify that the guest RAM turns from read-write to "blackhole" when crossing the low boundary of the TSEG. Both the standard 1MB/2MB/8MB TSEG sizes and an extended (16MB) TSEG size are tested. Cc: "Michael S. Tsirkin" Cc: Gerd Hoffmann Cc: Paolo Bonzini Suggested-by: Paolo Bonzini Signed-off-by: Laszlo Ersek Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- tests/q35-test.c | 113 +++++++++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 113 insertions(+) diff --git a/tests/q35-test.c b/tests/q35-test.c index 6c21b40..f98bed7 100644 --- a/tests/q35-test.c +++ b/tests/q35-test.c @@ -15,6 +15,48 @@ #include "libqos/pci-pc.h" #include "hw/pci-host/q35.h" =20 +#define TSEG_SIZE_TEST_GUEST_RAM_MBYTES 128 + +/* @esmramc_tseg_sz: ESMRAMC.TSEG_SZ bitmask for selecting the requested T= SEG + * size. Must be a subset of + * MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK. + * + * @extended_tseg_mbytes: Size of the extended TSEG. Only consulted if + * @esmramc_tseg_sz equals + * MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK precisely. + * + * @expected_tseg_mbytes: Expected guest-visible TSEG size in megabytes, + * matching @esmramc_tseg_sz and @extended_tseg_mby= tes + * above. + */ +struct TsegSizeArgs { + uint8_t esmramc_tseg_sz; + uint16_t extended_tseg_mbytes; + uint16_t expected_tseg_mbytes; +}; +typedef struct TsegSizeArgs TsegSizeArgs; + +static const TsegSizeArgs tseg_1mb =3D { + .esmramc_tseg_sz =3D MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB, + .extended_tseg_mbytes =3D 0, + .expected_tseg_mbytes =3D 1, +}; +static const TsegSizeArgs tseg_2mb =3D { + .esmramc_tseg_sz =3D MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB, + .extended_tseg_mbytes =3D 0, + .expected_tseg_mbytes =3D 2, +}; +static const TsegSizeArgs tseg_8mb =3D { + .esmramc_tseg_sz =3D MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB, + .extended_tseg_mbytes =3D 0, + .expected_tseg_mbytes =3D 8, +}; +static const TsegSizeArgs tseg_ext_16mb =3D { + .esmramc_tseg_sz =3D MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK, + .extended_tseg_mbytes =3D 16, + .expected_tseg_mbytes =3D 16, +}; + static void smram_set_bit(QPCIDevice *pcidev, uint8_t mask, bool enabled) { uint8_t smram; @@ -80,11 +122,82 @@ static void test_smram_lock(void) qtest_end(); } =20 +static void test_tseg_size(const void *data) +{ + const TsegSizeArgs *args =3D data; + char *cmdline; + QPCIBus *pcibus; + QPCIDevice *pcidev; + uint8_t smram_val; + uint8_t esmramc_val; + uint32_t ram_offs; + + if (args->esmramc_tseg_sz =3D=3D MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK)= { + cmdline =3D g_strdup_printf("-M q35 -m %uM " + "-global mch.extended-tseg-mbytes=3D%u", + TSEG_SIZE_TEST_GUEST_RAM_MBYTES, + args->extended_tseg_mbytes); + } else { + cmdline =3D g_strdup_printf("-M q35 -m %uM", + TSEG_SIZE_TEST_GUEST_RAM_MBYTES); + } + qtest_start(cmdline); + g_free(cmdline); + + /* locate the DRAM controller */ + pcibus =3D qpci_init_pc(NULL); + g_assert(pcibus !=3D NULL); + pcidev =3D qpci_device_find(pcibus, 0); + g_assert(pcidev !=3D NULL); + + /* Set TSEG size. Restrict TSEG visibility to SMM by setting T_EN. */ + esmramc_val =3D qpci_config_readb(pcidev, MCH_HOST_BRIDGE_ESMRAMC); + esmramc_val &=3D ~MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK; + esmramc_val |=3D args->esmramc_tseg_sz; + esmramc_val |=3D MCH_HOST_BRIDGE_ESMRAMC_T_EN; + qpci_config_writeb(pcidev, MCH_HOST_BRIDGE_ESMRAMC, esmramc_val); + + /* Enable TSEG by setting G_SMRAME. Close TSEG by setting D_CLS. */ + smram_val =3D qpci_config_readb(pcidev, MCH_HOST_BRIDGE_SMRAM); + smram_val &=3D ~(MCH_HOST_BRIDGE_SMRAM_D_OPEN | + MCH_HOST_BRIDGE_SMRAM_D_LCK); + smram_val |=3D (MCH_HOST_BRIDGE_SMRAM_D_CLS | + MCH_HOST_BRIDGE_SMRAM_G_SMRAME); + qpci_config_writeb(pcidev, MCH_HOST_BRIDGE_SMRAM, smram_val); + + /* lock TSEG */ + smram_val |=3D MCH_HOST_BRIDGE_SMRAM_D_LCK; + qpci_config_writeb(pcidev, MCH_HOST_BRIDGE_SMRAM, smram_val); + + /* Now check that the byte right before the TSEG is r/w, and that the = first + * byte in the TSEG always reads as 0xff. + */ + ram_offs =3D (TSEG_SIZE_TEST_GUEST_RAM_MBYTES - args->expected_tseg_mb= ytes) * + 1024 * 1024 - 1; + g_assert_cmpint(readb(ram_offs), =3D=3D, 0); + writeb(ram_offs, 1); + g_assert_cmpint(readb(ram_offs), =3D=3D, 1); + + ram_offs++; + g_assert_cmpint(readb(ram_offs), =3D=3D, 0xff); + writeb(ram_offs, 1); + g_assert_cmpint(readb(ram_offs), =3D=3D, 0xff); + + g_free(pcidev); + qpci_free_pc(pcibus); + qtest_end(); +} + int main(int argc, char **argv) { g_test_init(&argc, &argv, NULL); =20 qtest_add_func("/q35/smram/lock", test_smram_lock); =20 + qtest_add_data_func("/q35/tseg-size/1mb", &tseg_1mb, test_tseg_size); + qtest_add_data_func("/q35/tseg-size/2mb", &tseg_2mb, test_tseg_size); + qtest_add_data_func("/q35/tseg-size/8mb", &tseg_8mb, test_tseg_size); + qtest_add_data_func("/q35/tseg-size/ext/16mb", &tseg_ext_16mb, + test_tseg_size); return g_test_run(); } --=20 MST