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[81.231.233.234]) by smtp.gmail.com with ESMTPSA id x199sm163157lfa.13.2017.06.14.10.45.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 14 Jun 2017 10:45:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FAZ+7i+CSYfy3SduSGxJYt9dyxHO8CZp5FhNiQP6G8Q=; b=jqPNUnHwkQtsPSQziFgErcBktehsSEnTdwCE62PDAY7KZ37Qo5Cq+OW1vqu+lHXSfY VGdtOl8Q5v7Kcv4MoJAOCHQrhoxAektTz26+TRTIpkr7/TlHtA/LqtzadqqxTd6Un/Gn rh6XWpFjNvteZOFZZZNbs8gipOzC7oCrwsKsghkrORMpuKssdOn6098S8WHcoOI4g6Dx Zb5d10Y8sb7GZFXuVjPbEMuid1wbVxprUihcvJmMLHf+kBHgrdAP1kXI+lkTQTvw7sSb t/t6xfxcQvXt7Kl2yuLw/SDQ2S1szdQQvn/Y9tNzk+7RwZG38khDzzr62PEJ7TeYQgwN JM+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FAZ+7i+CSYfy3SduSGxJYt9dyxHO8CZp5FhNiQP6G8Q=; b=IoEcEv9q+HpfF8RHpvYQF9PXzekvCnYBKp5keH609SEHzPeRCwrCeRmDa8PIkzR7oz Fm8UyvF5FctJXfk/cOsPPmeOUBuPbeXHYlRWc4gMY5BSSPLdLyQ6y8sWiQVq7xYalaS4 SWbiGf9zjjQ+BTCJaDOmqFBwT1Tf/n5PucJt5ZEpRGMKAAPoXDX1yuk/RxDGpOezHB77 A9OqvtbY+wi31oNjZ1S1dSBM/amTMxiwvMX4xZZsRWYv7HEhUqxRO3gG3tjN7X2RGHu9 lmiOwqFycy4tMeDlRUTqUoBg37K64G1iWlt6fxHDVCTVBIsrK/DLPE8yKWRIc6jYLFHl kEbQ== X-Gm-Message-State: AKS2vOwA/uhBLBTP/yyCRLSaslHMtRxs3kIUu/J9vUhHb1KTx6Ep+c6i 7XXMOHyTNExe7jUJ X-Received: by 10.25.215.74 with SMTP id o71mr442210lfg.105.1497462356767; Wed, 14 Jun 2017 10:45:56 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Wed, 14 Jun 2017 19:45:47 +0200 Message-Id: <1497462353-3432-2-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497462353-3432-1-git-send-email-edgar.iglesias@gmail.com> References: <1497462353-3432-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::243 Subject: [Qemu-devel] [PULL v1 1/7] cputlb: cleanup get_page_addr_code to use VICTIM_TLB_HIT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, pbonzini@redhat.com, rth@twiddle.net, fred.konrad@greensocs.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: KONRAD Frederic This replaces env1 and page_index variables by env and index so we can use VICTIM_TLB_HIT macro later. Reviewed-by: Richard Henderson Reviewed-by: Edgar E. Iglesias Signed-off-by: KONRAD Frederic --- cputlb.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/cputlb.c b/cputlb.c index 743776a..1cc382d 100644 --- a/cputlb.c +++ b/cputlb.c @@ -751,21 +751,21 @@ static inline ram_addr_t qemu_ram_addr_from_host_nofa= il(void *ptr) * is actually a ram_addr_t (in system mode; the user mode emulation * version of this function returns a guest virtual address). */ -tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr) +tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr) { - int mmu_idx, page_index, pd; + int mmu_idx, index, pd; void *p; MemoryRegion *mr; - CPUState *cpu =3D ENV_GET_CPU(env1); + CPUState *cpu =3D ENV_GET_CPU(env); CPUIOTLBEntry *iotlbentry; =20 - page_index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - mmu_idx =3D cpu_mmu_index(env1, true); - if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=3D + index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + mmu_idx =3D cpu_mmu_index(env, true); + if (unlikely(env->tlb_table[mmu_idx][index].addr_code !=3D (addr & TARGET_PAGE_MASK))) { - cpu_ldub_code(env1, addr); + cpu_ldub_code(env, addr); } - iotlbentry =3D &env1->iotlb[mmu_idx][page_index]; + iotlbentry =3D &env->iotlb[mmu_idx][index]; pd =3D iotlbentry->addr & ~TARGET_PAGE_MASK; mr =3D iotlb_to_region(cpu, pd, iotlbentry->attrs); if (memory_region_is_unassigned(mr)) { @@ -777,7 +777,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1, t= arget_ulong addr) report_bad_exec(cpu, addr); exit(1); } - p =3D (void *)((uintptr_t)addr + env1->tlb_table[mmu_idx][page_index].= addend); + p =3D (void *)((uintptr_t)addr + env->tlb_table[mmu_idx][index].addend= ); return qemu_ram_addr_from_host_nofail(p); } =20 --=20 2.7.4 From nobody Wed Nov 5 13:30:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1497462458067622.9630675834545; Wed, 14 Jun 2017 10:47:38 -0700 (PDT) Received: from localhost ([::1]:50261 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dLCOG-0006gF-5K for importer@patchew.org; Wed, 14 Jun 2017 13:47:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54553) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dLCMl-0005kG-S2 for qemu-devel@nongnu.org; Wed, 14 Jun 2017 13:46:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dLCMh-000130-Rp for qemu-devel@nongnu.org; Wed, 14 Jun 2017 13:46:03 -0400 Received: from mail-lf0-x244.google.com ([2a00:1450:4010:c07::244]:36697) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dLCMh-00012f-Jv for qemu-devel@nongnu.org; Wed, 14 Jun 2017 13:45:59 -0400 Received: by mail-lf0-x244.google.com with SMTP id x81so956182lfb.3 for ; Wed, 14 Jun 2017 10:45:59 -0700 (PDT) Received: from localhost (81-231-233-234-no56.tbcn.telia.com. [81.231.233.234]) by smtp.gmail.com with ESMTPSA id 206sm154070ljj.16.2017.06.14.10.45.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 14 Jun 2017 10:45:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=a3lVWTwEtIZ5NbKDyvpy51eucoIxV8lPzmBabpXoSMw=; b=GcmQngMj2fWlLonz4y/5JguIcvys4/aBJx6VSn1ePSRjLINe0ChGO+zZXDUtvLHTh7 b136TEWD1j/UscvlJkYhRJWy5sNtCeh4sy/+ltwdiICaGPZLjRsA+svWqlF8k4/gwdqL kjLET/WRRNQgGF3sF34Z2Ic/RPo1/p8/ueS5tgvskIwb/Qwbhrt+8tGMSGiNVY5840am SNo8vEzyS5Xpz2NsIOUxvEVgUUEZW7aDoLi5Kl8hWRQDvmBSL2RjreEgn+B3ovVC7uvP 0gzD+aXweCMXIpl2YhG1D4PgoaAp4c5eKwRLXDApBvRRCPYIMTEGdRlMsfiZpsLuYJ/k wPIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=a3lVWTwEtIZ5NbKDyvpy51eucoIxV8lPzmBabpXoSMw=; b=AI5q/tgAmTk80LTxvJpGMw8a4pRwBg5uDx1WZY4OuW8HElz6L+ZLrqb2wufWlD2owC tbcL+SbUfVl6XkDL/jw47Dok+UiEX9ilvbdgwGo1pElMlNndYX8SLD0gHiUb4KcPk95w XyNV71LOUbT440lLDeayXZegR67akWl+/AWD99IMDw6/eIo1/hTNbP83pdyJ4DxYcn8C C1W8wsNgN4mFY3rUevVjLQAL4cTsz1TWlbN6iFspLHRVOcWUm9cWu+zzy85VaqLrUga+ zV7MV9Yf9sl9AIZ7Sezv3qBxqXSREGqZc0LPzUoXhDPbZMLtXtYA+AaIFLLkDasN/+jJ f2oA== X-Gm-Message-State: AKS2vOxXuIFXp3dAEBedof/2aibr7OyFIQ150Nd+2/RZCle+qf3lbfp/ uMcrRcMbM7corUGv X-Received: by 10.46.78.17 with SMTP id c17mr427944ljb.43.1497462358046; Wed, 14 Jun 2017 10:45:58 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Wed, 14 Jun 2017 19:45:48 +0200 Message-Id: <1497462353-3432-3-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497462353-3432-1-git-send-email-edgar.iglesias@gmail.com> References: <1497462353-3432-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::244 Subject: [Qemu-devel] [PULL v1 2/7] cputlb: move get_page_addr_code X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, pbonzini@redhat.com, rth@twiddle.net, fred.konrad@greensocs.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: KONRAD Frederic This just moves the code before VICTIM_TLB_HIT macro definition so we can use it. Reviewed-by: Richard Henderson Reviewed-by: Edgar E. Iglesias Signed-off-by: KONRAD Frederic V2 -> V3: * Rebase against cpu_unaligned access recent change. --- cputlb.c | 70 ++++++++++++++++++++++++++++++++----------------------------= ---- 1 file changed, 35 insertions(+), 35 deletions(-) diff --git a/cputlb.c b/cputlb.c index 1cc382d..5d6c755 100644 --- a/cputlb.c +++ b/cputlb.c @@ -746,41 +746,6 @@ static inline ram_addr_t qemu_ram_addr_from_host_nofai= l(void *ptr) return ram_addr; } =20 -/* NOTE: this function can trigger an exception */ -/* NOTE2: the returned address is not exactly the physical address: it - * is actually a ram_addr_t (in system mode; the user mode emulation - * version of this function returns a guest virtual address). - */ -tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr) -{ - int mmu_idx, index, pd; - void *p; - MemoryRegion *mr; - CPUState *cpu =3D ENV_GET_CPU(env); - CPUIOTLBEntry *iotlbentry; - - index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - mmu_idx =3D cpu_mmu_index(env, true); - if (unlikely(env->tlb_table[mmu_idx][index].addr_code !=3D - (addr & TARGET_PAGE_MASK))) { - cpu_ldub_code(env, addr); - } - iotlbentry =3D &env->iotlb[mmu_idx][index]; - pd =3D iotlbentry->addr & ~TARGET_PAGE_MASK; - mr =3D iotlb_to_region(cpu, pd, iotlbentry->attrs); - if (memory_region_is_unassigned(mr)) { - cpu_unassigned_access(cpu, addr, false, true, 0, 4); - /* The CPU's unassigned access hook might have longjumped out - * with an exception. If it didn't (or there was no hook) then - * we can't proceed further. - */ - report_bad_exec(cpu, addr); - exit(1); - } - p =3D (void *)((uintptr_t)addr + env->tlb_table[mmu_idx][index].addend= ); - return qemu_ram_addr_from_host_nofail(p); -} - static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, target_ulong addr, uintptr_t retaddr, int size) { @@ -868,6 +833,41 @@ static bool victim_tlb_hit(CPUArchState *env, size_t m= mu_idx, size_t index, victim_tlb_hit(env, mmu_idx, index, offsetof(CPUTLBEntry, TY), \ (ADDR) & TARGET_PAGE_MASK) =20 +/* NOTE: this function can trigger an exception */ +/* NOTE2: the returned address is not exactly the physical address: it + * is actually a ram_addr_t (in system mode; the user mode emulation + * version of this function returns a guest virtual address). + */ +tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr) +{ + int mmu_idx, index, pd; + void *p; + MemoryRegion *mr; + CPUState *cpu =3D ENV_GET_CPU(env); + CPUIOTLBEntry *iotlbentry; + + index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + mmu_idx =3D cpu_mmu_index(env, true); + if (unlikely(env->tlb_table[mmu_idx][index].addr_code !=3D + (addr & TARGET_PAGE_MASK))) { + cpu_ldub_code(env, addr); + } + iotlbentry =3D &env->iotlb[mmu_idx][index]; + pd =3D iotlbentry->addr & ~TARGET_PAGE_MASK; + mr =3D iotlb_to_region(cpu, pd, iotlbentry->attrs); + if (memory_region_is_unassigned(mr)) { + cpu_unassigned_access(cpu, addr, false, true, 0, 4); + /* The CPU's unassigned access hook might have longjumped out + * with an exception. If it didn't (or there was no hook) then + * we can't proceed further. + */ + report_bad_exec(cpu, addr); + exit(1); + } + p =3D (void *)((uintptr_t)addr + env->tlb_table[mmu_idx][index].addend= ); + return qemu_ram_addr_from_host_nofail(p); +} + /* Probe for whether the specified guest write access is permitted. * If it is not permitted then an exception will be taken in the same * way as if this were a real write access (and we will not return). --=20 2.7.4 From nobody Wed Nov 5 13:30:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1497462564794634.1232188879377; Wed, 14 Jun 2017 10:49:24 -0700 (PDT) Received: from localhost ([::1]:50270 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dLCPz-0000Df-CP for importer@patchew.org; Wed, 14 Jun 2017 13:49:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54552) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dLCMl-0005kF-S4 for qemu-devel@nongnu.org; Wed, 14 Jun 2017 13:46:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dLCMj-00013U-4Q for qemu-devel@nongnu.org; Wed, 14 Jun 2017 13:46:03 -0400 Received: from mail-lf0-x243.google.com ([2a00:1450:4010:c07::243]:34593) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dLCMi-00013E-Sz for qemu-devel@nongnu.org; Wed, 14 Jun 2017 13:46:01 -0400 Received: by mail-lf0-x243.google.com with SMTP id o28so970535lfk.1 for ; Wed, 14 Jun 2017 10:46:00 -0700 (PDT) Received: from localhost (81-231-233-234-no56.tbcn.telia.com. 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Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Wed, 14 Jun 2017 19:45:49 +0200 Message-Id: <1497462353-3432-4-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497462353-3432-1-git-send-email-edgar.iglesias@gmail.com> References: <1497462353-3432-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::243 Subject: [Qemu-devel] [PULL v1 3/7] cputlb: fix the way get_page_addr_code fills the tlb X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, pbonzini@redhat.com, rth@twiddle.net, fred.konrad@greensocs.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: KONRAD Frederic get_page_addr_code(..) does a cpu_ldub_code to fill the tlb: This can lead to some side effects if a device is mapped at this address. So this patch replaces the cpu_memory_ld by a tlb_fill. Reviewed-by: Richard Henderson Reviewed-by: Edgar E. Iglesias Signed-off-by: KONRAD Frederic --- cputlb.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/cputlb.c b/cputlb.c index 5d6c755..95265a0 100644 --- a/cputlb.c +++ b/cputlb.c @@ -849,8 +849,10 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, t= arget_ulong addr) index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); mmu_idx =3D cpu_mmu_index(env, true); if (unlikely(env->tlb_table[mmu_idx][index].addr_code !=3D - (addr & TARGET_PAGE_MASK))) { - cpu_ldub_code(env, addr); + (addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK)))) { + if (!VICTIM_TLB_HIT(addr_read, addr)) { + tlb_fill(ENV_GET_CPU(env), addr, MMU_INST_FETCH, mmu_idx, 0); + } } iotlbentry =3D &env->iotlb[mmu_idx][index]; pd =3D iotlbentry->addr & ~TARGET_PAGE_MASK; --=20 2.7.4 From nobody Wed Nov 5 13:30:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1497462564429896.0655956175806; Wed, 14 Jun 2017 10:49:24 -0700 (PDT) Received: from localhost ([::1]:50271 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dLCPz-0000Di-70 for importer@patchew.org; Wed, 14 Jun 2017 13:49:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54555) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dLCMl-0005kI-S9 for qemu-devel@nongnu.org; Wed, 14 Jun 2017 13:46:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dLCMk-00013v-Gy for qemu-devel@nongnu.org; Wed, 14 Jun 2017 13:46:03 -0400 Received: from mail-lf0-x243.google.com ([2a00:1450:4010:c07::243]:36699) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dLCMk-00013i-9c for qemu-devel@nongnu.org; Wed, 14 Jun 2017 13:46:02 -0400 Received: by mail-lf0-x243.google.com with SMTP id x81so956324lfb.3 for ; Wed, 14 Jun 2017 10:46:02 -0700 (PDT) Received: from localhost (81-231-233-234-no56.tbcn.telia.com. [81.231.233.234]) by smtp.gmail.com with ESMTPSA id 76sm165594lfq.10.2017.06.14.10.45.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 14 Jun 2017 10:45:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=S/ADx430q+FUb1LRld5B5GFrZWfaGJv58ka/JZuskq8=; b=aKsCINGXMZHdGqOmmhn8ro7881ZOtxVM+mtklktGRfoUuq2JpHZrRJl0IcfWOhpCKo /8c3kVoTzZ7owgYfaiIIhWO/2qPiJm60xoAl1PptdxPowOpMwiDuGYNSAgZ5Ya7svKj2 MfAqnGEkMZiCBGl5GIB3hKISrXo48TNzGgNRurjBG81Hz2XD3u6Rt96hhuoOEfn+eihy 0GQX1B42HuT4lbdBhKNfyJtyZggZAaRebLVpiY9Cu40fUdhWQ0acSZOHQkMZrwEzGz+B PabyaTeu4317qoBG6hAZU98QrqQrv/lsGQ/oxKpZMeFqBSLa9iRc6qV6zvp/ZhGK9jZa cWgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=S/ADx430q+FUb1LRld5B5GFrZWfaGJv58ka/JZuskq8=; b=tUprymVt6RH8b3o6rV8GWA05FCTIMrAsX0dTnt8N4DsFcQT3IizDpEPOivZh+11a26 ir38xLNEWRmmiYdfMq445UO+u+44kLO0hXbMSqExTaoIwO2t+5nr/mC1QhncP5weZY6G CO7bazNO3h56OU1y5HtqEobdMS32lkqs42JHchUxU+SnFM6s/74jZQo+eqzHY3tgJTZf VPoUeGhu9ErplxbuvbcHYa5bEYDGBuaCZsooEUkw1rPqWZS3FY/Ynuwv4+7DrcsrDIYw ApS9ttPlSK+Wzxe1TqDgcPp9vn2aopCVrhKq/tqQ1/U5Uvpbm8Y/s7CrRusjJWS6xKns xUHw== X-Gm-Message-State: AKS2vOxNQmG08QR82HGUqzG1Hz5O2YjMEDBLBQSbMim1n8/xfR/eSbJ8 n4YyjaY2SeekWbWG X-Received: by 10.46.20.9 with SMTP id u9mr452258ljd.54.1497462360843; Wed, 14 Jun 2017 10:46:00 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Wed, 14 Jun 2017 19:45:50 +0200 Message-Id: <1497462353-3432-5-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497462353-3432-1-git-send-email-edgar.iglesias@gmail.com> References: <1497462353-3432-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::243 Subject: [Qemu-devel] [PULL v1 4/7] qdev: add MemoryRegion property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, pbonzini@redhat.com, rth@twiddle.net, fred.konrad@greensocs.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: KONRAD Frederic We need to pass a pointer to a MemoryRegion for mmio_interface. So this just adds that. Reviewed-by: Edgar E. Iglesias Signed-off-by: KONRAD Frederic --- include/hw/qdev-properties.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h index d206fc9..0e9b492 100644 --- a/include/hw/qdev-properties.h +++ b/include/hw/qdev-properties.h @@ -171,6 +171,8 @@ extern PropertyInfo qdev_prop_arraylen; DEFINE_PROP_DEFAULT(_n, _s, _f, 0, qdev_prop_blocksize, uint16_t) #define DEFINE_PROP_PCI_HOST_DEVADDR(_n, _s, _f) \ DEFINE_PROP(_n, _s, _f, qdev_prop_pci_host_devaddr, PCIHostDeviceAddre= ss) +#define DEFINE_PROP_MEMORY_REGION(_n, _s, _f) \ + DEFINE_PROP(_n, _s, _f, qdev_prop_ptr, MemoryRegion *) =20 #define DEFINE_PROP_END_OF_LIST() \ {} --=20 2.7.4 From nobody Wed Nov 5 13:30:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1497462668394464.72775346594574; Wed, 14 Jun 2017 10:51:08 -0700 (PDT) Received: from localhost ([::1]:50281 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dLCRe-0001MP-4p for importer@patchew.org; Wed, 14 Jun 2017 13:51:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54596) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dLCMn-0005kf-NV for qemu-devel@nongnu.org; Wed, 14 Jun 2017 13:46:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dLCMm-00014r-8L for qemu-devel@nongnu.org; Wed, 14 Jun 2017 13:46:05 -0400 Received: from mail-lf0-x22e.google.com ([2a00:1450:4010:c07::22e]:33943) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dLCMl-000149-Tq for qemu-devel@nongnu.org; Wed, 14 Jun 2017 13:46:04 -0400 Received: by mail-lf0-x22e.google.com with SMTP id v20so6460081lfa.1 for ; Wed, 14 Jun 2017 10:46:03 -0700 (PDT) Received: from localhost (81-231-233-234-no56.tbcn.telia.com. [81.231.233.234]) by smtp.gmail.com with ESMTPSA id 63sm155055lja.19.2017.06.14.10.46.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 14 Jun 2017 10:46:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8dmRL0uhLd/5/itUEuuoso7Pi5mOaoLdmiiK17nrkzU=; b=FDmbRQIyDPgJykCEL1yY68NWojl4S6xK25RvlJB9yoT8toesbSXzZ6KjmAZfRim48O s8Q9119PEUGwvMUIz58UoSlxeKd1jFp+1nMgJuFu37EJbIDxzlCAvbJ+XbIt/8FEiZdh /uERH6puMrcGpNAPh2Ay4ClzeDXep0kfgLsbPqscC8v1rKPrCqIVA9zM3YO66d2Jr3+f 6q8RWhWeDQRJ+0KFOsVpPWueHMUlgLRLQ0cX8ZUMbQ1HtOb1kbhhZSL9FU+8Whe7Vb35 UVnWnIkWdE+SJdUVw4VrhZ240hqmi/2Qrh+mvzT0/X2lAixW24ZuP2XAEwjNMgpe34m/ x9DQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8dmRL0uhLd/5/itUEuuoso7Pi5mOaoLdmiiK17nrkzU=; b=WX2bscwCNSme/jHS18AfRGs7gLh70t/pSRyW/rzXovFzC2qs7CujhqlJtzc5dfBSCW olW/iAklCdGaNVS6kQ1bwokQ9HxSh87kpChLL0jXhbxA00xU8bmSwJwe53YhTf211ANY f8OrIiv1ZHa00blNPPlHeEHWmqMWlBru3VFzQArKCkBHqTJVdGG5SXpssKaAUx+inBPN 1mPgE7WzH1P/t7jU42Y9aXMtUrnIM+d4cFc6N7E/O9Z5U4zbdOgIElwKKp75JBJ8DjX2 Iji+wQTLjHxbM3wDQzpTB7isuzFtLwBu+ZuRwK5xdJF1wKhuOGBKi+wdZGWUgoR8hcHu zTcg== X-Gm-Message-State: AKS2vOx9MAg9ucZjkGio3/wGnQxQribRsUrjkRDPLT5sG2BOU93qYkkX Dt1+y8ayhLdiG95c X-Received: by 10.25.206.147 with SMTP id e141mr359567lfg.152.1497462362207; Wed, 14 Jun 2017 10:46:02 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Wed, 14 Jun 2017 19:45:51 +0200 Message-Id: <1497462353-3432-6-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497462353-3432-1-git-send-email-edgar.iglesias@gmail.com> References: <1497462353-3432-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::22e Subject: [Qemu-devel] [PULL v1 5/7] introduce mmio_interface X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, pbonzini@redhat.com, rth@twiddle.net, fred.konrad@greensocs.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: KONRAD Frederic This introduces mmio_interface object which contains a MemoryRegion and can be hotplugged/hotunplugged. Reviewed-by: Edgar E. Iglesias Signed-off-by: KONRAD Frederic V1 -> V2: * Fix the qemu_log format. --- hw/misc/Makefile.objs | 1 + hw/misc/mmio_interface.c | 128 +++++++++++++++++++++++++++++++++++= ++++ include/hw/misc/mmio_interface.h | 49 +++++++++++++++ 3 files changed, 178 insertions(+) create mode 100644 hw/misc/mmio_interface.c create mode 100644 include/hw/misc/mmio_interface.h diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index 2019846..08a79c3 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -57,3 +57,4 @@ obj-$(CONFIG_EDU) +=3D edu.o obj-$(CONFIG_HYPERV_TESTDEV) +=3D hyperv_testdev.o obj-$(CONFIG_AUX) +=3D auxbus.o obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_scu.o aspeed_sdmc.o +obj-y +=3D mmio_interface.o diff --git a/hw/misc/mmio_interface.c b/hw/misc/mmio_interface.c new file mode 100644 index 0000000..6f004d2 --- /dev/null +++ b/hw/misc/mmio_interface.c @@ -0,0 +1,128 @@ +/* + * mmio_interface.c + * + * Copyright (C) 2017 : GreenSocs + * http://www.greensocs.com/ , email: info@greensocs.com + * + * Developed by : + * Frederic Konrad + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option)any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + * + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "trace.h" +#include "hw/qdev-properties.h" +#include "hw/misc/mmio_interface.h" +#include "qapi/error.h" + +#ifndef DEBUG_MMIO_INTERFACE +#define DEBUG_MMIO_INTERFACE 0 +#endif + +static uint64_t mmio_interface_counter; + +#define DPRINTF(fmt, ...) do { = \ + if (DEBUG_MMIO_INTERFACE) { = \ + qemu_log("mmio_interface: 0x%" PRIX64 ": " fmt, s->id, ## __VA_ARG= S__);\ + } = \ +} while (0); + +static void mmio_interface_init(Object *obj) +{ + MMIOInterface *s =3D MMIO_INTERFACE(obj); + + if (DEBUG_MMIO_INTERFACE) { + s->id =3D mmio_interface_counter++; + } + + DPRINTF("interface created\n"); + s->host_ptr =3D 0; + s->subregion =3D 0; +} + +static void mmio_interface_realize(DeviceState *dev, Error **errp) +{ + MMIOInterface *s =3D MMIO_INTERFACE(dev); + + DPRINTF("realize from 0x%" PRIX64 " to 0x%" PRIX64 " map host pointer" + " %p\n", s->start, s->end, s->host_ptr); + + if (!s->host_ptr) { + error_setg(errp, "host_ptr property must be set"); + } + + if (!s->subregion) { + error_setg(errp, "subregion property must be set"); + } + + memory_region_init_ram_ptr(&s->ram_mem, OBJECT(s), "ram", + s->end - s->start + 1, s->host_ptr); + memory_region_set_readonly(&s->ram_mem, s->ro); + memory_region_add_subregion(s->subregion, s->start, &s->ram_mem); +} + +static void mmio_interface_unrealize(DeviceState *dev, Error **errp) +{ + MMIOInterface *s =3D MMIO_INTERFACE(dev); + + DPRINTF("unrealize from 0x%" PRIX64 " to 0x%" PRIX64 " map host pointe= r" + " %p\n", s->start, s->end, s->host_ptr); + memory_region_del_subregion(s->subregion, &s->ram_mem); +} + +static void mmio_interface_finalize(Object *obj) +{ + MMIOInterface *s =3D MMIO_INTERFACE(obj); + + DPRINTF("finalize from 0x%" PRIX64 " to 0x%" PRIX64 " map host pointer" + " %p\n", s->start, s->end, s->host_ptr); + object_unparent(OBJECT(&s->ram_mem)); +} + +static Property mmio_interface_properties[] =3D { + DEFINE_PROP_UINT64("start", MMIOInterface, start, 0), + DEFINE_PROP_UINT64("end", MMIOInterface, end, 0), + DEFINE_PROP_PTR("host_ptr", MMIOInterface, host_ptr), + DEFINE_PROP_BOOL("ro", MMIOInterface, ro, false), + DEFINE_PROP_MEMORY_REGION("subregion", MMIOInterface, subregion), + DEFINE_PROP_END_OF_LIST(), +}; + +static void mmio_interface_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D mmio_interface_realize; + dc->unrealize =3D mmio_interface_unrealize; + dc->props =3D mmio_interface_properties; +} + +static const TypeInfo mmio_interface_info =3D { + .name =3D TYPE_MMIO_INTERFACE, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(MMIOInterface), + .instance_init =3D mmio_interface_init, + .instance_finalize =3D mmio_interface_finalize, + .class_init =3D mmio_interface_class_init, +}; + +static void mmio_interface_register_types(void) +{ + type_register_static(&mmio_interface_info); +} + +type_init(mmio_interface_register_types) diff --git a/include/hw/misc/mmio_interface.h b/include/hw/misc/mmio_interf= ace.h new file mode 100644 index 0000000..90d34fb --- /dev/null +++ b/include/hw/misc/mmio_interface.h @@ -0,0 +1,49 @@ +/* + * mmio_interface.h + * + * Copyright (C) 2017 : GreenSocs + * http://www.greensocs.com/ , email: info@greensocs.com + * + * Developed by : + * Frederic Konrad + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option)any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + * + */ + +#ifndef MMIO_INTERFACE_H +#define MMIO_INTERFACE_H + +#include "exec/memory.h" + +#define TYPE_MMIO_INTERFACE "mmio_interface" +#define MMIO_INTERFACE(obj) OBJECT_CHECK(MMIOInterface, (obj), = \ + TYPE_MMIO_INTERFACE) + +typedef struct MMIOInterface { + DeviceState parent_obj; + + MemoryRegion *subregion; + MemoryRegion ram_mem; + uint64_t start; + uint64_t end; + bool ro; + uint64_t id; + void *host_ptr; +} MMIOInterface; + +void mmio_interface_map(MMIOInterface *s); +void mmio_interface_unmap(MMIOInterface *s); + +#endif /* MMIO_INTERFACE_H */ --=20 2.7.4 From nobody Wed Nov 5 13:30:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1497462765988205.30561148069057; Wed, 14 Jun 2017 10:52:45 -0700 (PDT) Received: from localhost ([::1]:50286 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dLCTE-000385-B6 for importer@patchew.org; Wed, 14 Jun 2017 13:52:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54614) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dLCMo-0005l5-US for qemu-devel@nongnu.org; Wed, 14 Jun 2017 13:46:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dLCMn-00015G-Ji for qemu-devel@nongnu.org; Wed, 14 Jun 2017 13:46:07 -0400 Received: from mail-lf0-x22b.google.com ([2a00:1450:4010:c07::22b]:32874) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dLCMn-00014w-8d for qemu-devel@nongnu.org; Wed, 14 Jun 2017 13:46:05 -0400 Received: by mail-lf0-x22b.google.com with SMTP id m77so6470025lfe.0 for ; Wed, 14 Jun 2017 10:46:05 -0700 (PDT) Received: from localhost (81-231-233-234-no56.tbcn.telia.com. [81.231.233.234]) by smtp.gmail.com with ESMTPSA id c88sm156294lfh.56.2017.06.14.10.46.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 14 Jun 2017 10:46:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tUkWpR5RVT2CL/YJWPsEqUW0ea5IFmPLyN55fL9XhNk=; b=PsoZptR6P/+tH2ujGN+BuBjsyidQogdpeGPl2KFIL/ZlhjAv27VuxJqZdnZGecxM93 jK0v8q7vH18R8tWL4grHmfZ0HqlaB99OsQR3ADdxNd5a+sfiafsP7kfX6YHJuHvmEaAi orBlR6JpzLZ2sTu4dGhIApbva8yrV07fb0cqtaW8W1Vmil4ajFlrUqQR3xXpvmwHeWCz a4jdqACuvXSarwnJ1NZLMN25Jaec/FNRarv7olmPzncZzakCdJvuPjrh3j+ICOeG6Edh WFwdofak9Nw0GMAO1pqWg5ijtkFEVhEtaSaw/RZewxDSPtaGL71Mi3mDwpaYRJKuWzi/ jPHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tUkWpR5RVT2CL/YJWPsEqUW0ea5IFmPLyN55fL9XhNk=; b=RaezIYunPJgQGMpX1WKLJHRSaPe9O8fX/MEVoV6ms28XaRciqmif+rFpQRtjJbUxkP dqNFCc1nOBKwT01bxBz5OxAw9PLl7ORuZjEmk2UE3lYRpdDNqkrRvUAEgsawlAiGpWfB 9V0Tyix3/PG77X0yhKF2vCr3ytgrXpAylnDd4jvNwFZfzpF5R9j5CnZTqj27pDVxdxOk SSkWFuuOWF+VUcUZwlhAdmweXERyfgoyNv/7hDOZ1GakYIeY+zSGmbRaqTwy3lfJ0PtS noH2DtUxeKO1Rp7ms/qriWsAlcYgw+TN3YPFlIwD78xVSXuS4+DA8Q5fOFYKsdZrKURU 2emg== X-Gm-Message-State: AKS2vOx0BBQXCBryvfnEcykr8LOkekJFgt5bQRGCeHSyQmV2BQny/Dqo YAULB+Qw056w9THm X-Received: by 10.25.166.15 with SMTP id p15mr358540lfe.43.1497462363646; Wed, 14 Jun 2017 10:46:03 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Wed, 14 Jun 2017 19:45:52 +0200 Message-Id: <1497462353-3432-7-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497462353-3432-1-git-send-email-edgar.iglesias@gmail.com> References: <1497462353-3432-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::22b Subject: [Qemu-devel] [PULL v1 6/7] exec: allow to get a pointer for some mmio memory region X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, pbonzini@redhat.com, rth@twiddle.net, fred.konrad@greensocs.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: KONRAD Frederic This introduces a special callback which allows to run code from some MMIO devices. SysBusDevice with a MemoryRegion which implements the request_ptr callback = will be notified when the guest try to execute code from their offset. Then it w= ill be able to eg: pre-load some code from an SPI device or ask a pointer from = an external simulator, etc.. When the pointer or the data in it are no longer valid the device has to invalidate it. Signed-off-by: KONRAD Frederic V2 -> V3: * Put the invalidate in an async work. * Clear the dirty flag before dropping the mmio interface. * Rebase against recent cpu_handle_unaligned changes. RFC -> V1: * Use mmio-interface instead of directly creating the subregion. --- cputlb.c | 10 +++++ include/exec/memory.h | 35 ++++++++++++++++ memory.c | 111 ++++++++++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 156 insertions(+) diff --git a/cputlb.c b/cputlb.c index 95265a0..1900936 100644 --- a/cputlb.c +++ b/cputlb.c @@ -858,6 +858,16 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, t= arget_ulong addr) pd =3D iotlbentry->addr & ~TARGET_PAGE_MASK; mr =3D iotlb_to_region(cpu, pd, iotlbentry->attrs); if (memory_region_is_unassigned(mr)) { + qemu_mutex_lock_iothread(); + if (memory_region_request_mmio_ptr(mr, addr)) { + qemu_mutex_unlock_iothread(); + /* A MemoryRegion is potentially added so re-run the + * get_page_addr_code. + */ + return get_page_addr_code(env, addr); + } + qemu_mutex_unlock_iothread(); + cpu_unassigned_access(cpu, addr, false, true, 0, 4); /* The CPU's unassigned access hook might have longjumped out * with an exception. If it didn't (or there was no hook) then diff --git a/include/exec/memory.h b/include/exec/memory.h index 80e605a..137339a 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -137,6 +137,15 @@ struct MemoryRegionOps { uint64_t data, unsigned size, MemTxAttrs attrs); + /* Instruction execution pre-callback: + * @addr is the address of the access relative to the @mr. + * @size is the size of the area returned by the callback. + * @offset is the location of the pointer inside @mr. + * + * Returns a pointer to a location which contains guest code. + */ + void *(*request_ptr)(void *opaque, hwaddr addr, unsigned *size, + unsigned *offset); =20 enum device_endian endianness; /* Guest-visible constraints: */ @@ -1354,6 +1363,32 @@ void memory_global_dirty_log_stop(void); void mtree_info(fprintf_function mon_printf, void *f, bool flatview); =20 /** + * memory_region_request_mmio_ptr: request a pointer to an mmio + * MemoryRegion. If it is possible map a RAM MemoryRegion with this pointe= r. + * When the device wants to invalidate the pointer it will call + * memory_region_invalidate_mmio_ptr. + * + * @mr: #MemoryRegion to check + * @addr: address within that region + * + * Returns true on success, false otherwise. + */ +bool memory_region_request_mmio_ptr(MemoryRegion *mr, hwaddr addr); + +/** + * memory_region_invalidate_mmio_ptr: invalidate the pointer to an mmio + * previously requested. + * In the end that means that if something wants to execute from this area= it + * will need to request the pointer again. + * + * @mr: #MemoryRegion associated to the pointer. + * @addr: address within that region + * @size: size of that area. + */ +void memory_region_invalidate_mmio_ptr(MemoryRegion *mr, hwaddr offset, + unsigned size); + +/** * memory_region_dispatch_read: perform a read directly to the specified * MemoryRegion. * diff --git a/memory.c b/memory.c index 0ddc4cc..9c89dd4 100644 --- a/memory.c +++ b/memory.c @@ -30,6 +30,8 @@ #include "exec/ram_addr.h" #include "sysemu/kvm.h" #include "sysemu/sysemu.h" +#include "hw/misc/mmio_interface.h" +#include "hw/qdev-properties.h" =20 //#define DEBUG_UNASSIGNED =20 @@ -2424,6 +2426,115 @@ void memory_listener_unregister(MemoryListener *lis= tener) listener->address_space =3D NULL; } =20 +bool memory_region_request_mmio_ptr(MemoryRegion *mr, hwaddr addr) +{ + void *host; + unsigned size =3D 0; + unsigned offset =3D 0; + Object *new_interface; + + if (!mr || !mr->ops->request_ptr) { + return false; + } + + /* + * Avoid an update if the request_ptr call + * memory_region_invalidate_mmio_ptr which seems to be likely when we = use + * a cache. + */ + memory_region_transaction_begin(); + + host =3D mr->ops->request_ptr(mr->opaque, addr - mr->addr, &size, &off= set); + + if (!host || !size) { + memory_region_transaction_commit(); + return false; + } + + new_interface =3D object_new("mmio_interface"); + qdev_prop_set_uint64(DEVICE(new_interface), "start", offset); + qdev_prop_set_uint64(DEVICE(new_interface), "end", offset + size - 1); + qdev_prop_set_bit(DEVICE(new_interface), "ro", true); + qdev_prop_set_ptr(DEVICE(new_interface), "host_ptr", host); + qdev_prop_set_ptr(DEVICE(new_interface), "subregion", mr); + object_property_set_bool(OBJECT(new_interface), true, "realized", NULL= ); + + memory_region_transaction_commit(); + return true; +} + +typedef struct MMIOPtrInvalidate { + MemoryRegion *mr; + hwaddr offset; + unsigned size; + int busy; + int allocated; +} MMIOPtrInvalidate; + +#define MAX_MMIO_INVALIDATE 10 +static MMIOPtrInvalidate mmio_ptr_invalidate_list[MAX_MMIO_INVALIDATE]; + +static void memory_region_do_invalidate_mmio_ptr(CPUState *cpu, + run_on_cpu_data data) +{ + MMIOPtrInvalidate *invalidate_data =3D (MMIOPtrInvalidate *)data.host_= ptr; + MemoryRegion *mr =3D invalidate_data->mr; + hwaddr offset =3D invalidate_data->offset; + unsigned size =3D invalidate_data->size; + MemoryRegionSection section =3D memory_region_find(mr, offset, size); + + qemu_mutex_lock_iothread(); + + /* Reset dirty so this doesn't happen later. */ + cpu_physical_memory_test_and_clear_dirty(offset, size, 1); + + if (section.mr !=3D mr) { + /* memory_region_find add a ref on section.mr */ + memory_region_unref(section.mr); + if (MMIO_INTERFACE(section.mr->owner)) { + /* We found the interface just drop it. */ + object_property_set_bool(section.mr->owner, false, "realized", + NULL); + object_unref(section.mr->owner); + object_unparent(section.mr->owner); + } + } + + qemu_mutex_unlock_iothread(); + + if (invalidate_data->allocated) { + g_free(invalidate_data); + } else { + invalidate_data->busy =3D 0; + } +} + +void memory_region_invalidate_mmio_ptr(MemoryRegion *mr, hwaddr offset, + unsigned size) +{ + size_t i; + MMIOPtrInvalidate *invalidate_data =3D NULL; + + for (i =3D 0; i < MAX_MMIO_INVALIDATE; i++) { + if (atomic_cmpxchg(&(mmio_ptr_invalidate_list[i].busy), 0, 1) =3D= =3D 0) { + invalidate_data =3D &mmio_ptr_invalidate_list[i]; + break; + } + } + + if (!invalidate_data) { + invalidate_data =3D g_malloc0(sizeof(MMIOPtrInvalidate)); + invalidate_data->allocated =3D 1; + } + + invalidate_data->mr =3D mr; + invalidate_data->offset =3D offset; + invalidate_data->size =3D size; + + async_safe_run_on_cpu(first_cpu, memory_region_do_invalidate_mmio_ptr, + RUN_ON_CPU_HOST_PTR(invalidate_data)); +} + void address_space_init(AddressSpace *as, MemoryRegion *root, const char *= name) { memory_region_ref(root); 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Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Wed, 14 Jun 2017 19:45:53 +0200 Message-Id: <1497462353-3432-8-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497462353-3432-1-git-send-email-edgar.iglesias@gmail.com> References: <1497462353-3432-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::243 Subject: [Qemu-devel] [PULL v1 7/7] xilinx_spips: allow mmio execution X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, pbonzini@redhat.com, rth@twiddle.net, fred.konrad@greensocs.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: KONRAD Frederic This allows to execute from the lqspi area. When the request_ptr is called the device loads 1024bytes from the SPI devi= ce. Then this code can be executed by the guest. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: KONRAD Frederic --- hw/ssi/xilinx_spips.c | 74 ++++++++++++++++++++++++++++++++++++++---------= ---- 1 file changed, 55 insertions(+), 19 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index da8adfa..e833028 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -496,6 +496,18 @@ static const MemoryRegionOps spips_ops =3D { .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 +static void xilinx_qspips_invalidate_mmio_ptr(XilinxQSPIPS *q) +{ + XilinxSPIPS *s =3D &q->parent_obj; + + if (q->lqspi_cached_addr !=3D ~0ULL) { + /* Invalidate the current mapped mmio */ + memory_region_invalidate_mmio_ptr(&s->mmlqspi, q->lqspi_cached_add= r, + LQSPI_CACHE_SIZE); + q->lqspi_cached_addr =3D ~0ULL; + } +} + static void xilinx_qspips_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { @@ -505,7 +517,7 @@ static void xilinx_qspips_write(void *opaque, hwaddr ad= dr, addr >>=3D 2; =20 if (addr =3D=3D R_LQSPI_CFG) { - q->lqspi_cached_addr =3D ~0ULL; + xilinx_qspips_invalidate_mmio_ptr(q); } } =20 @@ -517,27 +529,20 @@ static const MemoryRegionOps qspips_ops =3D { =20 #define LQSPI_CACHE_SIZE 1024 =20 -static uint64_t -lqspi_read(void *opaque, hwaddr addr, unsigned int size) +static void lqspi_load_cache(void *opaque, hwaddr addr) { - int i; XilinxQSPIPS *q =3D opaque; XilinxSPIPS *s =3D opaque; - uint32_t ret; - - if (addr >=3D q->lqspi_cached_addr && - addr <=3D q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { - uint8_t *retp =3D &q->lqspi_buf[addr - q->lqspi_cached_addr]; - ret =3D cpu_to_le32(*(uint32_t *)retp); - DB_PRINT_L(1, "addr: %08x, data: %08x\n", (unsigned)addr, - (unsigned)ret); - return ret; - } else { - int flash_addr =3D (addr / num_effective_busses(s)); - int slave =3D flash_addr >> LQSPI_ADDRESS_BITS; - int cache_entry =3D 0; - uint32_t u_page_save =3D s->regs[R_LQSPI_STS] & ~LQSPI_CFG_U_PAGE; - + int i; + int flash_addr =3D ((addr & ~(LQSPI_CACHE_SIZE - 1)) + / num_effective_busses(s)); + int slave =3D flash_addr >> LQSPI_ADDRESS_BITS; + int cache_entry =3D 0; + uint32_t u_page_save =3D s->regs[R_LQSPI_STS] & ~LQSPI_CFG_U_PAGE; + + if (addr < q->lqspi_cached_addr || + addr > q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { + xilinx_qspips_invalidate_mmio_ptr(q); s->regs[R_LQSPI_STS] &=3D ~LQSPI_CFG_U_PAGE; s->regs[R_LQSPI_STS] |=3D slave ? LQSPI_CFG_U_PAGE : 0; =20 @@ -589,12 +594,43 @@ lqspi_read(void *opaque, hwaddr addr, unsigned int si= ze) xilinx_spips_update_cs_lines(s); =20 q->lqspi_cached_addr =3D flash_addr * num_effective_busses(s); + } +} + +static void *lqspi_request_mmio_ptr(void *opaque, hwaddr addr, unsigned *s= ize, + unsigned *offset) +{ + XilinxQSPIPS *q =3D opaque; + hwaddr offset_within_the_region =3D addr & ~(LQSPI_CACHE_SIZE - 1); + + lqspi_load_cache(opaque, offset_within_the_region); + *size =3D LQSPI_CACHE_SIZE; + *offset =3D offset_within_the_region; + return q->lqspi_buf; +} + +static uint64_t +lqspi_read(void *opaque, hwaddr addr, unsigned int size) +{ + XilinxQSPIPS *q =3D opaque; + uint32_t ret; + + if (addr >=3D q->lqspi_cached_addr && + addr <=3D q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { + uint8_t *retp =3D &q->lqspi_buf[addr - q->lqspi_cached_addr]; + ret =3D cpu_to_le32(*(uint32_t *)retp); + DB_PRINT_L(1, "addr: %08x, data: %08x\n", (unsigned)addr, + (unsigned)ret); + return ret; + } else { + lqspi_load_cache(opaque, addr); return lqspi_read(opaque, addr, size); } } =20 static const MemoryRegionOps lqspi_ops =3D { .read =3D lqspi_read, + .request_ptr =3D lqspi_request_mmio_ptr, .endianness =3D DEVICE_NATIVE_ENDIAN, .valid =3D { .min_access_size =3D 1, --=20 2.7.4