From nobody Wed Nov 5 16:15:30 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 149701820092437.908569654303164; Fri, 9 Jun 2017 07:23:20 -0700 (PDT) Received: from localhost ([::1]:54965 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dJKoo-0001Nm-DH for importer@patchew.org; Fri, 09 Jun 2017 10:23:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41192) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dJKMI-00074b-Fu for qemu-devel@nongnu.org; Fri, 09 Jun 2017 09:53:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dJKMH-0006f6-9E for qemu-devel@nongnu.org; Fri, 09 Jun 2017 09:53:50 -0400 Received: from mx1.redhat.com ([209.132.183.28]:44998) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dJKMH-0006ex-04 for qemu-devel@nongnu.org; Fri, 09 Jun 2017 09:53:49 -0400 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id F2C3B4E4F5 for ; Fri, 9 Jun 2017 13:53:47 +0000 (UTC) Received: from pxdev.xzpeter.org.com (ovpn-12-95.pek2.redhat.com [10.72.12.95]) by smtp.corp.redhat.com (Postfix) with ESMTP id 0F262821E4; Fri, 9 Jun 2017 13:53:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com F2C3B4E4F5 Authentication-Results: ext-mx09.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx09.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=peterx@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com F2C3B4E4F5 From: Peter Xu To: qemu-devel@nongnu.org Date: Fri, 9 Jun 2017 21:53:28 +0800 Message-Id: <1497016409-22650-3-git-send-email-peterx@redhat.com> In-Reply-To: <1497016409-22650-1-git-send-email-peterx@redhat.com> References: <1497016409-22650-1-git-send-email-peterx@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Fri, 09 Jun 2017 13:53:48 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2 2/3] intel_iommu: cleanup vtd_{do_}iommu_translate() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marcel Apfelbaum , Jason Wang , peterx@redhat.com, "Michael S . Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" First, let vtd_do_iommu_translate() return a status, so that we explicitly knows whether error occured. Meanwhile, we make sure that IOMMUTLBEntry is filled in in that. Then, cleanup vtd_iommu_translate a bit. So even with PT we'll get a log now. Also, remove useless assignments. Signed-off-by: Peter Xu --- hw/i386/intel_iommu.c | 66 +++++++++++++++++++++++++++-----------= ---- hw/i386/intel_iommu_internal.h | 1 + hw/i386/trace-events | 1 + 3 files changed, 44 insertions(+), 24 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index a650151..24bdd00 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -1069,8 +1069,10 @@ out: * @devfn: The devfn, which is the combined of device and function number * @is_write: The access is a write operation * @entry: IOMMUTLBEntry that contain the addr to be translated and result + * + * Returns true if translation is successful, otherwise false. */ -static void vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus, +static bool vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus, uint8_t devfn, hwaddr addr, bool is_wri= te, IOMMUTLBEntry *entry) { @@ -1104,6 +1106,7 @@ static void vtd_do_iommu_translate(VTDAddressSpace *v= td_as, PCIBus *bus, page_mask =3D iotlb_entry->mask; goto out; } + /* Try to fetch context-entry from cache first */ if (cc_entry->context_cache_gen =3D=3D s->context_cache_gen) { trace_vtd_iotlb_cc_hit(bus_num, devfn, cc_entry->context_entry.hi, @@ -1121,7 +1124,7 @@ static void vtd_do_iommu_translate(VTDAddressSpace *v= td_as, PCIBus *bus, } else { vtd_report_dmar_fault(s, source_id, addr, ret_fr, is_write= ); } - return; + goto error; } /* Update context-cache */ trace_vtd_iotlb_cc_update(bus_num, devfn, ce.hi, ce.lo, @@ -1136,8 +1139,9 @@ static void vtd_do_iommu_translate(VTDAddressSpace *v= td_as, PCIBus *bus, * Also, let's ignore IOTLB caching as well for PT devices. */ if (vtd_ce_get_type(&ce) =3D=3D VTD_CONTEXT_TT_PASS_THROUGH) { + entry->iova =3D addr & VTD_PAGE_MASK; entry->translated_addr =3D entry->iova; - entry->addr_mask =3D VTD_PAGE_SIZE - 1; + entry->addr_mask =3D VTD_PAGE_MASK; entry->perm =3D IOMMU_RW; trace_vtd_translate_pt(source_id, entry->iova); =20 @@ -1152,7 +1156,7 @@ static void vtd_do_iommu_translate(VTDAddressSpace *v= td_as, PCIBus *bus, */ vtd_pt_enable_fast_path(s, source_id); =20 - return; + return true; } =20 ret_fr =3D vtd_iova_to_slpte(&ce, addr, is_write, &slpte, &level, @@ -1164,7 +1168,7 @@ static void vtd_do_iommu_translate(VTDAddressSpace *v= td_as, PCIBus *bus, } else { vtd_report_dmar_fault(s, source_id, addr, ret_fr, is_write); } - return; + goto error; } =20 page_mask =3D vtd_slpt_level_page_mask(level); @@ -1175,6 +1179,14 @@ out: entry->translated_addr =3D vtd_get_slpte_addr(slpte) & page_mask; entry->addr_mask =3D ~page_mask; entry->perm =3D IOMMU_ACCESS_FLAG(reads, writes); + return true; + +error: + entry->iova =3D 0; + entry->translated_addr =3D 0; + entry->addr_mask =3D 0; + entry->perm =3D IOMMU_NONE; + return false; } =20 static void vtd_root_table_setup(IntelIOMMUState *s) @@ -2252,32 +2264,38 @@ static IOMMUTLBEntry vtd_iommu_translate(MemoryRegi= on *iommu, hwaddr addr, { VTDAddressSpace *vtd_as =3D container_of(iommu, VTDAddressSpace, iommu= ); IntelIOMMUState *s =3D vtd_as->iommu_state; - IOMMUTLBEntry ret =3D { + IOMMUTLBEntry iotlb =3D { + /* We'll fill in the rest later. */ .target_as =3D &address_space_memory, - .iova =3D addr, - .translated_addr =3D 0, - .addr_mask =3D ~(hwaddr)0, - .perm =3D IOMMU_NONE, }; + bool success; =20 - if (!s->dmar_enabled) { + if (likely(s->dmar_enabled)) { + success =3D vtd_do_iommu_translate(vtd_as, vtd_as->bus, vtd_as->de= vfn, + addr, flag & IOMMU_WO, &iotlb); + } else { /* DMAR disabled, passthrough, use 4k-page*/ - ret.iova =3D addr & VTD_PAGE_MASK_4K; - ret.translated_addr =3D addr & VTD_PAGE_MASK_4K; - ret.addr_mask =3D ~VTD_PAGE_MASK_4K; - ret.perm =3D IOMMU_RW; - return ret; + iotlb.iova =3D addr & VTD_PAGE_MASK_4K; + iotlb.translated_addr =3D addr & VTD_PAGE_MASK_4K; + iotlb.addr_mask =3D ~VTD_PAGE_MASK_4K; + iotlb.perm =3D IOMMU_RW; + success =3D true; } =20 - vtd_do_iommu_translate(vtd_as, vtd_as->bus, vtd_as->devfn, addr, - flag & IOMMU_WO, &ret); - - trace_vtd_dmar_translate(pci_bus_num(vtd_as->bus), - VTD_PCI_SLOT(vtd_as->devfn), - VTD_PCI_FUNC(vtd_as->devfn), - ret.iova, ret.translated_addr, ret.addr_mask); + if (likely(success)) { + trace_vtd_dmar_translate(pci_bus_num(vtd_as->bus), + VTD_PCI_SLOT(vtd_as->devfn), + VTD_PCI_FUNC(vtd_as->devfn), + iotlb.iova, iotlb.translated_addr, + iotlb.addr_mask); + } else { + trace_vtd_err_dmar_translate(pci_bus_num(vtd_as->bus), + VTD_PCI_SLOT(vtd_as->devfn), + VTD_PCI_FUNC(vtd_as->devfn), + iotlb.iova); + } =20 - return ret; + return iotlb; } =20 static void vtd_iommu_notify_flag_changed(MemoryRegion *iommu, diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 0e73a65..f50ecd8 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -384,6 +384,7 @@ typedef struct VTDIOTLBPageInvInfo VTDIOTLBPageInvInfo; /* Pagesize of VTD paging structures, including root and context tables */ #define VTD_PAGE_SHIFT 12 #define VTD_PAGE_SIZE (1ULL << VTD_PAGE_SHIFT) +#define VTD_PAGE_MASK (VTD_PAGE_SIZE - 1) =20 #define VTD_PAGE_SHIFT_4K 12 #define VTD_PAGE_MASK_4K (~((1ULL << VTD_PAGE_SHIFT_4K) - 1)) diff --git a/hw/i386/trace-events b/hw/i386/trace-events index 8da20c3..5f111d6 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -73,6 +73,7 @@ vtd_err_dmar_iova_overflow(uint64_t iova) "iova 0x%"PRIx64 vtd_err_dmar_slpte_read_error(uint64_t iova, int level) "iova 0x%"PRIx64" = level %d" vtd_err_dmar_slpte_perm_error(uint64_t iova, int level, uint64_t slpte, bo= ol is_write) "iova 0x%"PRIx64" level %d slpte 0x%"PRIx64" write %d" vtd_err_dmar_slpte_resv_error(uint64_t iova, int level, uint64_t slpte) "i= ova 0x%"PRIx64" level %d slpte 0x%"PRIx64 +vtd_err_dmar_translate(uint8_t bus, uint8_t slot, uint8_t func, uint64_t i= ova) "dev %02x:%02x.%02x iova 0x%"PRIx64 vtd_err_qi_enable(uint16_t tail) "tail 0x%"PRIx16 vtd_err_qi_disable(uint16_t head, uint16_t tail, int type) "head 0x%"PRIx1= 6" tail 0x%"PRIx16" last_desc_type %d" vtd_err_qi_tail(uint16_t tail, uint16_t size) "tail 0x%"PRIx16" size 0x%"P= RIx16 --=20 2.7.4