From nobody Wed Nov 5 14:49:31 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1496929662032796.7903024954679; Thu, 8 Jun 2017 06:47:42 -0700 (PDT) Received: from localhost ([::1]:49713 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dIxmm-0001Fr-EG for importer@patchew.org; Thu, 08 Jun 2017 09:47:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48109) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dIxi4-0005eJ-4i for qemu-devel@nongnu.org; Thu, 08 Jun 2017 09:42:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dIxi3-0006yt-3y for qemu-devel@nongnu.org; Thu, 08 Jun 2017 09:42:48 -0400 Received: from 6.mo178.mail-out.ovh.net ([46.105.53.132]:53927) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dIxi2-0006yT-TU for qemu-devel@nongnu.org; Thu, 08 Jun 2017 09:42:47 -0400 Received: from player728.ha.ovh.net (b6.ovh.net [213.186.33.56]) by mo178.mail-out.ovh.net (Postfix) with ESMTP id ADE723EAC7 for ; Thu, 8 Jun 2017 15:42:45 +0200 (CEST) Received: from [192.168.0.243] (gar31-1-82-66-74-139.fbx.proxad.net [82.66.74.139]) (Authenticated sender: groug@kaod.org) by player728.ha.ovh.net (Postfix) with ESMTPA id 68DAC5400A9; Thu, 8 Jun 2017 15:42:42 +0200 (CEST) From: Greg Kurz To: qemu-devel@nongnu.org Date: Thu, 08 Jun 2017 15:42:41 +0200 Message-ID: <149692936183.12119.5013623492394505174.stgit@bahia> In-Reply-To: <149692935202.12119.3614006195497745877.stgit@bahia> References: <149692935202.12119.3614006195497745877.stgit@bahia> User-Agent: StGit/0.17.1-20-gc0b1b-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Ovh-Tracer-Id: 6076763276249176550 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeeljedrieefgdeikecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.53.132 Subject: [Qemu-devel] [PATCH v4 1/6] xics: introduce macros for ICP/ICS link properties X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, Cedric Le Goater , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 These properties are part of the XICS API. They deserve to appear explicitely in the XICS header file. Signed-off-by: Greg Kurz --- hw/intc/xics.c | 8 ++++---- hw/ppc/pnv_core.c | 3 ++- hw/ppc/pnv_psi.c | 3 ++- hw/ppc/spapr.c | 3 ++- hw/ppc/spapr_cpu_core.c | 3 ++- include/hw/ppc/xics.h | 4 ++++ 6 files changed, 16 insertions(+), 8 deletions(-) diff --git a/hw/intc/xics.c b/hw/intc/xics.c index ec73f02144c9..aa2c4e744f65 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -346,9 +346,9 @@ static void icp_realize(DeviceState *dev, Error **errp) Object *obj; Error *err =3D NULL; =20 - obj =3D object_property_get_link(OBJECT(dev), "xics", &err); + obj =3D object_property_get_link(OBJECT(dev), ICP_PROP_XICS, &err); if (!obj) { - error_setg(errp, "%s: required link 'xics' not found: %s", + error_setg(errp, "%s: required link '" ICP_PROP_XICS "' not found:= %s", __func__, error_get_pretty(err)); return; } @@ -654,9 +654,9 @@ static void ics_base_realize(DeviceState *dev, Error **= errp) Object *obj; Error *err =3D NULL; =20 - obj =3D object_property_get_link(OBJECT(dev), "xics", &err); + obj =3D object_property_get_link(OBJECT(dev), ICS_PROP_XICS, &err); if (!obj) { - error_setg(errp, "%s: required link 'xics' not found: %s", + error_setg(errp, "%s: required link '" ICS_PROP_XICS "' not found:= %s", __func__, error_get_pretty(err)); return; } diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index e8a9a94d5a24..0b6e72950ca3 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -121,7 +121,8 @@ static void pnv_core_realize_child(Object *child, XICSF= abric *xi, Error **errp) obj =3D object_new(TYPE_PNV_ICP); object_property_add_child(OBJECT(cpu), "icp", obj, &error_abort); object_unref(obj); - object_property_add_const_link(obj, "xics", OBJECT(xi), &error_abort); + object_property_add_const_link(obj, ICP_PROP_XICS, OBJECT(xi), + &error_abort); object_property_set_bool(obj, true, "realized", &local_err); if (local_err) { error_propagate(errp, local_err); diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c index 2bf5bfe3fdd6..9876c266223d 100644 --- a/hw/ppc/pnv_psi.c +++ b/hw/ppc/pnv_psi.c @@ -474,7 +474,8 @@ static void pnv_psi_realize(DeviceState *dev, Error **e= rrp) } =20 /* Create PSI interrupt control source */ - object_property_add_const_link(OBJECT(ics), "xics", obj, &error_abort= ); + object_property_add_const_link(OBJECT(ics), ICS_PROP_XICS, obj, + &error_abort); object_property_set_int(OBJECT(ics), PSI_NUM_INTERRUPTS, "nr-irqs", &e= rr); if (err) { error_propagate(errp, err); diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 01dda9ea9fb7..b2951d7618d6 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -107,7 +107,8 @@ static ICSState *spapr_ics_create(sPAPRMachineState *sp= apr, =20 obj =3D object_new(type_ics); object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort); - object_property_add_const_link(obj, "xics", OBJECT(spapr), &error_abor= t); + object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr), + &error_abort); object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err); if (local_err) { goto error; diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 029a14120edd..e81879c7cad7 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -145,7 +145,8 @@ static void spapr_cpu_core_realize_child(Object *child,= Error **errp) obj =3D object_new(spapr->icp_type); object_property_add_child(OBJECT(cpu), "icp", obj, &error_abort); object_unref(obj); - object_property_add_const_link(obj, "xics", OBJECT(spapr), &error_abor= t); + object_property_add_const_link(obj, ICP_PROP_XICS, OBJECT(spapr), + &error_abort); object_property_set_bool(obj, true, "realized", &local_err); if (local_err) { goto error; diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h index 40a506eacfb4..31145326ebf9 100644 --- a/include/hw/ppc/xics.h +++ b/include/hw/ppc/xics.h @@ -86,6 +86,8 @@ struct ICPState { XICSFabric *xics; }; =20 +#define ICP_PROP_XICS "xics" + struct PnvICPState { ICPState parent_obj; =20 @@ -130,6 +132,8 @@ struct ICSState { XICSFabric *xics; }; =20 +#define ICS_PROP_XICS "xics" + static inline bool ics_valid_irq(ICSState *ics, uint32_t nr) { return (ics->offset !=3D 0) && (nr >=3D ics->offset) From nobody Wed Nov 5 14:49:32 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1496929632683283.12989944332287; Thu, 8 Jun 2017 06:47:12 -0700 (PDT) Received: from localhost ([::1]:49711 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dIxmH-0000pT-Qp for importer@patchew.org; Thu, 08 Jun 2017 09:47:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48164) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dIxiF-0005oh-Le for qemu-devel@nongnu.org; Thu, 08 Jun 2017 09:43:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dIxiC-000794-HZ for qemu-devel@nongnu.org; Thu, 08 Jun 2017 09:42:59 -0400 Received: from 9.mo178.mail-out.ovh.net ([46.105.75.45]:35833) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dIxiC-00077U-BB for qemu-devel@nongnu.org; Thu, 08 Jun 2017 09:42:56 -0400 Received: from player728.ha.ovh.net (b6.ovh.net [213.186.33.56]) by mo178.mail-out.ovh.net (Postfix) with ESMTP id CC5903EAC7 for ; Thu, 8 Jun 2017 15:42:54 +0200 (CEST) Received: from [192.168.0.243] (gar31-1-82-66-74-139.fbx.proxad.net [82.66.74.139]) (Authenticated sender: groug@kaod.org) by player728.ha.ovh.net (Postfix) with ESMTPA id 8868F5400CA; Thu, 8 Jun 2017 15:42:51 +0200 (CEST) From: Greg Kurz To: qemu-devel@nongnu.org Date: Thu, 08 Jun 2017 15:42:50 +0200 Message-ID: <149692937073.12119.15678075319946323731.stgit@bahia> In-Reply-To: <149692935202.12119.3614006195497745877.stgit@bahia> References: <149692935202.12119.3614006195497745877.stgit@bahia> User-Agent: StGit/0.17.1-20-gc0b1b-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Ovh-Tracer-Id: 6079296547855833574 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeeljedrieefgdeikecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.75.45 Subject: [Qemu-devel] [PATCH v4 2/6] xics: pass appropriate types to realize() handlers. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, Cedric Le Goater , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 It makes more sense to pass an IPCState * to handlers of ICPStateClass instead of a DeviceState *, if only to benefit from compile time type checking. The same goes with ICSStateClass. While here, we also change the declaration of ICPStateClass in xics.h for consistency. Signed-off-by: Greg Kurz --- hw/intc/xics.c | 10 ++++------ hw/intc/xics_kvm.c | 6 ++---- hw/intc/xics_pnv.c | 6 +++--- include/hw/ppc/xics.h | 8 ++++---- 4 files changed, 13 insertions(+), 17 deletions(-) diff --git a/hw/intc/xics.c b/hw/intc/xics.c index aa2c4e744f65..f74a96e932d7 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -356,7 +356,7 @@ static void icp_realize(DeviceState *dev, Error **errp) icp->xics =3D XICS_FABRIC(obj); =20 if (icpc->realize) { - icpc->realize(dev, errp); + icpc->realize(icp, errp); } =20 qemu_register_reset(icp_reset, dev); @@ -606,10 +606,8 @@ static void ics_simple_initfn(Object *obj) ics->offset =3D XICS_IRQ_BASE; } =20 -static void ics_simple_realize(DeviceState *dev, Error **errp) +static void ics_simple_realize(ICSState *ics, Error **errp) { - ICSState *ics =3D ICS_SIMPLE(dev); - if (!ics->nr_irqs) { error_setg(errp, "Number of interrupts needs to be greater 0"); return; @@ -617,7 +615,7 @@ static void ics_simple_realize(DeviceState *dev, Error = **errp) ics->irqs =3D g_malloc0(ics->nr_irqs * sizeof(ICSIRQState)); ics->qirqs =3D qemu_allocate_irqs(ics_simple_set_irq, ics, ics->nr_irq= s); =20 - qemu_register_reset(ics_simple_reset, dev); + qemu_register_reset(ics_simple_reset, ics); } =20 static Property ics_simple_properties[] =3D { @@ -664,7 +662,7 @@ static void ics_base_realize(DeviceState *dev, Error **= errp) =20 =20 if (icsc->realize) { - icsc->realize(dev, errp); + icsc->realize(ics, errp); } } =20 diff --git a/hw/intc/xics_kvm.c b/hw/intc/xics_kvm.c index 45bf110b51e6..41c5b9439562 100644 --- a/hw/intc/xics_kvm.c +++ b/hw/intc/xics_kvm.c @@ -328,10 +328,8 @@ static void ics_kvm_reset(void *dev) ics_set_kvm_state(ics, 1); } =20 -static void ics_kvm_realize(DeviceState *dev, Error **errp) +static void ics_kvm_realize(ICSState *ics, Error **errp) { - ICSState *ics =3D ICS_SIMPLE(dev); - if (!ics->nr_irqs) { error_setg(errp, "Number of interrupts needs to be greater 0"); return; @@ -339,7 +337,7 @@ static void ics_kvm_realize(DeviceState *dev, Error **e= rrp) ics->irqs =3D g_malloc0(ics->nr_irqs * sizeof(ICSIRQState)); ics->qirqs =3D qemu_allocate_irqs(ics_kvm_set_irq, ics, ics->nr_irqs); =20 - qemu_register_reset(ics_kvm_reset, dev); + qemu_register_reset(ics_kvm_reset, ics); } =20 static void ics_kvm_class_init(ObjectClass *klass, void *data) diff --git a/hw/intc/xics_pnv.c b/hw/intc/xics_pnv.c index 12ae605f10e8..2a955a894678 100644 --- a/hw/intc/xics_pnv.c +++ b/hw/intc/xics_pnv.c @@ -159,11 +159,11 @@ static const MemoryRegionOps pnv_icp_ops =3D { }, }; =20 -static void pnv_icp_realize(DeviceState *dev, Error **errp) +static void pnv_icp_realize(ICPState *icp, Error **errp) { - PnvICPState *icp =3D PNV_ICP(dev); + PnvICPState *pnv_icp =3D PNV_ICP(icp); =20 - memory_region_init_io(&icp->mmio, OBJECT(dev), &pnv_icp_ops, + memory_region_init_io(&pnv_icp->mmio, OBJECT(icp), &pnv_icp_ops, icp, "icp-thread", 0x1000); } =20 diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h index 31145326ebf9..797df82fefc0 100644 --- a/include/hw/ppc/xics.h +++ b/include/hw/ppc/xics.h @@ -65,9 +65,9 @@ typedef struct XICSFabric XICSFabric; struct ICPStateClass { DeviceClass parent_class; =20 - void (*realize)(DeviceState *dev, Error **errp); - void (*pre_save)(ICPState *s); - int (*post_load)(ICPState *s, int version_id); + void (*realize)(ICPState *icp, Error **errp); + void (*pre_save)(ICPState *icp); + int (*post_load)(ICPState *icp, int version_id); void (*cpu_setup)(ICPState *icp, PowerPCCPU *cpu); void (*reset)(ICPState *icp); }; @@ -113,7 +113,7 @@ struct PnvICPState { struct ICSStateClass { DeviceClass parent_class; =20 - void (*realize)(DeviceState *dev, Error **errp); + void (*realize)(ICSState *s, Error **errp); void (*pre_save)(ICSState *s); int (*post_load)(ICSState *s, int version_id); void (*reject)(ICSState *s, uint32_t irq); From nobody Wed Nov 5 14:49:32 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1496929781421245.3486834091184; Thu, 8 Jun 2017 06:49:41 -0700 (PDT) Received: from localhost ([::1]:49723 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dIxoh-0002x7-PS for importer@patchew.org; Thu, 08 Jun 2017 09:49:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48218) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dIxiO-0005yH-I8 for qemu-devel@nongnu.org; Thu, 08 Jun 2017 09:43:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dIxiL-0007JN-EN for qemu-devel@nongnu.org; Thu, 08 Jun 2017 09:43:08 -0400 Received: from 8.mo178.mail-out.ovh.net ([46.105.74.227]:47667) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dIxiL-0007II-3b for qemu-devel@nongnu.org; Thu, 08 Jun 2017 09:43:05 -0400 Received: from player728.ha.ovh.net (b6.ovh.net [213.186.33.56]) by mo178.mail-out.ovh.net (Postfix) with ESMTP id ADF553EA9C for ; Thu, 8 Jun 2017 15:43:03 +0200 (CEST) Received: from [192.168.0.243] (gar31-1-82-66-74-139.fbx.proxad.net [82.66.74.139]) (Authenticated sender: groug@kaod.org) by player728.ha.ovh.net (Postfix) with ESMTPA id 645865400D5; Thu, 8 Jun 2017 15:43:00 +0200 (CEST) From: Greg Kurz To: qemu-devel@nongnu.org Date: Thu, 08 Jun 2017 15:42:59 +0200 Message-ID: <149692937985.12119.13044357560316687626.stgit@bahia> In-Reply-To: <149692935202.12119.3614006195497745877.stgit@bahia> References: <149692935202.12119.3614006195497745877.stgit@bahia> User-Agent: StGit/0.17.1-20-gc0b1b-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Ovh-Tracer-Id: 6081829823465757158 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeeljedrieefgdeikecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.74.227 Subject: [Qemu-devel] [PATCH v4 3/6] xics: setup cpu at realize time X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, Cedric Le Goater , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Until recently, spapr used to allocate ICPState objects for the lifetime of the machine. They would only be associated to vCPUs in xics_cpu_setup() when plugging a CPU core. Now that ICPState objects have the same lifecycle as vCPUs, it is possible to associate them during realization. This patch hence open-codes xics_cpu_setup() in icp_realize(). The vCPU is passed as a property. Note that vCPU now needs to be realized first for the IRQs to be allocated. It also needs to resetted before ICPState realization in order to synchronize with KVM. Since ICPState objects are freed when unrealized, xics_cpu_destroy() isn't needed anymore and can be safely dropped. Signed-off-by: Greg Kurz Reviewed-by: C=C3=A9dric Le Goater --- v4: - renamed property from "cs" to "cpu" and make it a macro (ICP_PROP_CPU) - fixed copy/paste mistake in error message in icp_realize() --- hw/intc/xics.c | 76 ++++++++++++++++++++-----------------------= ---- hw/ppc/pnv_core.c | 18 +++++------ hw/ppc/spapr_cpu_core.c | 23 ++++++-------- include/hw/ppc/xics.h | 3 +- 4 files changed, 51 insertions(+), 69 deletions(-) diff --git a/hw/intc/xics.c b/hw/intc/xics.c index f74a96e932d7..fdbfddffeea5 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -38,50 +38,6 @@ #include "monitor/monitor.h" #include "hw/intc/intc.h" =20 -void xics_cpu_destroy(XICSFabric *xi, PowerPCCPU *cpu) -{ - CPUState *cs =3D CPU(cpu); - ICPState *icp =3D ICP(cpu->intc); - - assert(icp); - assert(cs =3D=3D icp->cs); - - icp->output =3D NULL; - icp->cs =3D NULL; -} - -void xics_cpu_setup(XICSFabric *xi, PowerPCCPU *cpu, ICPState *icp) -{ - CPUState *cs =3D CPU(cpu); - CPUPPCState *env =3D &cpu->env; - ICPStateClass *icpc; - - assert(icp); - - cpu->intc =3D OBJECT(icp); - icp->cs =3D cs; - - icpc =3D ICP_GET_CLASS(icp); - if (icpc->cpu_setup) { - icpc->cpu_setup(icp, cpu); - } - - switch (PPC_INPUT(env)) { - case PPC_FLAGS_INPUT_POWER7: - icp->output =3D env->irq_inputs[POWER7_INPUT_INT]; - break; - - case PPC_FLAGS_INPUT_970: - icp->output =3D env->irq_inputs[PPC970_INPUT_INT]; - break; - - default: - error_report("XICS interrupt controller does not support this CPU " - "bus model"); - abort(); - } -} - void icp_pic_print_info(ICPState *icp, Monitor *mon) { int cpu_index =3D icp->cs ? icp->cs->cpu_index : -1; @@ -343,6 +299,8 @@ static void icp_realize(DeviceState *dev, Error **errp) { ICPState *icp =3D ICP(dev); ICPStateClass *icpc =3D ICP_GET_CLASS(dev); + PowerPCCPU *cpu; + CPUPPCState *env; Object *obj; Error *err =3D NULL; =20 @@ -355,6 +313,36 @@ static void icp_realize(DeviceState *dev, Error **errp) =20 icp->xics =3D XICS_FABRIC(obj); =20 + obj =3D object_property_get_link(OBJECT(dev), ICP_PROP_CPU, &err); + if (!obj) { + error_setg(errp, "%s: required link '" ICP_PROP_CPU "' not found: = %s", + __func__, error_get_pretty(err)); + return; + } + + cpu =3D POWERPC_CPU(obj); + cpu->intc =3D OBJECT(icp); + icp->cs =3D CPU(obj); + + if (icpc->cpu_setup) { + icpc->cpu_setup(icp, cpu); + } + + env =3D &cpu->env; + switch (PPC_INPUT(env)) { + case PPC_FLAGS_INPUT_POWER7: + icp->output =3D env->irq_inputs[POWER7_INPUT_INT]; + break; + + case PPC_FLAGS_INPUT_970: + icp->output =3D env->irq_inputs[PPC970_INPUT_INT]; + break; + + default: + error_setg(errp, "XICS interrupt controller does not support this = CPU bus model"); + return; + } + if (icpc->realize) { icpc->realize(icp, errp); } diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 0b6e72950ca3..c7b00b610c1e 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -118,20 +118,20 @@ static void pnv_core_realize_child(Object *child, XIC= SFabric *xi, Error **errp) PowerPCCPU *cpu =3D POWERPC_CPU(cs); Object *obj; =20 - obj =3D object_new(TYPE_PNV_ICP); - object_property_add_child(OBJECT(cpu), "icp", obj, &error_abort); - object_unref(obj); - object_property_add_const_link(obj, ICP_PROP_XICS, OBJECT(xi), - &error_abort); - object_property_set_bool(obj, true, "realized", &local_err); + object_property_set_bool(child, true, "realized", &local_err); if (local_err) { error_propagate(errp, local_err); return; } =20 - object_property_set_bool(child, true, "realized", &local_err); + obj =3D object_new(TYPE_PNV_ICP); + object_property_add_child(child, "icp", obj, NULL); + object_unref(obj); + object_property_add_const_link(obj, ICP_PROP_XICS, OBJECT(xi), + &error_abort); + object_property_add_const_link(obj, ICP_PROP_CPU, child, &error_abort); + object_property_set_bool(obj, true, "realized", &local_err); if (local_err) { - object_unparent(obj); error_propagate(errp, local_err); return; } @@ -142,8 +142,6 @@ static void pnv_core_realize_child(Object *child, XICSF= abric *xi, Error **errp) error_propagate(errp, local_err); return; } - - xics_cpu_setup(xi, cpu, ICP(obj)); } =20 static void pnv_core_realize(DeviceState *dev, Error **errp) diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index e81879c7cad7..9fb896b407db 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -53,9 +53,6 @@ static void spapr_cpu_reset(void *opaque) =20 static void spapr_cpu_destroy(PowerPCCPU *cpu) { - sPAPRMachineState *spapr =3D SPAPR_MACHINE(qdev_get_machine()); - - xics_cpu_destroy(XICS_FABRIC(spapr), cpu); qemu_unregister_reset(spapr_cpu_reset, cpu); } =20 @@ -140,29 +137,29 @@ static void spapr_cpu_core_realize_child(Object *chil= d, Error **errp) sPAPRMachineState *spapr =3D SPAPR_MACHINE(qdev_get_machine()); CPUState *cs =3D CPU(child); PowerPCCPU *cpu =3D POWERPC_CPU(cs); - Object *obj; + Object *obj =3D NULL; =20 - obj =3D object_new(spapr->icp_type); - object_property_add_child(OBJECT(cpu), "icp", obj, &error_abort); - object_unref(obj); - object_property_add_const_link(obj, ICP_PROP_XICS, OBJECT(spapr), - &error_abort); - object_property_set_bool(obj, true, "realized", &local_err); + object_property_set_bool(child, true, "realized", &local_err); if (local_err) { goto error; } =20 - object_property_set_bool(child, true, "realized", &local_err); + spapr_cpu_init(spapr, cpu, &local_err); if (local_err) { goto error; } =20 - spapr_cpu_init(spapr, cpu, &local_err); + obj =3D object_new(spapr->icp_type); + object_property_add_child(child, "icp", obj, &error_abort); + object_unref(obj); + object_property_add_const_link(obj, ICP_PROP_XICS, OBJECT(spapr), + &error_abort); + object_property_add_const_link(obj, ICP_PROP_CPU, child, &error_abort); + object_property_set_bool(obj, true, "realized", &local_err); if (local_err) { goto error; } =20 - xics_cpu_setup(XICS_FABRIC(spapr), cpu, ICP(obj)); return; =20 error: diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h index 797df82fefc0..37b8fb1e8817 100644 --- a/include/hw/ppc/xics.h +++ b/include/hw/ppc/xics.h @@ -87,6 +87,7 @@ struct ICPState { }; =20 #define ICP_PROP_XICS "xics" +#define ICP_PROP_CPU "cpu" =20 struct PnvICPState { ICPState parent_obj; @@ -187,8 +188,6 @@ void spapr_dt_xics(int nr_servers, void *fdt, uint32_t = phandle); =20 qemu_irq xics_get_qirq(XICSFabric *xi, int irq); ICPState *xics_icp_get(XICSFabric *xi, int server); -void xics_cpu_setup(XICSFabric *xi, PowerPCCPU *cpu, ICPState *icp); -void xics_cpu_destroy(XICSFabric *xi, PowerPCCPU *cpu); =20 /* Internal XICS interfaces */ void icp_set_cppr(ICPState *icp, uint8_t cppr); From nobody Wed Nov 5 14:49:32 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1496929854372736.3879449527483; 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Thu, 8 Jun 2017 15:43:09 +0200 (CEST) From: Greg Kurz To: qemu-devel@nongnu.org Date: Thu, 08 Jun 2017 15:43:08 +0200 Message-ID: <149692938872.12119.17948850600182624221.stgit@bahia> In-Reply-To: <149692935202.12119.3614006195497745877.stgit@bahia> References: <149692935202.12119.3614006195497745877.stgit@bahia> User-Agent: StGit/0.17.1-20-gc0b1b-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Ovh-Tracer-Id: 6084644573877017062 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeeljedrieefgdeikecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.76.150 Subject: [Qemu-devel] [PATCH v4 4/6] xics: drop ICPStateClass::cpu_setup() handler X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, Cedric Le Goater , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 The cpu_setup() handler is only implemented by xics_kvm, where it really does a typical "realize" job. Moreover, the realize() handler is called shortly after cpu_setup(), on the same path. This patch converts xics_kvm to implement realize() instead of cpu_setup(). Signed-off-by: Greg Kurz Reviewed-by: C=C3=A9dric Le Goater --- hw/intc/xics.c | 4 ---- hw/intc/xics_kvm.c | 12 ++++++------ include/hw/ppc/xics.h | 1 - 3 files changed, 6 insertions(+), 11 deletions(-) diff --git a/hw/intc/xics.c b/hw/intc/xics.c index fdbfddffeea5..7ccfb53c55a0 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -324,10 +324,6 @@ static void icp_realize(DeviceState *dev, Error **errp) cpu->intc =3D OBJECT(icp); icp->cs =3D CPU(obj); =20 - if (icpc->cpu_setup) { - icpc->cpu_setup(icp, cpu); - } - env =3D &cpu->env; switch (PPC_INPUT(env)) { case PPC_FLAGS_INPUT_POWER7: diff --git a/hw/intc/xics_kvm.c b/hw/intc/xics_kvm.c index 41c5b9439562..3091ad3ac2c8 100644 --- a/hw/intc/xics_kvm.c +++ b/hw/intc/xics_kvm.c @@ -115,9 +115,9 @@ static void icp_kvm_reset(ICPState *icp) icp_set_kvm_state(icp, 1); } =20 -static void icp_kvm_cpu_setup(ICPState *icp, PowerPCCPU *cpu) +static void icp_kvm_realize(ICPState *icp, Error **errp) { - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D icp->cs; KVMEnabledICP *enabled_icp; unsigned long vcpu_id =3D kvm_arch_vcpu_id(cs); int ret; @@ -139,9 +139,9 @@ static void icp_kvm_cpu_setup(ICPState *icp, PowerPCCPU= *cpu) =20 ret =3D kvm_vcpu_enable_cap(cs, KVM_CAP_IRQ_XICS, 0, kernel_xics_fd, v= cpu_id); if (ret < 0) { - error_report("Unable to connect CPU%ld to kernel XICS: %s", vcpu_i= d, - strerror(errno)); - exit(1); + error_setg(errp, "Unable to connect CPU%ld to kernel XICS: %s", vc= pu_id, + strerror(errno)); + return; } enabled_icp =3D g_malloc(sizeof(*enabled_icp)); enabled_icp->vcpu_id =3D vcpu_id; @@ -154,7 +154,7 @@ static void icp_kvm_class_init(ObjectClass *klass, void= *data) =20 icpc->pre_save =3D icp_get_kvm_state; icpc->post_load =3D icp_set_kvm_state; - icpc->cpu_setup =3D icp_kvm_cpu_setup; + icpc->realize =3D icp_kvm_realize; icpc->reset =3D icp_kvm_reset; } =20 diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h index 37b8fb1e8817..28d248abad61 100644 --- a/include/hw/ppc/xics.h +++ b/include/hw/ppc/xics.h @@ -68,7 +68,6 @@ struct ICPStateClass { void (*realize)(ICPState *icp, Error **errp); void (*pre_save)(ICPState *icp); int (*post_load)(ICPState *icp, int version_id); - void (*cpu_setup)(ICPState *icp, PowerPCCPU *cpu); void (*reset)(ICPState *icp); }; =20 From nobody Wed Nov 5 14:49:32 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1496929922830640.3498835408976; Thu, 8 Jun 2017 06:52:02 -0700 (PDT) Received: from localhost ([::1]:49749 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dIxqz-0004dZ-GA for importer@patchew.org; Thu, 08 Jun 2017 09:52:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48314) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dIxie-0006T0-Jl for qemu-devel@nongnu.org; Thu, 08 Jun 2017 09:43:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dIxid-0007V0-Me for qemu-devel@nongnu.org; Thu, 08 Jun 2017 09:43:24 -0400 Received: from 10.mo178.mail-out.ovh.net ([46.105.76.150]:42735) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dIxid-0007Ua-Fg for qemu-devel@nongnu.org; Thu, 08 Jun 2017 09:43:23 -0400 Received: from player728.ha.ovh.net (b6.ovh.net [213.186.33.56]) by mo178.mail-out.ovh.net (Postfix) with ESMTP id 2A1923EAE1 for ; Thu, 8 Jun 2017 15:43:22 +0200 (CEST) Received: from [192.168.0.243] (gar31-1-82-66-74-139.fbx.proxad.net [82.66.74.139]) (Authenticated sender: groug@kaod.org) by player728.ha.ovh.net (Postfix) with ESMTPA id E19D65400D2; Thu, 8 Jun 2017 15:43:18 +0200 (CEST) From: Greg Kurz To: qemu-devel@nongnu.org Date: Thu, 08 Jun 2017 15:43:18 +0200 Message-ID: <149692939833.12119.5229563110691809599.stgit@bahia> In-Reply-To: <149692935202.12119.3614006195497745877.stgit@bahia> References: <149692935202.12119.3614006195497745877.stgit@bahia> User-Agent: StGit/0.17.1-20-gc0b1b-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Ovh-Tracer-Id: 6087177848911927782 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeeljedrieefgdeikecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.76.150 Subject: [Qemu-devel] [PATCH v4 5/6] xics: directly register ICPState objects to vmstate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, Cedric Le Goater , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 The ICPState objects are currently registered to vmstate as qdev objects. Their instance ids are hence computed automatically in the migration code, and thus depends on the order the CPU cores were plugged. If the destination had its CPU cores plugged in a different order than the source, then ICPState objects will have different instance_ids and load the wrong state. Since CPU objects have a reliable cpu_index which is already used as instance_id in vmstate, let's use it for ICPState as well. Signed-off-by: Greg Kurz --- hw/intc/xics.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/intc/xics.c b/hw/intc/xics.c index 7ccfb53c55a0..faa5c631f655 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -344,10 +344,14 @@ static void icp_realize(DeviceState *dev, Error **err= p) } =20 qemu_register_reset(icp_reset, dev); + vmstate_register(NULL, icp->cs->cpu_index, &vmstate_icp_server, icp); } =20 static void icp_unrealize(DeviceState *dev, Error **errp) { + ICPState *icp =3D ICP(dev); + + vmstate_unregister(NULL, &vmstate_icp_server, icp); qemu_unregister_reset(icp_reset, dev); } =20 @@ -355,7 +359,6 @@ static void icp_class_init(ObjectClass *klass, void *da= ta) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 - dc->vmsd =3D &vmstate_icp_server; dc->realize =3D icp_realize; dc->unrealize =3D icp_unrealize; } From nobody Wed Nov 5 14:49:32 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 149692998948640.01704640110199; Thu, 8 Jun 2017 06:53:09 -0700 (PDT) Received: from localhost ([::1]:49752 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dIxs3-0005xq-NE for importer@patchew.org; Thu, 08 Jun 2017 09:53:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48358) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dIxiq-0006dI-2X for qemu-devel@nongnu.org; Thu, 08 Jun 2017 09:43:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dIxim-0007Yk-T7 for qemu-devel@nongnu.org; Thu, 08 Jun 2017 09:43:36 -0400 Received: from 1.mo178.mail-out.ovh.net ([178.33.251.53]:52732) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dIxim-0007YS-JP for qemu-devel@nongnu.org; Thu, 08 Jun 2017 09:43:32 -0400 Received: from player728.ha.ovh.net (b6.ovh.net [213.186.33.56]) by mo178.mail-out.ovh.net (Postfix) with ESMTP id 0B1423EAD8 for ; Thu, 8 Jun 2017 15:43:31 +0200 (CEST) Received: from [192.168.0.243] (gar31-1-82-66-74-139.fbx.proxad.net [82.66.74.139]) (Authenticated sender: groug@kaod.org) by player728.ha.ovh.net (Postfix) with ESMTPA id B5B7D5400CB; Thu, 8 Jun 2017 15:43:27 +0200 (CEST) From: Greg Kurz To: qemu-devel@nongnu.org Date: Thu, 08 Jun 2017 15:43:27 +0200 Message-ID: <149692940719.12119.1126399233332975562.stgit@bahia> In-Reply-To: <149692935202.12119.3614006195497745877.stgit@bahia> References: <149692935202.12119.3614006195497745877.stgit@bahia> User-Agent: StGit/0.17.1-20-gc0b1b-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Ovh-Tracer-Id: 6089429648106494438 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeeljedrieefgdeikecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 178.33.251.53 Subject: [Qemu-devel] [PATCH v4 6/6] spapr: fix migration of ICPState objects from/to older QEMU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, Cedric Le Goater , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Commit 5bc8d26de20c ("spapr: allocate the ICPState object from under sPAPRCPUCore") moved ICPState objects from the machine to CPU cores. This is an improvement since we no longer allocate ICPState objects that will never be used. But it has the side-effect of breaking migration of older machine types from older QEMU versions. This patch allows spapr to register dummy "icp/server" entries to vmstate. These entries use a dedicated VMStateDescription that can swallow and discard state of an incoming migration stream, and that don't send anything on outgoing migration. As for real ICPState objects, the instance_id is the cpu_index of the corresponding vCPU, which happens to be equal to the generated instance_id of older machine types. The machine can unregister/register these entries when CPUs are dynamically plugged/unplugged. This is only available for pseries-2.9 and older machines, thanks to a compat property. Signed-off-by: Greg Kurz --- v4: - dropped paranoid g_assert()s --- hw/ppc/spapr.c | 86 ++++++++++++++++++++++++++++++++++++++++++++= +++- include/hw/ppc/spapr.h | 2 + 2 files changed, 86 insertions(+), 2 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index b2951d7618d6..1379986c0c7b 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -125,9 +125,50 @@ error: return NULL; } =20 +static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) +{ + return false; +} + +static const VMStateDescription pre_2_10_vmstate_dummy_icp =3D { + .name =3D "icp/server", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D pre_2_10_vmstate_dummy_icp_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UNUSED(4), /* uint32_t xirr */ + VMSTATE_UNUSED(1), /* uint8_t pending_priority */ + VMSTATE_UNUSED(1), /* uint8_t mfrr */ + VMSTATE_END_OF_LIST() + }, +}; + +static void pre_2_10_vmstate_register_dummy_icp(sPAPRMachineState *spapr, = int i) +{ + bool *flag =3D &spapr->pre_2_10_ignore_icp[i]; + + vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, flag); + *flag =3D true; +} + +static void pre_2_10_vmstate_unregister_dummy_icp(sPAPRMachineState *spapr, + int i) +{ + bool *flag =3D &spapr->pre_2_10_ignore_icp[i]; + + vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, flag); + *flag =3D false; +} + +static inline int xics_nr_servers(void) +{ + return DIV_ROUND_UP(max_cpus * kvmppc_smt_threads(), smp_threads); +} + static void xics_system_init(MachineState *machine, int nr_irqs, Error **e= rrp) { sPAPRMachineState *spapr =3D SPAPR_MACHINE(machine); + sPAPRMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(machine); =20 if (kvm_enabled()) { if (machine_kernel_irqchip_allowed(machine) && @@ -149,6 +190,15 @@ static void xics_system_init(MachineState *machine, in= t nr_irqs, Error **errp) return; } } + + if (smc->pre_2_10_has_unused_icps) { + int i; + + spapr->pre_2_10_ignore_icp =3D g_malloc(xics_nr_servers()); + for (i =3D 0; i < xics_nr_servers(); i++) { + pre_2_10_vmstate_register_dummy_icp(spapr, i); + } + } } =20 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, @@ -977,7 +1027,6 @@ static void *spapr_build_fdt(sPAPRMachineState *spapr, void *fdt; sPAPRPHBState *phb; char *buf; - int smt =3D kvmppc_smt_threads(); =20 fdt =3D g_malloc0(FDT_MAX_SIZE); _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); @@ -1017,7 +1066,7 @@ static void *spapr_build_fdt(sPAPRMachineState *spapr, _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); =20 /* /interrupt controller */ - spapr_dt_xics(DIV_ROUND_UP(max_cpus * smt, smp_threads), fdt, PHANDLE_= XICP); + spapr_dt_xics(xics_nr_servers(), fdt, PHANDLE_XICP); =20 ret =3D spapr_populate_memory(spapr, fdt); if (ret < 0) { @@ -2803,9 +2852,24 @@ static void spapr_core_unplug(HotplugHandler *hotplu= g_dev, DeviceState *dev, Error **errp) { MachineState *ms =3D MACHINE(qdev_get_machine()); + sPAPRMachineState *spapr =3D SPAPR_MACHINE(ms); CPUCore *cc =3D CPU_CORE(dev); CPUArchId *core_slot =3D spapr_find_cpu_slot(ms, cc->core_id, NULL); =20 + if (spapr->pre_2_10_ignore_icp) { + sPAPRCPUCore *sc =3D SPAPR_CPU_CORE(OBJECT(dev)); + sPAPRCPUCoreClass *scc =3D SPAPR_CPU_CORE_GET_CLASS(OBJECT(cc)); + const char *typename =3D object_class_get_name(scc->cpu_class); + size_t size =3D object_type_get_instance_size(typename); + int i; + + for (i =3D 0; i < cc->nr_threads; i++) { + CPUState *cs =3D CPU(sc->threads + i * size); + + pre_2_10_vmstate_register_dummy_icp(spapr, cs->cpu_index); + } + } + assert(core_slot); core_slot->cpu =3D NULL; object_unparent(OBJECT(dev)); @@ -2913,6 +2977,21 @@ static void spapr_core_plug(HotplugHandler *hotplug_= dev, DeviceState *dev, } } core_slot->cpu =3D OBJECT(dev); + + if (spapr->pre_2_10_ignore_icp) { + sPAPRCPUCoreClass *scc =3D SPAPR_CPU_CORE_GET_CLASS(OBJECT(cc)); + const char *typename =3D object_class_get_name(scc->cpu_class); + size_t size =3D object_type_get_instance_size(typename); + int i; + + for (i =3D 0; i < cc->nr_threads; i++) { + sPAPRCPUCore *sc =3D SPAPR_CPU_CORE(dev); + void *obj =3D sc->threads + i * size; + + cs =3D CPU(obj); + pre_2_10_vmstate_unregister_dummy_icp(spapr, cs->cpu_index); + } + } } =20 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *= dev, @@ -3362,9 +3441,12 @@ static void spapr_machine_2_9_instance_options(Machi= neState *machine) =20 static void spapr_machine_2_9_class_options(MachineClass *mc) { + sPAPRMachineClass *smc =3D SPAPR_MACHINE_CLASS(mc); + spapr_machine_2_10_class_options(mc); SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9); mc->numa_auto_assign_ram =3D numa_legacy_auto_assign_ram; + smc->pre_2_10_has_unused_icps =3D true; } =20 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index f973b0284596..64382623199d 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -53,6 +53,7 @@ struct sPAPRMachineClass { bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs = */ bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ const char *tcg_default_cpu; /* which (TCG) CPU to simulate by default= */ + bool pre_2_10_has_unused_icps; void (*phb_placement)(sPAPRMachineState *spapr, uint32_t index, uint64_t *buid, hwaddr *pio,=20 hwaddr *mmio32, hwaddr *mmio64, @@ -90,6 +91,7 @@ struct sPAPRMachineState { sPAPROptionVector *ov5_cas; /* negotiated (via CAS) option vectors= */ bool cas_reboot; bool cas_legacy_guest_workaround; + bool *pre_2_10_ignore_icp; =20 Notifier epow_notifier; QTAILQ_HEAD(, sPAPREventLogEntry) pending_events;