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X-Received-From: 2a00:1450:4010:c07::241 Subject: [Qemu-devel] [PATCH v2] target/xtensa: support output to chardev console X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In semihosting mode QEMU allows guest to read and write host file descriptors directly, including descriptors 0..2, a.k.a. stdin, stdout and stderr. Sometimes it's desirable to have semihosting console controlled by -serial option, e.g. to connect it to network. Add semihosting console to xtensa-semi.c, open it in the 'sim' machine in the presence of -serial option and direct stdout and stderr to it when it's present. Signed-off-by: Max Filippov --- Changes v1->v2: - include chardev/char-fe.h instead of sysemu/char.h hw/xtensa/sim.c | 4 +++ target/xtensa/cpu.h | 1 + target/xtensa/xtensa-semi.c | 66 +++++++++++++++++++++++++++++++++++------= ---- 3 files changed, 57 insertions(+), 14 deletions(-) diff --git a/hw/xtensa/sim.c b/hw/xtensa/sim.c index b27e28d..5521e91 100644 --- a/hw/xtensa/sim.c +++ b/hw/xtensa/sim.c @@ -114,6 +114,9 @@ static void xtensa_sim_init(MachineState *machine) xtensa_create_memory_regions(&sysram, "xtensa.sysram"); } =20 + if (serial_hds[0]) { + xtensa_sim_open_console(serial_hds[0]); + } if (kernel_filename) { uint64_t elf_entry; uint64_t elf_lowaddr; @@ -136,6 +139,7 @@ static void xtensa_sim_machine_init(MachineClass *mc) mc->is_default =3D true; mc->init =3D xtensa_sim_init; mc->max_cpus =3D 4; + mc->no_serial =3D 1; } =20 DEFINE_MACHINE("sim", xtensa_sim_machine_init) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index ecca17d..ee29fb1 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -483,6 +483,7 @@ void xtensa_translate_init(void); void xtensa_breakpoint_handler(CPUState *cs); void xtensa_finalize_config(XtensaConfig *config); void xtensa_register_core(XtensaConfigList *node); +void xtensa_sim_open_console(Chardev *chr); void check_interrupts(CPUXtensaState *s); void xtensa_irq_init(CPUXtensaState *env); void *xtensa_get_extint(CPUXtensaState *env, unsigned extint); diff --git a/target/xtensa/xtensa-semi.c b/target/xtensa/xtensa-semi.c index ffcaf8d..32e2bd7 100644 --- a/target/xtensa/xtensa-semi.c +++ b/target/xtensa/xtensa-semi.c @@ -27,9 +27,14 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "chardev/char-fe.h" #include "exec/helper-proto.h" #include "exec/semihost.h" +#include "qapi/error.h" #include "qemu/log.h" +#include "sysemu/sysemu.h" + +static CharBackend *xtensa_sim_console; =20 enum { TARGET_SYS_exit =3D 1, @@ -148,6 +153,15 @@ static uint32_t errno_h2g(int host_errno) } } =20 +void xtensa_sim_open_console(Chardev *chr) +{ + static CharBackend console; + + qemu_chr_fe_init(&console, chr, &error_abort); + qemu_chr_fe_set_handlers(&console, NULL, NULL, NULL, NULL, NULL, true); + xtensa_sim_console =3D &console; +} + void HELPER(simcall)(CPUXtensaState *env) { CPUState *cs =3D CPU(xtensa_env_get_cpu(env)); @@ -181,10 +195,25 @@ void HELPER(simcall)(CPUXtensaState *env) if (buf) { vaddr +=3D io_sz; len -=3D io_sz; - io_done =3D is_write ? - write(fd, buf, io_sz) : - read(fd, buf, io_sz); - regs[3] =3D errno_h2g(errno); + if (fd < 3 && xtensa_sim_console) { + if (is_write && (fd =3D=3D 1 || fd =3D=3D 2)) { + io_done =3D qemu_chr_fe_write_all(xtensa_sim_c= onsole, + buf, io_sz); + regs[3] =3D errno_h2g(errno); + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s fd %d is not supported with = chardev console\n", + is_write ? + "writing to" : "reading from", f= d); + io_done =3D -1; + regs[3] =3D TARGET_EBADF; + } + } else { + io_done =3D is_write ? + write(fd, buf, io_sz) : + read(fd, buf, io_sz); + regs[3] =3D errno_h2g(errno); + } if (io_done =3D=3D -1) { error =3D true; io_done =3D 0; @@ -256,10 +285,6 @@ void HELPER(simcall)(CPUXtensaState *env) uint32_t target_tvv[2]; =20 struct timeval tv =3D {0}; - fd_set fdset; - - FD_ZERO(&fdset); - FD_SET(fd, &fdset); =20 if (target_tv) { cpu_memory_rw_debug(cs, target_tv, @@ -267,12 +292,25 @@ void HELPER(simcall)(CPUXtensaState *env) tv.tv_sec =3D (int32_t)tswap32(target_tvv[0]); tv.tv_usec =3D (int32_t)tswap32(target_tvv[1]); } - regs[2] =3D select(fd + 1, - rq =3D=3D SELECT_ONE_READ ? &fdset : NULL, - rq =3D=3D SELECT_ONE_WRITE ? &fdset : NULL, - rq =3D=3D SELECT_ONE_EXCEPT ? &fdset : NULL, - target_tv ? &tv : NULL); - regs[3] =3D errno_h2g(errno); + if (fd < 3 && xtensa_sim_console) { + if ((fd =3D=3D 1 || fd =3D=3D 2) && rq =3D=3D SELECT_ONE_W= RITE) { + regs[2] =3D 1; + } else { + regs[2] =3D 0; + } + regs[3] =3D 0; + } else { + fd_set fdset; + + FD_ZERO(&fdset); + FD_SET(fd, &fdset); + regs[2] =3D select(fd + 1, + rq =3D=3D SELECT_ONE_READ ? &fdset : NU= LL, + rq =3D=3D SELECT_ONE_WRITE ? &fdset : NU= LL, + rq =3D=3D SELECT_ONE_EXCEPT ? &fdset : NU= LL, + target_tv ? &tv : NULL); + regs[3] =3D errno_h2g(errno); + } } break; =20 --=20 2.1.4