From nobody Mon Feb 9 11:33:20 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1496017248419119.9702630029226; Sun, 28 May 2017 17:20:48 -0700 (PDT) Received: from localhost ([::1]:46218 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dF8QQ-0001GJ-MG for importer@patchew.org; Sun, 28 May 2017 20:20:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59279) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dF8OM-0008V1-7W for qemu-devel@nongnu.org; Sun, 28 May 2017 20:18:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dF8OK-00064O-Na for qemu-devel@nongnu.org; Sun, 28 May 2017 20:18:38 -0400 Received: from mx1.redhat.com ([209.132.183.28]:38578) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dF8OK-00064K-ET; Sun, 28 May 2017 20:18:36 -0400 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 58D72C049D57; Mon, 29 May 2017 00:18:35 +0000 (UTC) Received: from redhat.com (ovpn-120-144.rdu2.redhat.com [10.10.120.144]) by smtp.corp.redhat.com (Postfix) with SMTP id EEEC517985; Mon, 29 May 2017 00:18:31 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 58D72C049D57 Authentication-Results: ext-mx07.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx07.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=mst@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com 58D72C049D57 Date: Mon, 29 May 2017 03:18:31 +0300 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Message-ID: <1496017081-24032-2-git-send-email-mst@redhat.com> References: <1496017081-24032-1-git-send-email-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1496017081-24032-1-git-send-email-mst@redhat.com> X-Mutt-Fcc: =sent X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.31]); Mon, 29 May 2017 00:18:35 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL 01/13] memory: tune last param of iommu_ops.translate() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Eduardo Habkost , Peter Crosthwaite , Jason Wang , Alexander Graf , Peter Xu , Christian Borntraeger , qemu-ppc@nongnu.org, Cornelia Huck , Paolo Bonzini , Richard Henderson , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Peter Xu This patch converts the old "is_write" bool into IOMMUAccessFlags. The difference is that "is_write" can only express either read/write, but sometimes what we really want is "none" here (neither read nor write). Replay is an good example - during replay, we should not check any RW permission bits since thats not an actual IO at all. CC: Paolo Bonzini CC: David Gibson Reviewed-by: David Gibson Acked-by: David Gibson Acked-by: Paolo Bonzini Signed-off-by: Peter Xu Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Reviewed-by: Jason Wang --- include/exec/memory.h | 10 ++++++++-- exec.c | 3 ++- hw/alpha/typhoon.c | 2 +- hw/dma/rc4030.c | 2 +- hw/i386/amd_iommu.c | 4 ++-- hw/i386/intel_iommu.c | 4 ++-- hw/pci-host/apb.c | 2 +- hw/ppc/spapr_iommu.c | 2 +- hw/s390x/s390-pci-bus.c | 2 +- hw/s390x/s390-pci-inst.c | 2 +- memory.c | 3 ++- 11 files changed, 22 insertions(+), 14 deletions(-) diff --git a/include/exec/memory.h b/include/exec/memory.h index 99e0f54..97fd0c2 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -185,8 +185,14 @@ struct MemoryRegionOps { typedef struct MemoryRegionIOMMUOps MemoryRegionIOMMUOps; =20 struct MemoryRegionIOMMUOps { - /* Return a TLB entry that contains a given address. */ - IOMMUTLBEntry (*translate)(MemoryRegion *iommu, hwaddr addr, bool is_w= rite); + /* + * Return a TLB entry that contains a given address. Flag should + * be the access permission of this translation operation. We can + * set flag to IOMMU_NONE to mean that we don't need any + * read/write permission checks, like, when for region replay. + */ + IOMMUTLBEntry (*translate)(MemoryRegion *iommu, hwaddr addr, + IOMMUAccessFlags flag); /* Returns minimum supported page size */ uint64_t (*get_min_page_size)(MemoryRegion *iommu); /* Called when IOMMU Notifier flag changed */ diff --git a/exec.c b/exec.c index ff16f04..b1db12f 100644 --- a/exec.c +++ b/exec.c @@ -486,7 +486,8 @@ static MemoryRegionSection address_space_do_translate(A= ddressSpace *as, break; } =20 - iotlb =3D mr->iommu_ops->translate(mr, addr, is_write); + iotlb =3D mr->iommu_ops->translate(mr, addr, is_write ? + IOMMU_WO : IOMMU_RO); addr =3D ((iotlb.translated_addr & ~iotlb.addr_mask) | (addr & iotlb.addr_mask)); *plen =3D MIN(*plen, (addr | iotlb.addr_mask) - addr + 1); diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c index f50f5cf..c1cf780 100644 --- a/hw/alpha/typhoon.c +++ b/hw/alpha/typhoon.c @@ -664,7 +664,7 @@ static bool window_translate(TyphoonWindow *win, hwaddr= addr, /* TODO: A translation failure here ought to set PCI error codes on the Pchip and generate a machine check interrupt. */ static IOMMUTLBEntry typhoon_translate_iommu(MemoryRegion *iommu, hwaddr a= ddr, - bool is_write) + IOMMUAccessFlags flag) { TyphoonPchip *pchip =3D container_of(iommu, TyphoonPchip, iommu); IOMMUTLBEntry ret; diff --git a/hw/dma/rc4030.c b/hw/dma/rc4030.c index 0080141..edf9432 100644 --- a/hw/dma/rc4030.c +++ b/hw/dma/rc4030.c @@ -489,7 +489,7 @@ static const MemoryRegionOps jazzio_ops =3D { }; =20 static IOMMUTLBEntry rc4030_dma_translate(MemoryRegion *iommu, hwaddr addr, - bool is_write) + IOMMUAccessFlags flag) { rc4030State *s =3D container_of(iommu, rc4030State, dma_mr); IOMMUTLBEntry ret =3D { diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 329058d..7b6d4ea 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -988,7 +988,7 @@ static inline bool amdvi_is_interrupt_addr(hwaddr addr) } =20 static IOMMUTLBEntry amdvi_translate(MemoryRegion *iommu, hwaddr addr, - bool is_write) + IOMMUAccessFlags flag) { AMDVIAddressSpace *as =3D container_of(iommu, AMDVIAddressSpace, iommu= ); AMDVIState *s =3D as->iommu_state; @@ -1017,7 +1017,7 @@ static IOMMUTLBEntry amdvi_translate(MemoryRegion *io= mmu, hwaddr addr, return ret; } =20 - amdvi_do_translate(as, addr, is_write, &ret); + amdvi_do_translate(as, addr, flag & IOMMU_WO, &ret); trace_amdvi_translation_result(as->bus_num, PCI_SLOT(as->devfn), PCI_FUNC(as->devfn), addr, ret.translated_addr); return ret; diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 9ba2162..4a51df8 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2221,7 +2221,7 @@ static void vtd_mem_write(void *opaque, hwaddr addr, } =20 static IOMMUTLBEntry vtd_iommu_translate(MemoryRegion *iommu, hwaddr addr, - bool is_write) + IOMMUAccessFlags flag) { VTDAddressSpace *vtd_as =3D container_of(iommu, VTDAddressSpace, iommu= ); IntelIOMMUState *s =3D vtd_as->iommu_state; @@ -2243,7 +2243,7 @@ static IOMMUTLBEntry vtd_iommu_translate(MemoryRegion= *iommu, hwaddr addr, } =20 vtd_do_iommu_translate(vtd_as, vtd_as->bus, vtd_as->devfn, addr, - is_write, &ret); + flag & IOMMU_WO, &ret); VTD_DPRINTF(MMU, "bus %"PRIu8 " slot %"PRIu8 " func %"PRIu8 " devfn %"PRIu8 " iova 0x%"PRIx64 " hpa 0x%"PRIx64, pci_bus_num(vtd_as->bu= s), diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c index edc88f4..2a80f68 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/apb.c @@ -209,7 +209,7 @@ static AddressSpace *pbm_pci_dma_iommu(PCIBus *bus, voi= d *opaque, int devfn) =20 /* Called from RCU critical section */ static IOMMUTLBEntry pbm_translate_iommu(MemoryRegion *iommu, hwaddr addr, - bool is_write) + IOMMUAccessFlags flag) { IOMMUState *is =3D container_of(iommu, IOMMUState, iommu); hwaddr baseaddr, offset; diff --git a/hw/ppc/spapr_iommu.c b/hw/ppc/spapr_iommu.c index 29c80bb..0341bc0 100644 --- a/hw/ppc/spapr_iommu.c +++ b/hw/ppc/spapr_iommu.c @@ -111,7 +111,7 @@ static void spapr_tce_free_table(uint64_t *table, int f= d, uint32_t nb_table) =20 /* Called from RCU critical section */ static IOMMUTLBEntry spapr_tce_translate_iommu(MemoryRegion *iommu, hwaddr= addr, - bool is_write) + IOMMUAccessFlags flag) { sPAPRTCETable *tcet =3D container_of(iommu, sPAPRTCETable, iommu); uint64_t tce; diff --git a/hw/s390x/s390-pci-bus.c b/hw/s390x/s390-pci-bus.c index 66a6fbe..5651483 100644 --- a/hw/s390x/s390-pci-bus.c +++ b/hw/s390x/s390-pci-bus.c @@ -357,7 +357,7 @@ out: } =20 static IOMMUTLBEntry s390_translate_iommu(MemoryRegion *mr, hwaddr addr, - bool is_write) + IOMMUAccessFlags flag) { uint64_t pte; uint32_t flags; diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c index 314a9cb..8bc7c98 100644 --- a/hw/s390x/s390-pci-inst.c +++ b/hw/s390x/s390-pci-inst.c @@ -624,7 +624,7 @@ int rpcit_service_call(S390CPU *cpu, uint8_t r1, uint8_= t r2) =20 mr =3D &iommu->iommu_mr; while (start < end) { - entry =3D mr->iommu_ops->translate(mr, start, 0); + entry =3D mr->iommu_ops->translate(mr, start, IOMMU_NONE); =20 if (!entry.translated_addr) { pbdev->state =3D ZPCI_FS_ERROR; diff --git a/memory.c b/memory.c index b727f5e..3f0aae8 100644 --- a/memory.c +++ b/memory.c @@ -1625,6 +1625,7 @@ void memory_region_iommu_replay(MemoryRegion *mr, IOM= MUNotifier *n, { hwaddr addr, granularity; IOMMUTLBEntry iotlb; + IOMMUAccessFlags flag =3D is_write ? IOMMU_WO : IOMMU_RO; =20 /* If the IOMMU has its own replay callback, override */ if (mr->iommu_ops->replay) { @@ -1635,7 +1636,7 @@ void memory_region_iommu_replay(MemoryRegion *mr, IOM= MUNotifier *n, granularity =3D memory_region_iommu_get_min_page_size(mr); =20 for (addr =3D 0; addr < memory_region_size(mr); addr +=3D granularity)= { - iotlb =3D mr->iommu_ops->translate(mr, addr, is_write); + iotlb =3D mr->iommu_ops->translate(mr, addr, flag); if (iotlb.perm !=3D IOMMU_NONE) { n->notify(n, &iotlb); } --=20 MST