From nobody Mon Feb 9 10:58:16 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 149517081582356.724581027929844; Thu, 18 May 2017 22:13:35 -0700 (PDT) Received: from localhost ([::1]:56584 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dBaEI-00037m-H7 for importer@patchew.org; Fri, 19 May 2017 01:13:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52397) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dBaBR-00012A-4L for qemu-devel@nongnu.org; Fri, 19 May 2017 01:10:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dBaBP-0005iR-Lm for qemu-devel@nongnu.org; Fri, 19 May 2017 01:10:37 -0400 Received: from mga04.intel.com ([192.55.52.120]:39329) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dBaBP-0005ha-D0 for qemu-devel@nongnu.org; Fri, 19 May 2017 01:10:35 -0400 Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 May 2017 22:10:35 -0700 Received: from yangzhon-virtual.bj.intel.com ([10.238.145.52]) by orsmga002.jf.intel.com with ESMTP; 18 May 2017 22:10:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,362,1491289200"; d="scan'208";a="89089335" From: Yang Zhong To: eblake@redhat.com Date: Fri, 19 May 2017 13:09:42 +0800 Message-Id: <1495170583-30905-4-git-send-email-yang.zhong@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1495170583-30905-1-git-send-email-yang.zhong@intel.com> References: <1495170583-30905-1-git-send-email-yang.zhong@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.120 Subject: [Qemu-devel] [PATCH v0 3/4] move cpu-exec.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yang Zhong , pbonzini@redhat.com, anthony.xu@intel.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" move cpu-exec.c to ./accel/tcg/ Signed-off-by: Yang Zhong --- Makefile.objs | 1 + Makefile.target | 4 ++-- accel/tcg/Makefile.objs | 1 + cpu-exec.c =3D> accel/tcg/cpu-exec.c | 5 +++-- accel/tcg/trace-events | 7 +++++++ trace-events | 5 ----- 6 files changed, 14 insertions(+), 9 deletions(-) rename cpu-exec.c =3D> accel/tcg/cpu-exec.c (99%) create mode 100644 accel/tcg/trace-events diff --git a/Makefile.objs b/Makefile.objs index 2a8de77..6a33874 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -163,6 +163,7 @@ trace-events-subdirs +=3D target/ppc trace-events-subdirs +=3D qom trace-events-subdirs +=3D linux-user trace-events-subdirs +=3D qapi +trace-events-subdirs +=3D accel/tcg =20 trace-events-files =3D $(SRC_PATH)/trace-events $(trace-events-subdirs:%= =3D$(SRC_PATH)/%/trace-events) =20 diff --git a/Makefile.target b/Makefile.target index 3e19fe9..709d07a 100644 --- a/Makefile.target +++ b/Makefile.target @@ -88,7 +88,8 @@ all: $(PROGS) stap =20 ######################################################### # cpu emulator library -obj-y =3D exec.o translate-all.o cpu-exec.o +obj-y =3D exec.o translate-all.o +obj-y +=3D accel/ obj-y +=3D translate-common.o obj-y +=3D cpu-exec-common.o obj-y +=3D tcg/tcg.o tcg/tcg-op.o tcg/optimize.o @@ -143,7 +144,6 @@ obj-y +=3D arch_init.o cpus.o monitor.o gdbstub.o ballo= on.o ioport.o numa.o obj-y +=3D qtest.o bootdevice.o obj-y +=3D hw/ obj-$(CONFIG_KVM) +=3D kvm-all.o -obj-y +=3D accel/ obj-y +=3D memory.o obj-y +=3D memory_mapping.o obj-y +=3D dump.o diff --git a/accel/tcg/Makefile.objs b/accel/tcg/Makefile.objs index 487570f..6b75a31 100644 --- a/accel/tcg/Makefile.objs +++ b/accel/tcg/Makefile.objs @@ -1,2 +1,3 @@ obj-$(CONFIG_SOFTMMU) +=3D tcg-all.o obj-$(CONFIG_SOFTMMU) +=3D cputlb.o +obj-y +=3D cpu-exec.o diff --git a/cpu-exec.c b/accel/tcg/cpu-exec.c similarity index 99% rename from cpu-exec.c rename to accel/tcg/cpu-exec.c index 63a56d0..2019160 100644 --- a/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -18,7 +18,7 @@ */ #include "qemu/osdep.h" #include "cpu.h" -#include "trace-root.h" +#include "trace.h" #include "disas/disas.h" #include "exec/exec-all.h" #include "tcg.h" @@ -200,8 +200,9 @@ static void cpu_exec_nocache(CPUState *cpu, int max_cyc= les, =20 /* Should never happen. We only end up here when an existing TB is too long. */ - if (max_cycles > CF_COUNT_MASK) + if (max_cycles > CF_COUNT_MASK) { max_cycles =3D CF_COUNT_MASK; + } =20 tb_lock(); tb =3D tb_gen_code(cpu, orig_tb->pc, orig_tb->cs_base, orig_tb->flags, diff --git a/accel/tcg/trace-events b/accel/tcg/trace-events new file mode 100644 index 0000000..f2db388 --- /dev/null +++ b/accel/tcg/trace-events @@ -0,0 +1,7 @@ +# Trace events for debugging and performance instrumentation + +# TCG related tracing (mostly disabled by default) +# cpu-exec.c +disable exec_tb(void *tb, uintptr_t pc) "tb:%p pc=3D0x%"PRIxPTR +disable exec_tb_nocache(void *tb, uintptr_t pc) "tb:%p pc=3D0x%"PRIxPTR +disable exec_tb_exit(void *last_tb, unsigned int flags) "tb:%p flags=3D%x" diff --git a/trace-events b/trace-events index e582d63..153942d 100644 --- a/trace-events +++ b/trace-events @@ -73,11 +73,6 @@ kvm_irqchip_add_msi_route(int virq) "Adding MSI route vi= rq=3D%d" kvm_irqchip_update_msi_route(int virq) "Updating MSI route virq=3D%d" =20 # TCG related tracing (mostly disabled by default) -# cpu-exec.c -disable exec_tb(void *tb, uintptr_t pc) "tb:%p pc=3D0x%"PRIxPTR -disable exec_tb_nocache(void *tb, uintptr_t pc) "tb:%p pc=3D0x%"PRIxPTR -disable exec_tb_exit(void *last_tb, unsigned int flags) "tb:%p flags=3D%x" - # translate-all.c translate_block(void *tb, uintptr_t pc, uint8_t *tb_code) "tb:%p, pc:0x%"P= RIxPTR", tb_code:%p" =20 --=20 1.9.1