From nobody Fri May 3 12:50:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1495164133140174.3171041021958; Thu, 18 May 2017 20:22:13 -0700 (PDT) Received: from localhost ([::1]:56358 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dBYUS-0007it-IK for importer@patchew.org; Thu, 18 May 2017 23:22:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35280) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dBYSf-0006ee-H5 for qemu-devel@nongnu.org; Thu, 18 May 2017 23:20:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dBYSd-0005Na-Fm for qemu-devel@nongnu.org; Thu, 18 May 2017 23:20:17 -0400 Received: from mx1.redhat.com ([209.132.183.28]:58944) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dBYSd-0005N4-6C for qemu-devel@nongnu.org; Thu, 18 May 2017 23:20:15 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 162CC3DE3E; Fri, 19 May 2017 03:20:14 +0000 (UTC) Received: from pxdev.xzpeter.org.com (ovpn-12-101.pek2.redhat.com [10.72.12.101]) by smtp.corp.redhat.com (Postfix) with ESMTP id 9C28D784C2; Fri, 19 May 2017 03:20:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 162CC3DE3E Authentication-Results: ext-mx05.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx05.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=peterx@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com 162CC3DE3E From: Peter Xu To: qemu-devel@nongnu.org Date: Fri, 19 May 2017 11:19:40 +0800 Message-Id: <1495163989-9994-2-git-send-email-peterx@redhat.com> In-Reply-To: <1495163989-9994-1-git-send-email-peterx@redhat.com> References: <1495163989-9994-1-git-send-email-peterx@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.29]); Fri, 19 May 2017 03:20:14 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v4 01/10] memory: tune last param of iommu_ops.translate() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lan Tianyu , yi.l.liu@intel.com, "Michael S . Tsirkin" , Jason Wang , peterx@redhat.com, Marcel Apfelbaum , Paolo Bonzini , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch converts the old "is_write" bool into IOMMUAccessFlags. The difference is that "is_write" can only express either read/write, but sometimes what we really want is "none" here (neither read nor write). Replay is an good example - during replay, we should not check any RW permission bits since thats not an actual IO at all. CC: Paolo Bonzini CC: David Gibson Reviewed-by: David Gibson Acked-by: David Gibson Acked-by: Paolo Bonzini Signed-off-by: Peter Xu Reviewed-by: Jason Wang --- exec.c | 3 ++- hw/alpha/typhoon.c | 2 +- hw/dma/rc4030.c | 2 +- hw/i386/amd_iommu.c | 4 ++-- hw/i386/intel_iommu.c | 4 ++-- hw/pci-host/apb.c | 2 +- hw/ppc/spapr_iommu.c | 2 +- hw/s390x/s390-pci-bus.c | 2 +- hw/s390x/s390-pci-inst.c | 2 +- include/exec/memory.h | 10 ++++++++-- memory.c | 3 ++- 11 files changed, 22 insertions(+), 14 deletions(-) diff --git a/exec.c b/exec.c index 96e3ac9..0d479b2 100644 --- a/exec.c +++ b/exec.c @@ -485,7 +485,8 @@ static MemoryRegionSection address_space_do_translate(A= ddressSpace *as, break; } =20 - iotlb =3D mr->iommu_ops->translate(mr, addr, is_write); + iotlb =3D mr->iommu_ops->translate(mr, addr, is_write ? + IOMMU_WO : IOMMU_RO); addr =3D ((iotlb.translated_addr & ~iotlb.addr_mask) | (addr & iotlb.addr_mask)); *plen =3D MIN(*plen, (addr | iotlb.addr_mask) - addr + 1); diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c index f50f5cf..c1cf780 100644 --- a/hw/alpha/typhoon.c +++ b/hw/alpha/typhoon.c @@ -664,7 +664,7 @@ static bool window_translate(TyphoonWindow *win, hwaddr= addr, /* TODO: A translation failure here ought to set PCI error codes on the Pchip and generate a machine check interrupt. */ static IOMMUTLBEntry typhoon_translate_iommu(MemoryRegion *iommu, hwaddr a= ddr, - bool is_write) + IOMMUAccessFlags flag) { TyphoonPchip *pchip =3D container_of(iommu, TyphoonPchip, iommu); IOMMUTLBEntry ret; diff --git a/hw/dma/rc4030.c b/hw/dma/rc4030.c index 0080141..edf9432 100644 --- a/hw/dma/rc4030.c +++ b/hw/dma/rc4030.c @@ -489,7 +489,7 @@ static const MemoryRegionOps jazzio_ops =3D { }; =20 static IOMMUTLBEntry rc4030_dma_translate(MemoryRegion *iommu, hwaddr addr, - bool is_write) + IOMMUAccessFlags flag) { rc4030State *s =3D container_of(iommu, rc4030State, dma_mr); IOMMUTLBEntry ret =3D { diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 329058d..7b6d4ea 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -988,7 +988,7 @@ static inline bool amdvi_is_interrupt_addr(hwaddr addr) } =20 static IOMMUTLBEntry amdvi_translate(MemoryRegion *iommu, hwaddr addr, - bool is_write) + IOMMUAccessFlags flag) { AMDVIAddressSpace *as =3D container_of(iommu, AMDVIAddressSpace, iommu= ); AMDVIState *s =3D as->iommu_state; @@ -1017,7 +1017,7 @@ static IOMMUTLBEntry amdvi_translate(MemoryRegion *io= mmu, hwaddr addr, return ret; } =20 - amdvi_do_translate(as, addr, is_write, &ret); + amdvi_do_translate(as, addr, flag & IOMMU_WO, &ret); trace_amdvi_translation_result(as->bus_num, PCI_SLOT(as->devfn), PCI_FUNC(as->devfn), addr, ret.translated_addr); return ret; diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 9ba2162..4a51df8 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2221,7 +2221,7 @@ static void vtd_mem_write(void *opaque, hwaddr addr, } =20 static IOMMUTLBEntry vtd_iommu_translate(MemoryRegion *iommu, hwaddr addr, - bool is_write) + IOMMUAccessFlags flag) { VTDAddressSpace *vtd_as =3D container_of(iommu, VTDAddressSpace, iommu= ); IntelIOMMUState *s =3D vtd_as->iommu_state; @@ -2243,7 +2243,7 @@ static IOMMUTLBEntry vtd_iommu_translate(MemoryRegion= *iommu, hwaddr addr, } =20 vtd_do_iommu_translate(vtd_as, vtd_as->bus, vtd_as->devfn, addr, - is_write, &ret); + flag & IOMMU_WO, &ret); VTD_DPRINTF(MMU, "bus %"PRIu8 " slot %"PRIu8 " func %"PRIu8 " devfn %"PRIu8 " iova 0x%"PRIx64 " hpa 0x%"PRIx64, pci_bus_num(vtd_as->bu= s), diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c index edc88f4..2a80f68 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/apb.c @@ -209,7 +209,7 @@ static AddressSpace *pbm_pci_dma_iommu(PCIBus *bus, voi= d *opaque, int devfn) =20 /* Called from RCU critical section */ static IOMMUTLBEntry pbm_translate_iommu(MemoryRegion *iommu, hwaddr addr, - bool is_write) + IOMMUAccessFlags flag) { IOMMUState *is =3D container_of(iommu, IOMMUState, iommu); hwaddr baseaddr, offset; diff --git a/hw/ppc/spapr_iommu.c b/hw/ppc/spapr_iommu.c index 29c80bb..0341bc0 100644 --- a/hw/ppc/spapr_iommu.c +++ b/hw/ppc/spapr_iommu.c @@ -111,7 +111,7 @@ static void spapr_tce_free_table(uint64_t *table, int f= d, uint32_t nb_table) =20 /* Called from RCU critical section */ static IOMMUTLBEntry spapr_tce_translate_iommu(MemoryRegion *iommu, hwaddr= addr, - bool is_write) + IOMMUAccessFlags flag) { sPAPRTCETable *tcet =3D container_of(iommu, sPAPRTCETable, iommu); uint64_t tce; diff --git a/hw/s390x/s390-pci-bus.c b/hw/s390x/s390-pci-bus.c index 66a6fbe..5651483 100644 --- a/hw/s390x/s390-pci-bus.c +++ b/hw/s390x/s390-pci-bus.c @@ -357,7 +357,7 @@ out: } =20 static IOMMUTLBEntry s390_translate_iommu(MemoryRegion *mr, hwaddr addr, - bool is_write) + IOMMUAccessFlags flag) { uint64_t pte; uint32_t flags; diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c index 314a9cb..8bc7c98 100644 --- a/hw/s390x/s390-pci-inst.c +++ b/hw/s390x/s390-pci-inst.c @@ -624,7 +624,7 @@ int rpcit_service_call(S390CPU *cpu, uint8_t r1, uint8_= t r2) =20 mr =3D &iommu->iommu_mr; while (start < end) { - entry =3D mr->iommu_ops->translate(mr, start, 0); + entry =3D mr->iommu_ops->translate(mr, start, IOMMU_NONE); =20 if (!entry.translated_addr) { pbdev->state =3D ZPCI_FS_ERROR; diff --git a/include/exec/memory.h b/include/exec/memory.h index 99e0f54..97fd0c2 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -185,8 +185,14 @@ struct MemoryRegionOps { typedef struct MemoryRegionIOMMUOps MemoryRegionIOMMUOps; =20 struct MemoryRegionIOMMUOps { - /* Return a TLB entry that contains a given address. */ - IOMMUTLBEntry (*translate)(MemoryRegion *iommu, hwaddr addr, bool is_w= rite); + /* + * Return a TLB entry that contains a given address. Flag should + * be the access permission of this translation operation. We can + * set flag to IOMMU_NONE to mean that we don't need any + * read/write permission checks, like, when for region replay. + */ + IOMMUTLBEntry (*translate)(MemoryRegion *iommu, hwaddr addr, + IOMMUAccessFlags flag); /* Returns minimum supported page size */ uint64_t (*get_min_page_size)(MemoryRegion *iommu); /* Called when IOMMU Notifier flag changed */ diff --git a/memory.c b/memory.c index b727f5e..3f0aae8 100644 --- a/memory.c +++ b/memory.c @@ -1625,6 +1625,7 @@ void memory_region_iommu_replay(MemoryRegion *mr, IOM= MUNotifier *n, { hwaddr addr, granularity; IOMMUTLBEntry iotlb; + IOMMUAccessFlags flag =3D is_write ? IOMMU_WO : IOMMU_RO; =20 /* If the IOMMU has its own replay callback, override */ if (mr->iommu_ops->replay) { @@ -1635,7 +1636,7 @@ void memory_region_iommu_replay(MemoryRegion *mr, IOM= MUNotifier *n, granularity =3D memory_region_iommu_get_min_page_size(mr); =20 for (addr =3D 0; addr < memory_region_size(mr); addr +=3D granularity)= { - iotlb =3D mr->iommu_ops->translate(mr, addr, is_write); + iotlb =3D mr->iommu_ops->translate(mr, addr, flag); if (iotlb.perm !=3D IOMMU_NONE) { n->notify(n, &iotlb); } --=20 2.7.4 From nobody Fri May 3 12:50:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1495164333061533.7112757015618; Thu, 18 May 2017 20:25:33 -0700 (PDT) Received: from localhost ([::1]:56381 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dBYXj-0002OV-Os for importer@patchew.org; Thu, 18 May 2017 23:25:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35357) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dBYSx-0006s5-Cm for qemu-devel@nongnu.org; Thu, 18 May 2017 23:20:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dBYSn-0005Wl-4l for qemu-devel@nongnu.org; Thu, 18 May 2017 23:20:34 -0400 Received: from mx1.redhat.com ([209.132.183.28]:32820) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dBYSm-0005WZ-Rr for qemu-devel@nongnu.org; Thu, 18 May 2017 23:20:25 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id D678080C0C; Fri, 19 May 2017 03:20:23 +0000 (UTC) Received: from pxdev.xzpeter.org.com (ovpn-12-101.pek2.redhat.com [10.72.12.101]) by smtp.corp.redhat.com (Postfix) with ESMTP id B4971784C2; Fri, 19 May 2017 03:20:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com D678080C0C Authentication-Results: ext-mx02.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx02.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=peterx@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com D678080C0C From: Peter Xu To: qemu-devel@nongnu.org Date: Fri, 19 May 2017 11:19:41 +0800 Message-Id: <1495163989-9994-3-git-send-email-peterx@redhat.com> In-Reply-To: <1495163989-9994-1-git-send-email-peterx@redhat.com> References: <1495163989-9994-1-git-send-email-peterx@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.26]); Fri, 19 May 2017 03:20:24 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v4 02/10] memory: remove the last param in memory_region_iommu_replay() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lan Tianyu , yi.l.liu@intel.com, "Michael S . Tsirkin" , Jason Wang , peterx@redhat.com, Marcel Apfelbaum , Paolo Bonzini , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We were always passing in that one as "false" to assume that's an read operation, and we also assume that IOMMU translation would always have that read permission. A better permission would be IOMMU_NONE since the replay is after all not a real read operation, but just a page table rebuilding process. CC: David Gibson CC: Paolo Bonzini Reviewed-by: David Gibson Acked-by: Paolo Bonzini Signed-off-by: Peter Xu Reviewed-by: Jason Wang --- hw/vfio/common.c | 2 +- include/exec/memory.h | 5 +---- memory.c | 8 +++----- 3 files changed, 5 insertions(+), 10 deletions(-) diff --git a/hw/vfio/common.c b/hw/vfio/common.c index a8f12ee..b9abe77 100644 --- a/hw/vfio/common.c +++ b/hw/vfio/common.c @@ -502,7 +502,7 @@ static void vfio_listener_region_add(MemoryListener *li= stener, QLIST_INSERT_HEAD(&container->giommu_list, giommu, giommu_next); =20 memory_region_register_iommu_notifier(giommu->iommu, &giommu->n); - memory_region_iommu_replay(giommu->iommu, &giommu->n, false); + memory_region_iommu_replay(giommu->iommu, &giommu->n); =20 return; } diff --git a/include/exec/memory.h b/include/exec/memory.h index 97fd0c2..bfdc685 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -731,11 +731,8 @@ void memory_region_register_iommu_notifier(MemoryRegio= n *mr, * * @mr: the memory region to observe * @n: the notifier to which to replay iommu mappings - * @is_write: Whether to treat the replay as a translate "write" - * through the iommu */ -void memory_region_iommu_replay(MemoryRegion *mr, IOMMUNotifier *n, - bool is_write); +void memory_region_iommu_replay(MemoryRegion *mr, IOMMUNotifier *n); =20 /** * memory_region_iommu_replay_all: replay existing IOMMU translations diff --git a/memory.c b/memory.c index 3f0aae8..0ddc4cc 100644 --- a/memory.c +++ b/memory.c @@ -1620,12 +1620,10 @@ uint64_t memory_region_iommu_get_min_page_size(Memo= ryRegion *mr) return TARGET_PAGE_SIZE; } =20 -void memory_region_iommu_replay(MemoryRegion *mr, IOMMUNotifier *n, - bool is_write) +void memory_region_iommu_replay(MemoryRegion *mr, IOMMUNotifier *n) { hwaddr addr, granularity; IOMMUTLBEntry iotlb; - IOMMUAccessFlags flag =3D is_write ? IOMMU_WO : IOMMU_RO; =20 /* If the IOMMU has its own replay callback, override */ if (mr->iommu_ops->replay) { @@ -1636,7 +1634,7 @@ void memory_region_iommu_replay(MemoryRegion *mr, IOM= MUNotifier *n, granularity =3D memory_region_iommu_get_min_page_size(mr); =20 for (addr =3D 0; addr < memory_region_size(mr); addr +=3D granularity)= { - iotlb =3D mr->iommu_ops->translate(mr, addr, flag); + iotlb =3D mr->iommu_ops->translate(mr, addr, IOMMU_NONE); if (iotlb.perm !=3D IOMMU_NONE) { n->notify(n, &iotlb); } @@ -1654,7 +1652,7 @@ void memory_region_iommu_replay_all(MemoryRegion *mr) IOMMUNotifier *notifier; =20 IOMMU_NOTIFIER_FOREACH(notifier, mr) { - memory_region_iommu_replay(mr, notifier, false); + memory_region_iommu_replay(mr, notifier); } } =20 --=20 2.7.4 From nobody Fri May 3 12:50:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1495164271282761.5617004673107; Thu, 18 May 2017 20:24:31 -0700 (PDT) Received: from localhost ([::1]:56372 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dBYWh-0001X5-VQ for importer@patchew.org; Thu, 18 May 2017 23:24:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35374) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dBYT0-0006uL-Ub for qemu-devel@nongnu.org; Thu, 18 May 2017 23:20:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dBYSr-0005XL-7m for qemu-devel@nongnu.org; Thu, 18 May 2017 23:20:38 -0400 Received: from mx1.redhat.com ([209.132.183.28]:36354) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dBYSq-0005X5-VN for qemu-devel@nongnu.org; Thu, 18 May 2017 23:20:29 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id D606CC04B924; Fri, 19 May 2017 03:20:27 +0000 (UTC) Received: from pxdev.xzpeter.org.com (ovpn-12-101.pek2.redhat.com [10.72.12.101]) by smtp.corp.redhat.com (Postfix) with ESMTP id 6D40D7E2FC; Fri, 19 May 2017 03:20:24 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com D606CC04B924 Authentication-Results: ext-mx07.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx07.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=peterx@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com D606CC04B924 From: Peter Xu To: qemu-devel@nongnu.org Date: Fri, 19 May 2017 11:19:42 +0800 Message-Id: <1495163989-9994-4-git-send-email-peterx@redhat.com> In-Reply-To: <1495163989-9994-1-git-send-email-peterx@redhat.com> References: <1495163989-9994-1-git-send-email-peterx@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.31]); Fri, 19 May 2017 03:20:28 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v4 03/10] x86-iommu: use DeviceClass properties X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lan Tianyu , yi.l.liu@intel.com, "Michael S . Tsirkin" , Jason Wang , peterx@redhat.com, Marcel Apfelbaum , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" No reason to keep tens of lines if we can do it actually far shorter. Signed-off-by: Peter Xu Reviewed-by: Jason Wang --- hw/i386/x86-iommu.c | 47 +++++++---------------------------------------- 1 file changed, 7 insertions(+), 40 deletions(-) diff --git a/hw/i386/x86-iommu.c b/hw/i386/x86-iommu.c index 23dcd3f..02b8825 100644 --- a/hw/i386/x86-iommu.c +++ b/hw/i386/x86-iommu.c @@ -88,55 +88,22 @@ static void x86_iommu_realize(DeviceState *dev, Error *= *errp) x86_iommu_set_default(X86_IOMMU_DEVICE(dev)); } =20 +static Property x86_iommu_properties[] =3D { + DEFINE_PROP_BOOL("intremap", X86IOMMUState, intr_supported, false), + DEFINE_PROP_BOOL("device-iotlb", X86IOMMUState, dt_supported, false), + DEFINE_PROP_END_OF_LIST(), +}; + static void x86_iommu_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); dc->realize =3D x86_iommu_realize; -} - -static bool x86_iommu_intremap_prop_get(Object *o, Error **errp) -{ - X86IOMMUState *s =3D X86_IOMMU_DEVICE(o); - return s->intr_supported; -} - -static void x86_iommu_intremap_prop_set(Object *o, bool value, Error **err= p) -{ - X86IOMMUState *s =3D X86_IOMMU_DEVICE(o); - s->intr_supported =3D value; -} - -static bool x86_iommu_device_iotlb_prop_get(Object *o, Error **errp) -{ - X86IOMMUState *s =3D X86_IOMMU_DEVICE(o); - return s->dt_supported; -} - -static void x86_iommu_device_iotlb_prop_set(Object *o, bool value, Error *= *errp) -{ - X86IOMMUState *s =3D X86_IOMMU_DEVICE(o); - s->dt_supported =3D value; -} - -static void x86_iommu_instance_init(Object *o) -{ - X86IOMMUState *s =3D X86_IOMMU_DEVICE(o); - - /* By default, do not support IR */ - s->intr_supported =3D false; - object_property_add_bool(o, "intremap", x86_iommu_intremap_prop_get, - x86_iommu_intremap_prop_set, NULL); - s->dt_supported =3D false; - object_property_add_bool(o, "device-iotlb", - x86_iommu_device_iotlb_prop_get, - x86_iommu_device_iotlb_prop_set, - NULL); + dc->props =3D x86_iommu_properties; } =20 static const TypeInfo x86_iommu_info =3D { .name =3D TYPE_X86_IOMMU_DEVICE, .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_init =3D x86_iommu_instance_init, .instance_size =3D sizeof(X86IOMMUState), .class_init =3D x86_iommu_class_init, .class_size =3D sizeof(X86IOMMUClass), --=20 2.7.4 From nobody Fri May 3 12:50:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1495164208808750.4778435854914; Thu, 18 May 2017 20:23:28 -0700 (PDT) Received: from localhost ([::1]:56366 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dBYVj-0000SE-Bz for importer@patchew.org; Thu, 18 May 2017 23:23:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35390) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dBYT5-0006yh-CL for qemu-devel@nongnu.org; Thu, 18 May 2017 23:20:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dBYSv-0005YL-SS for qemu-devel@nongnu.org; Thu, 18 May 2017 23:20:43 -0400 Received: from mx1.redhat.com ([209.132.183.28]:57628) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dBYSv-0005Xw-Ic for qemu-devel@nongnu.org; Thu, 18 May 2017 23:20:33 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 92BAC3D941; Fri, 19 May 2017 03:20:32 +0000 (UTC) Received: from pxdev.xzpeter.org.com (ovpn-12-101.pek2.redhat.com [10.72.12.101]) by smtp.corp.redhat.com (Postfix) with ESMTP id 6BBAF784C2; Fri, 19 May 2017 03:20:28 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 92BAC3D941 Authentication-Results: ext-mx06.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx06.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=peterx@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com 92BAC3D941 From: Peter Xu To: qemu-devel@nongnu.org Date: Fri, 19 May 2017 11:19:43 +0800 Message-Id: <1495163989-9994-5-git-send-email-peterx@redhat.com> In-Reply-To: <1495163989-9994-1-git-send-email-peterx@redhat.com> References: <1495163989-9994-1-git-send-email-peterx@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.30]); Fri, 19 May 2017 03:20:32 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v4 04/10] intel_iommu: renaming context entry helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lan Tianyu , yi.l.liu@intel.com, "Michael S . Tsirkin" , Jason Wang , peterx@redhat.com, Marcel Apfelbaum , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The old names are too long and less ordered. Let's start to use vtd_ce_*() as a pattern. Signed-off-by: Peter Xu Reviewed-by: Jason Wang --- hw/i386/intel_iommu.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 4a51df8..f06055f 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -512,7 +512,7 @@ static int vtd_get_root_entry(IntelIOMMUState *s, uint8= _t index, return 0; } =20 -static inline bool vtd_context_entry_present(VTDContextEntry *context) +static inline bool vtd_ce_present(VTDContextEntry *context) { return context->lo & VTD_CONTEXT_ENTRY_P; } @@ -533,7 +533,7 @@ static int vtd_get_context_entry_from_root(VTDRootEntry= *root, uint8_t index, return 0; } =20 -static inline dma_addr_t vtd_get_slpt_base_from_context(VTDContextEntry *c= e) +static inline dma_addr_t vtd_ce_get_slpt_base(VTDContextEntry *ce) { return ce->lo & VTD_CONTEXT_ENTRY_SLPTPTR; } @@ -585,19 +585,19 @@ static inline bool vtd_is_level_supported(IntelIOMMUS= tate *s, uint32_t level) /* Get the page-table level that hardware should use for the second-level * page-table walk from the Address Width field of context-entry. */ -static inline uint32_t vtd_get_level_from_context_entry(VTDContextEntry *c= e) +static inline uint32_t vtd_ce_get_level(VTDContextEntry *ce) { return 2 + (ce->hi & VTD_CONTEXT_ENTRY_AW); } =20 -static inline uint32_t vtd_get_agaw_from_context_entry(VTDContextEntry *ce) +static inline uint32_t vtd_ce_get_agaw(VTDContextEntry *ce) { return 30 + (ce->hi & VTD_CONTEXT_ENTRY_AW) * 9; } =20 static inline uint64_t vtd_iova_limit(VTDContextEntry *ce) { - uint32_t ce_agaw =3D vtd_get_agaw_from_context_entry(ce); + uint32_t ce_agaw =3D vtd_ce_get_agaw(ce); return 1ULL << MIN(ce_agaw, VTD_MGAW); } =20 @@ -642,8 +642,8 @@ static int vtd_iova_to_slpte(VTDContextEntry *ce, uint6= 4_t iova, bool is_write, uint64_t *slptep, uint32_t *slpte_level, bool *reads, bool *writes) { - dma_addr_t addr =3D vtd_get_slpt_base_from_context(ce); - uint32_t level =3D vtd_get_level_from_context_entry(ce); + dma_addr_t addr =3D vtd_ce_get_slpt_base(ce); + uint32_t level =3D vtd_ce_get_level(ce); uint32_t offset; uint64_t slpte; uint64_t access_right_check; @@ -664,7 +664,7 @@ static int vtd_iova_to_slpte(VTDContextEntry *ce, uint6= 4_t iova, bool is_write, VTD_DPRINTF(GENERAL, "error: fail to access second-level pagin= g " "entry at level %"PRIu32 " for iova 0x%"PRIx64, level, iova); - if (level =3D=3D vtd_get_level_from_context_entry(ce)) { + if (level =3D=3D vtd_ce_get_level(ce)) { /* Invalid programming of context-entry */ return -VTD_FR_CONTEXT_ENTRY_INV; } else { @@ -809,8 +809,8 @@ static int vtd_page_walk(VTDContextEntry *ce, uint64_t = start, uint64_t end, vtd_page_walk_hook hook_fn, void *private, bool notify_unmap) { - dma_addr_t addr =3D vtd_get_slpt_base_from_context(ce); - uint32_t level =3D vtd_get_level_from_context_entry(ce); + dma_addr_t addr =3D vtd_ce_get_slpt_base(ce); + uint32_t level =3D vtd_ce_get_level(ce); =20 if (!vtd_iova_range_check(start, ce)) { return -VTD_FR_ADDR_BEYOND_MGAW; @@ -851,7 +851,7 @@ static int vtd_dev_to_context_entry(IntelIOMMUState *s,= uint8_t bus_num, return ret_fr; } =20 - if (!vtd_context_entry_present(ce)) { + if (!vtd_ce_present(ce)) { /* Not error - it's okay we don't have context entry. */ trace_vtd_ce_not_present(bus_num, devfn); return -VTD_FR_CONTEXT_ENTRY_P; @@ -861,7 +861,7 @@ static int vtd_dev_to_context_entry(IntelIOMMUState *s,= uint8_t bus_num, return -VTD_FR_CONTEXT_ENTRY_RSVD; } /* Check if the programming of context-entry is valid */ - if (!vtd_is_level_supported(s, vtd_get_level_from_context_entry(ce))) { + if (!vtd_is_level_supported(s, vtd_ce_get_level(ce))) { trace_vtd_ce_invalid(ce->hi, ce->lo); return -VTD_FR_CONTEXT_ENTRY_INV; } else { --=20 2.7.4 From nobody Fri May 3 12:50:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1495164262880832.6199881751489; Thu, 18 May 2017 20:24:22 -0700 (PDT) Received: from localhost ([::1]:56370 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dBYWb-0001Qz-IQ for importer@patchew.org; Thu, 18 May 2017 23:24:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35435) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dBYT8-0006zD-IO for qemu-devel@nongnu.org; Thu, 18 May 2017 23:20:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dBYT4-0005bQ-KE for qemu-devel@nongnu.org; Thu, 18 May 2017 23:20:46 -0400 Received: from mx1.redhat.com ([209.132.183.28]:41192) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dBYT4-0005b9-Db for qemu-devel@nongnu.org; Thu, 18 May 2017 23:20:42 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 63E7E80F97; Fri, 19 May 2017 03:20:41 +0000 (UTC) Received: from pxdev.xzpeter.org.com (ovpn-12-101.pek2.redhat.com [10.72.12.101]) by smtp.corp.redhat.com (Postfix) with ESMTP id 250E1784C2; Fri, 19 May 2017 03:20:32 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 63E7E80F97 Authentication-Results: ext-mx03.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx03.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=peterx@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com 63E7E80F97 From: Peter Xu To: qemu-devel@nongnu.org Date: Fri, 19 May 2017 11:19:44 +0800 Message-Id: <1495163989-9994-6-git-send-email-peterx@redhat.com> In-Reply-To: <1495163989-9994-1-git-send-email-peterx@redhat.com> References: <1495163989-9994-1-git-send-email-peterx@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Fri, 19 May 2017 03:20:41 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v4 05/10] intel_iommu: provide vtd_ce_get_type() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lan Tianyu , yi.l.liu@intel.com, "Michael S . Tsirkin" , Jason Wang , peterx@redhat.com, Marcel Apfelbaum , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Helper to fetch VT-d context entry type. Signed-off-by: Peter Xu Reviewed-by: Jason Wang --- hw/i386/intel_iommu.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index f06055f..b477143 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -595,6 +595,11 @@ static inline uint32_t vtd_ce_get_agaw(VTDContextEntry= *ce) return 30 + (ce->hi & VTD_CONTEXT_ENTRY_AW) * 9; } =20 +static inline uint32_t vtd_ce_get_type(VTDContextEntry *ce) +{ + return ce->lo & VTD_CONTEXT_ENTRY_TT; +} + static inline uint64_t vtd_iova_limit(VTDContextEntry *ce) { uint32_t ce_agaw =3D vtd_ce_get_agaw(ce); @@ -865,7 +870,7 @@ static int vtd_dev_to_context_entry(IntelIOMMUState *s,= uint8_t bus_num, trace_vtd_ce_invalid(ce->hi, ce->lo); return -VTD_FR_CONTEXT_ENTRY_INV; } else { - switch (ce->lo & VTD_CONTEXT_ENTRY_TT) { + switch (vtd_ce_get_type(ce)) { case VTD_CONTEXT_TT_MULTI_LEVEL: /* fall through */ case VTD_CONTEXT_TT_DEV_IOTLB: --=20 2.7.4 From nobody Fri May 3 12:50:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1495164388132117.49520316184385; Thu, 18 May 2017 20:26:28 -0700 (PDT) Received: from localhost ([::1]:56383 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dBYYc-00033z-SZ for importer@patchew.org; Thu, 18 May 2017 23:26:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35476) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dBYTB-00071C-JC for qemu-devel@nongnu.org; Thu, 18 May 2017 23:20:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dBYT8-0005d8-Ea for qemu-devel@nongnu.org; Thu, 18 May 2017 23:20:49 -0400 Received: from mx1.redhat.com ([209.132.183.28]:45456) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dBYT8-0005cT-8L for qemu-devel@nongnu.org; Thu, 18 May 2017 23:20:46 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 054B481F01; Fri, 19 May 2017 03:20:45 +0000 (UTC) Received: from pxdev.xzpeter.org.com (ovpn-12-101.pek2.redhat.com [10.72.12.101]) by smtp.corp.redhat.com (Postfix) with ESMTP id EEFC8784C2; Fri, 19 May 2017 03:20:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 054B481F01 Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=peterx@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com 054B481F01 From: Peter Xu To: qemu-devel@nongnu.org Date: Fri, 19 May 2017 11:19:45 +0800 Message-Id: <1495163989-9994-7-git-send-email-peterx@redhat.com> In-Reply-To: <1495163989-9994-1-git-send-email-peterx@redhat.com> References: <1495163989-9994-1-git-send-email-peterx@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.25]); Fri, 19 May 2017 03:20:45 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v4 06/10] intel_iommu: use IOMMU_ACCESS_FLAG() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lan Tianyu , yi.l.liu@intel.com, "Michael S . Tsirkin" , Jason Wang , peterx@redhat.com, Marcel Apfelbaum , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We have that now, so why not use it. Signed-off-by: Peter Xu Reviewed-by: Jason Wang --- hw/i386/intel_iommu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index b477143..3240e5d 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -1010,7 +1010,7 @@ out: entry->iova =3D addr & page_mask; entry->translated_addr =3D vtd_get_slpte_addr(slpte) & page_mask; entry->addr_mask =3D ~page_mask; - entry->perm =3D (writes ? 2 : 0) + (reads ? 1 : 0); + entry->perm =3D IOMMU_ACCESS_FLAG(reads, writes); } =20 static void vtd_root_table_setup(IntelIOMMUState *s) --=20 2.7.4 From nobody Fri May 3 12:50:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1495164460055129.30207929266817; Thu, 18 May 2017 20:27:40 -0700 (PDT) Received: from localhost ([::1]:56388 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dBYZm-0004Ja-IM for importer@patchew.org; Thu, 18 May 2017 23:27:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35501) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dBYTC-00072H-UD for qemu-devel@nongnu.org; Thu, 18 May 2017 23:20:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dBYTB-0005eh-Vt for qemu-devel@nongnu.org; Thu, 18 May 2017 23:20:50 -0400 Received: from mx1.redhat.com ([209.132.183.28]:37358) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dBYTB-0005eO-MZ for qemu-devel@nongnu.org; Thu, 18 May 2017 23:20:49 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id A57FA8553C; Fri, 19 May 2017 03:20:48 +0000 (UTC) Received: from pxdev.xzpeter.org.com (ovpn-12-101.pek2.redhat.com [10.72.12.101]) by smtp.corp.redhat.com (Postfix) with ESMTP id 9D7CE784C2; Fri, 19 May 2017 03:20:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com A57FA8553C Authentication-Results: ext-mx04.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx04.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=peterx@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com A57FA8553C From: Peter Xu To: qemu-devel@nongnu.org Date: Fri, 19 May 2017 11:19:46 +0800 Message-Id: <1495163989-9994-8-git-send-email-peterx@redhat.com> In-Reply-To: <1495163989-9994-1-git-send-email-peterx@redhat.com> References: <1495163989-9994-1-git-send-email-peterx@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Fri, 19 May 2017 03:20:48 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v4 07/10] intel_iommu: allow dev-iotlb context entry conditionally X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lan Tianyu , yi.l.liu@intel.com, "Michael S . Tsirkin" , Jason Wang , peterx@redhat.com, Marcel Apfelbaum , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When device-iotlb is not specified, we should fail this check. A new function vtd_ce_type_check() is introduced. While I'm at it, clean up the vtd_dev_to_context_entry() a bit - replace many "else if" usage into direct if check. That'll make the logic more clear. Signed-off-by: Peter Xu Reviewed-by: Jason Wang --- hw/i386/intel_iommu.c | 49 ++++++++++++++++++++++++++++++++++++-----------= -- 1 file changed, 36 insertions(+), 13 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 3240e5d..aac2cc7 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -600,6 +600,26 @@ static inline uint32_t vtd_ce_get_type(VTDContextEntry= *ce) return ce->lo & VTD_CONTEXT_ENTRY_TT; } =20 +/* Return true if check passed, otherwise false */ +static inline bool vtd_ce_type_check(X86IOMMUState *x86_iommu, + VTDContextEntry *ce) +{ + switch (vtd_ce_get_type(ce)) { + case VTD_CONTEXT_TT_MULTI_LEVEL: + /* Always supported */ + break; + case VTD_CONTEXT_TT_DEV_IOTLB: + if (!x86_iommu->dt_supported) { + return false; + } + break; + default: + /* Unknwon type */ + return false; + } + return true; +} + static inline uint64_t vtd_iova_limit(VTDContextEntry *ce) { uint32_t ce_agaw =3D vtd_ce_get_agaw(ce); @@ -836,6 +856,7 @@ static int vtd_dev_to_context_entry(IntelIOMMUState *s,= uint8_t bus_num, { VTDRootEntry re; int ret_fr; + X86IOMMUState *x86_iommu =3D X86_IOMMU_DEVICE(s); =20 ret_fr =3D vtd_get_root_entry(s, bus_num, &re); if (ret_fr) { @@ -846,7 +867,9 @@ static int vtd_dev_to_context_entry(IntelIOMMUState *s,= uint8_t bus_num, /* Not error - it's okay we don't have root entry. */ trace_vtd_re_not_present(bus_num); return -VTD_FR_ROOT_ENTRY_P; - } else if (re.rsvd || (re.val & VTD_ROOT_ENTRY_RSVD)) { + } + + if (re.rsvd || (re.val & VTD_ROOT_ENTRY_RSVD)) { trace_vtd_re_invalid(re.rsvd, re.val); return -VTD_FR_ROOT_ENTRY_RSVD; } @@ -860,26 +883,26 @@ static int vtd_dev_to_context_entry(IntelIOMMUState *= s, uint8_t bus_num, /* Not error - it's okay we don't have context entry. */ trace_vtd_ce_not_present(bus_num, devfn); return -VTD_FR_CONTEXT_ENTRY_P; - } else if ((ce->hi & VTD_CONTEXT_ENTRY_RSVD_HI) || - (ce->lo & VTD_CONTEXT_ENTRY_RSVD_LO)) { + } + + if ((ce->hi & VTD_CONTEXT_ENTRY_RSVD_HI) || + (ce->lo & VTD_CONTEXT_ENTRY_RSVD_LO)) { trace_vtd_ce_invalid(ce->hi, ce->lo); return -VTD_FR_CONTEXT_ENTRY_RSVD; } + /* Check if the programming of context-entry is valid */ if (!vtd_is_level_supported(s, vtd_ce_get_level(ce))) { trace_vtd_ce_invalid(ce->hi, ce->lo); return -VTD_FR_CONTEXT_ENTRY_INV; - } else { - switch (vtd_ce_get_type(ce)) { - case VTD_CONTEXT_TT_MULTI_LEVEL: - /* fall through */ - case VTD_CONTEXT_TT_DEV_IOTLB: - break; - default: - trace_vtd_ce_invalid(ce->hi, ce->lo); - return -VTD_FR_CONTEXT_ENTRY_INV; - } } + + /* Do translation type check */ + if (!vtd_ce_type_check(x86_iommu, ce)) { + trace_vtd_ce_invalid(ce->hi, ce->lo); + return -VTD_FR_CONTEXT_ENTRY_INV; + } + return 0; } =20 --=20 2.7.4 From nobody Fri May 3 12:50:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1495164174810463.5771850541536; Thu, 18 May 2017 20:22:54 -0700 (PDT) Received: from localhost ([::1]:56361 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dBYVB-0008Mh-Dc for importer@patchew.org; Thu, 18 May 2017 23:22:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35569) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dBYTH-000761-Lf for qemu-devel@nongnu.org; Thu, 18 May 2017 23:20:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dBYTF-0005g5-TU for qemu-devel@nongnu.org; Thu, 18 May 2017 23:20:55 -0400 Received: from mx1.redhat.com ([209.132.183.28]:46574) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dBYTF-0005fa-Eg for qemu-devel@nongnu.org; Thu, 18 May 2017 23:20:53 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 72BBA61D04; Fri, 19 May 2017 03:20:52 +0000 (UTC) Received: from pxdev.xzpeter.org.com (ovpn-12-101.pek2.redhat.com [10.72.12.101]) by smtp.corp.redhat.com (Postfix) with ESMTP id 33A20784C2; Fri, 19 May 2017 03:20:48 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 72BBA61D04 Authentication-Results: ext-mx10.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx10.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=peterx@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com 72BBA61D04 From: Peter Xu To: qemu-devel@nongnu.org Date: Fri, 19 May 2017 11:19:47 +0800 Message-Id: <1495163989-9994-9-git-send-email-peterx@redhat.com> In-Reply-To: <1495163989-9994-1-git-send-email-peterx@redhat.com> References: <1495163989-9994-1-git-send-email-peterx@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.39]); Fri, 19 May 2017 03:20:52 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v4 08/10] intel_iommu: support passthrough (PT) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lan Tianyu , yi.l.liu@intel.com, "Michael S . Tsirkin" , Jason Wang , peterx@redhat.com, Marcel Apfelbaum , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Hardware support for VT-d device passthrough. Although current Linux can live with iommu=3Dpt even without this, but this is faster than when using software passthrough. Signed-off-by: Peter Xu Reviewed-by: Jason Wang Reviewed-by: Liu, Yi L --- hw/i386/intel_iommu.c | 231 ++++++++++++++++++++++++++++++-------= ---- hw/i386/intel_iommu_internal.h | 1 + hw/i386/trace-events | 2 + hw/i386/x86-iommu.c | 1 + include/hw/i386/x86-iommu.h | 1 + 5 files changed, 177 insertions(+), 59 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index aac2cc7..15610b9 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -613,6 +613,11 @@ static inline bool vtd_ce_type_check(X86IOMMUState *x8= 6_iommu, return false; } break; + case VTD_CONTEXT_TT_PASS_THROUGH: + if (!x86_iommu->pt_supported) { + return false; + } + break; default: /* Unknwon type */ return false; @@ -660,6 +665,29 @@ static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, uin= t32_t level) } } =20 +/* Find the VTD address space associated with a given bus number */ +static VTDBus *vtd_find_as_from_bus_num(IntelIOMMUState *s, uint8_t bus_nu= m) +{ + VTDBus *vtd_bus =3D s->vtd_as_by_bus_num[bus_num]; + if (!vtd_bus) { + /* + * Iterate over the registered buses to find the one which + * currently hold this bus number, and update the bus_num + * lookup table: + */ + GHashTableIter iter; + + g_hash_table_iter_init(&iter, s->vtd_as_by_busptr); + while (g_hash_table_iter_next(&iter, NULL, (void **)&vtd_bus)) { + if (pci_bus_num(vtd_bus->bus) =3D=3D bus_num) { + s->vtd_as_by_bus_num[bus_num] =3D vtd_bus; + return vtd_bus; + } + } + } + return vtd_bus; +} + /* Given the @iova, get relevant @slptep. @slpte_level will be the last le= vel * of the translation, can be used for deciding the size of large page. */ @@ -906,6 +934,91 @@ static int vtd_dev_to_context_entry(IntelIOMMUState *s= , uint8_t bus_num, return 0; } =20 +/* + * Fetch translation type for specific device. Returns <0 if error + * happens, otherwise return the shifted type to check against + * VTD_CONTEXT_TT_*. + */ +static int vtd_dev_get_trans_type(VTDAddressSpace *as) +{ + IntelIOMMUState *s; + VTDContextEntry ce; + int ret; + + s =3D as->iommu_state; + + ret =3D vtd_dev_to_context_entry(s, pci_bus_num(as->bus), + as->devfn, &ce); + if (ret) { + return ret; + } + + return vtd_ce_get_type(&ce); +} + +static bool vtd_dev_pt_enabled(VTDAddressSpace *as) +{ + int ret; + + assert(as); + + ret =3D vtd_dev_get_trans_type(as); + if (ret < 0) { + /* + * Possibly failed to parse the context entry for some reason + * (e.g., during init, or any guest configuration errors on + * context entries). We should assume PT not enabled for + * safety. + */ + return false; + } + + return ret =3D=3D VTD_CONTEXT_TT_PASS_THROUGH; +} + +/* Return whether the device is using IOMMU translation. */ +static bool vtd_switch_address_space(VTDAddressSpace *as) +{ + bool use_iommu; + + assert(as); + + use_iommu =3D as->iommu_state->dmar_enabled & !vtd_dev_pt_enabled(as); + + trace_vtd_switch_address_space(pci_bus_num(as->bus), + VTD_PCI_SLOT(as->devfn), + VTD_PCI_FUNC(as->devfn), + use_iommu); + + /* Turn off first then on the other */ + if (use_iommu) { + memory_region_set_enabled(&as->sys_alias, false); + memory_region_set_enabled(&as->iommu, true); + } else { + memory_region_set_enabled(&as->iommu, false); + memory_region_set_enabled(&as->sys_alias, true); + } + + return use_iommu; +} + +static void vtd_switch_address_space_all(IntelIOMMUState *s) +{ + GHashTableIter iter; + VTDBus *vtd_bus; + int i; + + g_hash_table_iter_init(&iter, s->vtd_as_by_busptr); + while (g_hash_table_iter_next(&iter, NULL, (void **)&vtd_bus)) { + for (i =3D 0; i < X86_IOMMU_PCI_DEVFN_MAX; i++) { + if (!vtd_bus->dev_as[i]) { + continue; + } + vtd_switch_address_space(vtd_bus->dev_as[i]); + } + } +} + static inline uint16_t vtd_make_source_id(uint8_t bus_num, uint8_t devfn) { return ((bus_num & 0xffUL) << 8) | (devfn & 0xffUL); @@ -943,6 +1056,31 @@ static inline bool vtd_is_interrupt_addr(hwaddr addr) return VTD_INTERRUPT_ADDR_FIRST <=3D addr && addr <=3D VTD_INTERRUPT_A= DDR_LAST; } =20 +static void vtd_pt_enable_fast_path(IntelIOMMUState *s, uint16_t source_id) +{ + VTDBus *vtd_bus; + VTDAddressSpace *vtd_as; + bool success =3D false; + + vtd_bus =3D vtd_find_as_from_bus_num(s, VTD_SID_TO_BUS(source_id)); + if (!vtd_bus) { + goto out; + } + + vtd_as =3D vtd_bus->dev_as[VTD_SID_TO_DEVFN(source_id)]; + if (!vtd_as) { + goto out; + } + + if (vtd_switch_address_space(vtd_as) =3D=3D false) { + /* We switched off IOMMU region successfully. */ + success =3D true; + } + +out: + trace_vtd_pt_enable_fast_path(source_id, success); +} + /* Map dev to context-entry then do a paging-structures walk to do a iommu * translation. * @@ -1014,6 +1152,30 @@ static void vtd_do_iommu_translate(VTDAddressSpace *= vtd_as, PCIBus *bus, cc_entry->context_cache_gen =3D s->context_cache_gen; } =20 + /* + * We don't need to translate for pass-through context entries. + * Also, let's ignore IOTLB caching as well for PT devices. + */ + if (vtd_ce_get_type(&ce) =3D=3D VTD_CONTEXT_TT_PASS_THROUGH) { + entry->translated_addr =3D entry->iova; + entry->addr_mask =3D VTD_PAGE_SIZE - 1; + entry->perm =3D IOMMU_RW; + trace_vtd_translate_pt(source_id, entry->iova); + + /* + * When this happens, it means firstly caching-mode is not + * enabled, and this is the first passthrough translation for + * the device. Let's enable the fast path for passthrough. + * + * When passthrough is disabled again for the device, we can + * capture it via the context entry invalidation, then the + * IOMMU region can be swapped back. + */ + vtd_pt_enable_fast_path(s, source_id); + + return; + } + ret_fr =3D vtd_iova_to_slpte(&ce, addr, is_write, &slpte, &level, &reads, &writes); if (ret_fr) { @@ -1083,6 +1245,7 @@ static void vtd_context_global_invalidate(IntelIOMMUS= tate *s) if (s->context_cache_gen =3D=3D VTD_CONTEXT_CACHE_GEN_MAX) { vtd_reset_context_cache(s); } + vtd_switch_address_space_all(s); /* * From VT-d spec 6.5.2.1, a global context entry invalidation * should be followed by a IOTLB global invalidation, so we should @@ -1093,29 +1256,6 @@ static void vtd_context_global_invalidate(IntelIOMMU= State *s) vtd_iommu_replay_all(s); } =20 - -/* Find the VTD address space currently associated with a given bus number, - */ -static VTDBus *vtd_find_as_from_bus_num(IntelIOMMUState *s, uint8_t bus_nu= m) -{ - VTDBus *vtd_bus =3D s->vtd_as_by_bus_num[bus_num]; - if (!vtd_bus) { - /* Iterate over the registered buses to find the one - * which currently hold this bus number, and update the bus_num lo= okup table: - */ - GHashTableIter iter; - - g_hash_table_iter_init(&iter, s->vtd_as_by_busptr); - while (g_hash_table_iter_next (&iter, NULL, (void**)&vtd_bus)) { - if (pci_bus_num(vtd_bus->bus) =3D=3D bus_num) { - s->vtd_as_by_bus_num[bus_num] =3D vtd_bus; - return vtd_bus; - } - } - } - return vtd_bus; -} - /* Do a context-cache device-selective invalidation. * @func_mask: FM field after shifting */ @@ -1158,6 +1298,11 @@ static void vtd_context_device_invalidate(IntelIOMMU= State *s, VTD_PCI_FUNC(devfn_it)); vtd_as->context_cache_entry.context_cache_gen =3D 0; /* + * Do switch address space when needed, in case if the + * device passthrough bit is switched. + */ + vtd_switch_address_space(vtd_as); + /* * So a device is moving out of (or moving into) a * domain, a replay() suites here to notify all the * IOMMU_NOTIFIER_MAP registers about this change. @@ -1389,42 +1534,6 @@ static void vtd_handle_gcmd_sirtp(IntelIOMMUState *s) vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_IRTPS); } =20 -static void vtd_switch_address_space(VTDAddressSpace *as) -{ - assert(as); - - trace_vtd_switch_address_space(pci_bus_num(as->bus), - VTD_PCI_SLOT(as->devfn), - VTD_PCI_FUNC(as->devfn), - as->iommu_state->dmar_enabled); - - /* Turn off first then on the other */ - if (as->iommu_state->dmar_enabled) { - memory_region_set_enabled(&as->sys_alias, false); - memory_region_set_enabled(&as->iommu, true); - } else { - memory_region_set_enabled(&as->iommu, false); - memory_region_set_enabled(&as->sys_alias, true); - } -} - -static void vtd_switch_address_space_all(IntelIOMMUState *s) -{ - GHashTableIter iter; - VTDBus *vtd_bus; - int i; - - g_hash_table_iter_init(&iter, s->vtd_as_by_busptr); - while (g_hash_table_iter_next(&iter, NULL, (void **)&vtd_bus)) { - for (i =3D 0; i < X86_IOMMU_PCI_DEVFN_MAX; i++) { - if (!vtd_bus->dev_as[i]) { - continue; - } - vtd_switch_address_space(vtd_bus->dev_as[i]); - } - } -} - /* Handle Translation Enable/Disable */ static void vtd_handle_gcmd_te(IntelIOMMUState *s, bool en) { @@ -2872,6 +2981,10 @@ static void vtd_init(IntelIOMMUState *s) s->ecap |=3D VTD_ECAP_DT; } =20 + if (x86_iommu->pt_supported) { + s->ecap |=3D VTD_ECAP_PT; + } + if (s->caching_mode) { s->cap |=3D VTD_CAP_CM; } diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 29d6707..0e73a65 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -187,6 +187,7 @@ /* Interrupt Remapping support */ #define VTD_ECAP_IR (1ULL << 3) #define VTD_ECAP_EIM (1ULL << 4) +#define VTD_ECAP_PT (1ULL << 6) #define VTD_ECAP_MHMV (15ULL << 20) =20 /* CAP_REG */ diff --git a/hw/i386/trace-events b/hw/i386/trace-events index 04a6980..72556da 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -38,6 +38,8 @@ vtd_page_walk_skip_perm(uint64_t iova, uint64_t next) "Pa= ge walk skip iova 0x%"P vtd_page_walk_skip_reserve(uint64_t iova, uint64_t next) "Page walk skip i= ova 0x%"PRIx64" - 0x%"PRIx64" due to rsrv set" vtd_switch_address_space(uint8_t bus, uint8_t slot, uint8_t fn, bool on) "= Device %02x:%02x.%x switching address space (iommu enabled=3D%d)" vtd_as_unmap_whole(uint8_t bus, uint8_t slot, uint8_t fn, uint64_t iova, u= int64_t size) "Device %02x:%02x.%x start 0x%"PRIx64" size 0x%"PRIx64 +vtd_translate_pt(uint16_t sid, uint64_t addr) "source id 0x%"PRIu16", iova= 0x%"PRIx64 +vtd_pt_enable_fast_path(uint16_t sid, bool success) "sid 0x%"PRIu16" %d" =20 # hw/i386/amd_iommu.c amdvi_evntlog_fail(uint64_t addr, uint32_t head) "error: fail to write at = addr 0x%"PRIx64" + offset 0x%"PRIx32 diff --git a/hw/i386/x86-iommu.c b/hw/i386/x86-iommu.c index 02b8825..293caf8 100644 --- a/hw/i386/x86-iommu.c +++ b/hw/i386/x86-iommu.c @@ -91,6 +91,7 @@ static void x86_iommu_realize(DeviceState *dev, Error **e= rrp) static Property x86_iommu_properties[] =3D { DEFINE_PROP_BOOL("intremap", X86IOMMUState, intr_supported, false), DEFINE_PROP_BOOL("device-iotlb", X86IOMMUState, dt_supported, false), + DEFINE_PROP_BOOL("pt", X86IOMMUState, pt_supported, true), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/include/hw/i386/x86-iommu.h b/include/hw/i386/x86-iommu.h index 361c07c..ef89c0c 100644 --- a/include/hw/i386/x86-iommu.h +++ b/include/hw/i386/x86-iommu.h @@ -74,6 +74,7 @@ struct X86IOMMUState { SysBusDevice busdev; bool intr_supported; /* Whether vIOMMU supports IR */ bool dt_supported; /* Whether vIOMMU supports DT */ + bool pt_supported; /* Whether vIOMMU supports pass-through */ IommuType type; /* IOMMU type - AMD/Intel */ QLIST_HEAD(, IEC_Notifier) iec_notifiers; /* IEC notify list */ }; --=20 2.7.4 From nobody Fri May 3 12:50:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1495164504204592.4550492661126; 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Fri, 19 May 2017 03:21:02 +0000 (UTC) Received: from pxdev.xzpeter.org.com (ovpn-12-101.pek2.redhat.com [10.72.12.101]) by smtp.corp.redhat.com (Postfix) with ESMTP id 1DE9C784C2; Fri, 19 May 2017 03:20:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 44AC780C0A Authentication-Results: ext-mx02.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx02.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=peterx@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com 44AC780C0A From: Peter Xu To: qemu-devel@nongnu.org Date: Fri, 19 May 2017 11:19:48 +0800 Message-Id: <1495163989-9994-10-git-send-email-peterx@redhat.com> In-Reply-To: <1495163989-9994-1-git-send-email-peterx@redhat.com> References: <1495163989-9994-1-git-send-email-peterx@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.26]); Fri, 19 May 2017 03:21:02 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v4 09/10] intel_iommu: turn off pt before 2.9 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lan Tianyu , yi.l.liu@intel.com, "Michael S . Tsirkin" , Jason Wang , peterx@redhat.com, Marcel Apfelbaum , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is for compatibility. Signed-off-by: Peter Xu Reviewed-by: Jason Wang --- include/hw/compat.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/hw/compat.h b/include/hw/compat.h index 55b1765..4c53d60 100644 --- a/include/hw/compat.h +++ b/include/hw/compat.h @@ -6,6 +6,10 @@ .driver =3D "pci-bridge",\ .property =3D "shpc",\ .value =3D "off",\ + },{\ + .driver =3D "intel-iommu",\ + .property =3D "pt",\ + .value =3D "off",\ }, =20 #define HW_COMPAT_2_8 \ --=20 2.7.4 From nobody Fri May 3 12:50:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1495164409022533.2348476087004; Thu, 18 May 2017 20:26:49 -0700 (PDT) Received: from localhost ([::1]:56385 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dBYYx-0003KC-Fg for importer@patchew.org; Thu, 18 May 2017 23:26:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35796) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dBYTU-0007Gd-WB for qemu-devel@nongnu.org; Thu, 18 May 2017 23:21:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dBYTT-0005lF-V3 for qemu-devel@nongnu.org; Thu, 18 May 2017 23:21:08 -0400 Received: from mx1.redhat.com ([209.132.183.28]:37444) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dBYTT-0005ku-Lm for qemu-devel@nongnu.org; Thu, 18 May 2017 23:21:07 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id A81658553C; Fri, 19 May 2017 03:21:06 +0000 (UTC) Received: from pxdev.xzpeter.org.com (ovpn-12-101.pek2.redhat.com [10.72.12.101]) by smtp.corp.redhat.com (Postfix) with ESMTP id CB15A7E5CC; Fri, 19 May 2017 03:21:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com A81658553C Authentication-Results: ext-mx04.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx04.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=peterx@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com A81658553C From: Peter Xu To: qemu-devel@nongnu.org Date: Fri, 19 May 2017 11:19:49 +0800 Message-Id: <1495163989-9994-11-git-send-email-peterx@redhat.com> In-Reply-To: <1495163989-9994-1-git-send-email-peterx@redhat.com> References: <1495163989-9994-1-git-send-email-peterx@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Fri, 19 May 2017 03:21:06 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v4 10/10] vhost: iommu: cache static mapping if there is X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lan Tianyu , yi.l.liu@intel.com, "Michael S . Tsirkin" , Jason Wang , peterx@redhat.com, Marcel Apfelbaum , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch pre-heat vhost iotlb cache when passthrough mode enabled. Sometimes, even if user specified iommu_platform for vhost devices, IOMMU might still be disabled. One case is passthrough mode in VT-d implementation. We can detect this by observing iommu_list. If it's empty, it means IOMMU translation is disabled, then we can actually pre-heat the translation (it'll be static mapping then) by first invalidating all IOTLB, then cache existing memory ranges into vhost backend iotlb using 1:1 mapping. Signed-off-by: Peter Xu Reviewed-by: Jason Wang --- hw/virtio/trace-events | 4 ++++ hw/virtio/vhost.c | 49 ++++++++++++++++++++++++++++++++++++++++++++++= +++ 2 files changed, 53 insertions(+) diff --git a/hw/virtio/trace-events b/hw/virtio/trace-events index 1f7a7c1..54dcbb3 100644 --- a/hw/virtio/trace-events +++ b/hw/virtio/trace-events @@ -24,3 +24,7 @@ virtio_balloon_handle_output(const char *name, uint64_t g= pa) "section name: %s g virtio_balloon_get_config(uint32_t num_pages, uint32_t actual) "num_pages:= %d actual: %d" virtio_balloon_set_config(uint32_t actual, uint32_t oldactual) "actual: %d= oldactual: %d" virtio_balloon_to_target(uint64_t target, uint32_t num_pages) "balloon tar= get: %"PRIx64" num_pages: %d" + +# hw/virtio/vhost.c +vhost_iommu_commit(void) "" +vhost_iommu_static_preheat(void) "" diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c index 03a46a7..8069135 100644 --- a/hw/virtio/vhost.c +++ b/hw/virtio/vhost.c @@ -27,6 +27,7 @@ #include "hw/virtio/virtio-access.h" #include "migration/blocker.h" #include "sysemu/dma.h" +#include "trace.h" =20 /* enabled until disconnected backend stabilizes */ #define _VHOST_DEBUG 1 @@ -730,6 +731,11 @@ static void vhost_iommu_unmap_notify(IOMMUNotifier *n,= IOMMUTLBEntry *iotlb) } } =20 +static bool vhost_iommu_mr_enabled(struct vhost_dev *dev) +{ + return !QLIST_EMPTY(&dev->iommu_list); +} + static void vhost_iommu_region_add(MemoryListener *listener, MemoryRegionSection *section) { @@ -782,6 +788,48 @@ static void vhost_iommu_region_del(MemoryListener *lis= tener, } } =20 +static void vhost_iommu_commit(MemoryListener *listener) +{ + struct vhost_dev *dev =3D container_of(listener, struct vhost_dev, + iommu_listener); + struct vhost_memory_region *r; + int i; + + trace_vhost_iommu_commit(); + + if (!vhost_iommu_mr_enabled(dev)) { + /* + * This means iommu_platform is enabled, however iommu memory + * region is disabled, e.g., when device passthrough is setup. + * Then, no translation is needed any more. + * + * Let's first invalidate the whole IOTLB, then pre-heat the + * static mapping by looping over vhost memory ranges. + */ + + if (dev->vhost_ops->vhost_invalidate_device_iotlb(dev, 0, + UINT64_MAX)) { + error_report("%s: flush existing IOTLB failed", __func__); + return; + } + + for (i =3D 0; i < dev->mem->nregions; i++) { + r =3D &dev->mem->regions[i]; + /* Vhost regions are writable RAM, so IOMMU_RW suites. */ + if (dev->vhost_ops->vhost_update_device_iotlb(dev, + r->guest_phys_ad= dr, + r->userspace_add= r, + r->memory_size, + IOMMU_RW)) { + error_report("%s: pre-heat static mapping failed", __func_= _); + return; + } + } + + trace_vhost_iommu_static_preheat(); + } +} + static void vhost_region_nop(MemoryListener *listener, MemoryRegionSection *section) { @@ -1298,6 +1346,7 @@ int vhost_dev_init(struct vhost_dev *hdev, void *opaq= ue, hdev->iommu_listener =3D (MemoryListener) { .region_add =3D vhost_iommu_region_add, .region_del =3D vhost_iommu_region_del, + .commit =3D vhost_iommu_commit, }; =20 if (hdev->migration_blocker =3D=3D NULL) { --=20 2.7.4