From nobody Fri May 3 00:52:40 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1495021676490498.69327785652763; Wed, 17 May 2017 04:47:56 -0700 (PDT) Received: from localhost ([::1]:47159 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dAxQn-0006o0-Ow for importer@patchew.org; Wed, 17 May 2017 07:47:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46154) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dAxPy-0006OG-Cz for qemu-devel@nongnu.org; Wed, 17 May 2017 07:47:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dAxPv-0004Cz-C3 for qemu-devel@nongnu.org; Wed, 17 May 2017 07:47:02 -0400 Received: from mail-wm0-x244.google.com ([2a00:1450:400c:c09::244]:34482) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dAxPv-0004CR-2f for qemu-devel@nongnu.org; Wed, 17 May 2017 07:46:59 -0400 Received: by mail-wm0-x244.google.com with SMTP id d127so2937339wmf.1 for ; Wed, 17 May 2017 04:46:58 -0700 (PDT) Received: from localhost.localdomain ([141.226.163.173]) by smtp.gmail.com with ESMTPSA id o18sm2101554wrb.47.2017.05.17.04.46.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 17 May 2017 04:46:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id; bh=fJ9zX/B4Fe/KpZjZ9poyx1fjzZ6GNK7XY7tMhPf7Daw=; b=gsKhOkzLvaBSVPjkLq6QvwYmg67QB6r/0kdl4hPo97p7+O5Bi6IQm+WJ+b1MnCOMBc 3moOHNnIKDweqE+Fek/ObdjpI+tyzw8viYPko4v5gSQKvPFdRhKtDGxQgw92aGQ7VX4s v+Dr6j5vkAgg8y1t4ib5eRfH0w3EbiVIDSrkclRM21bgTWUKY8V18TmCyGRtkqh3ZBfZ y3Mnmika/LeaeDjp8vCszAqlctjxxCg2S3kJMDvRZ1SB2j+LM62wyzMqRhgFEP2QpaKR i6LPopgZ7v1FUdRC03uTFzIFO3BLXj76veUujoLI5XpiSnqBJIz8S5EpJsZDTLRVQqeR pGBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=fJ9zX/B4Fe/KpZjZ9poyx1fjzZ6GNK7XY7tMhPf7Daw=; b=cVSOb36B8lOoxLw/Tp70KBCl4/4yrrCduteMSQobNmSNzo09INSWHWvHI6AK7/ACrT WnoIhO/D8xJtOb5jdfoJtgn+9r2HxPh2S8XDxbbiSbl9Dc+XlGZGRUCYaYTQ/e8wEbyO Z8sJPq3eYlR3pH9u8ntuoKRWiwrXQHeJ1zFWmOotFmZWW8Pwnypi4p0AT2tLyW6gK8Nw IJpkkw1BOTof/An3JuHtjEIe8Wnti7hq9arF7PGLs4tbGi88ukw+Yvh7lJ5VspqWRINT 2nb40G6j3WXjB30p3N7aVkyKE8ldWi0pngKW255986KVcaOntn0HUvQ67ogS3m064JpK LVVA== X-Gm-Message-State: AODbwcBVnS0/yl9x6g/3ATAd3j6e7EfPQ64aRX5smV6AkSUXrvNCCi7i I2/hGOUJiLiFCWA4 X-Received: by 10.28.135.7 with SMTP id j7mr348423wmd.56.1495021617364; Wed, 17 May 2017 04:46:57 -0700 (PDT) From: Sameeh Jubran To: qemu-devel@nongnu.org, Jason Wang , Dmitry Fleytman Date: Wed, 17 May 2017 14:46:12 +0300 Message-Id: <1495021572-20852-1-git-send-email-sameeh@daynix.com> X-Mailer: git-send-email 2.7.0.windows.1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::244 Subject: [Qemu-devel] [PATCH] e1000e: Fix a bug where guest hangs upon migration X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yan Vugenfirer Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The bug was caused by the "receive overrun" (bit #6 of the ICR register) in= terrupt which would be triggered post migration in a heavy traffic environment. Eve= n though the "receive overrun" bit (#6) is masked out by the IMS register (refer to the = log below) the driver still receives an interrupt as the "receive overrun" bit (#6) ca= uses the "Other" - bit #24 of the ICR register - bit to be set as documented below. = The driver handles the interrupt and clears the "Other" bit (#24) but doesn't clear the "receive overrun" bit (#6) which leads to an infinite loop. Apparently the = Windows driver expects that the "receive overrun" bit and other ones - documented b= elow - to be cleared when the "Other" bit (#24) is cleared. So to sum that up: 1. Bit #6 of the ICR register is set by heavy traffic 2. As a results of setting bit #6, bit #24 is set 3. The driver receives an interrupt for bit 24 (it doesn't receieve an inte= rrupt for bit #6 as it is masked out by IMS) 4. The driver handles and clears the interrupt of bit #24 5. Bit #6 is still set. 6. 2 happens all over again The Interrupt Cause Read - ICR register: The ICR has the "Other" bit - bit #24 - that is set when one or more of the= following ICR register's bits are set: LSC - bit #2, RXO - bit #6, MDAC - bit #9, SRPD - bit #16, ACK - bit #17, M= NG - bit #18 Log sample of the storm: 27563@1494850819.411877:e1000e_irq_pending_interrupts ICR PENDING: 0x100000= 0 (ICR: 0x815000c2, IMS: 0x1a00004) 27563@1494850819.411900:e1000e_irq_pending_interrupts ICR PENDING: 0x0 (ICR= : 0x815000c2, IMS: 0xa00004) 27563@1494850819.411915:e1000e_irq_pending_interrupts ICR PENDING: 0x0 (ICR= : 0x815000c2, IMS: 0xa00004) 27563@1494850819.412380:e1000e_irq_pending_interrupts ICR PENDING: 0x0 (ICR= : 0x815000c2, IMS: 0xa00004) 27563@1494850819.412395:e1000e_irq_pending_interrupts ICR PENDING: 0x0 (ICR= : 0x815000c2, IMS: 0xa00004) 27563@1494850819.412436:e1000e_irq_pending_interrupts ICR PENDING: 0x0 (ICR= : 0x815000c2, IMS: 0xa00004) 27563@1494850819.412441:e1000e_irq_pending_interrupts ICR PENDING: 0x0 (ICR= : 0x815000c2, IMS: 0xa00004) 27563@1494850819.412998:e1000e_irq_pending_interrupts ICR PENDING: 0x100000= 0 (ICR: 0x815000c2, IMS: 0x1a00004) This commit solves: https://bugzilla.redhat.com/show_bug.cgi?id=3D1447935 https://bugzilla.redhat.com/show_bug.cgi?id=3D1449490 Signed-off-by: Sameeh Jubran Reviewed-by: Dmitry Fleytman Tested-by: Dr. David Alan Gilbert --- hw/net/e1000e_core.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c index 28c5be1..8174b53 100644 --- a/hw/net/e1000e_core.c +++ b/hw/net/e1000e_core.c @@ -2454,14 +2454,17 @@ e1000e_set_ics(E1000ECore *core, int index, uint32_= t val) static void e1000e_set_icr(E1000ECore *core, int index, uint32_t val) { + uint32_t icr =3D 0; if ((core->mac[ICR] & E1000_ICR_ASSERTED) && (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { trace_e1000e_irq_icr_process_iame(); e1000e_clear_ims_bits(core, core->mac[IAM]); } =20 - trace_e1000e_irq_icr_write(val, core->mac[ICR], core->mac[ICR] & ~val); - core->mac[ICR] &=3D ~val; + icr =3D core->mac[ICR] & ~val; + icr =3D (val & E1000_ICR_OTHER) ? (icr & ~E1000_ICR_OTHER_CAUSES) : ic= r; + trace_e1000e_irq_icr_write(val, core->mac[ICR], icr); + core->mac[ICR] =3D icr; e1000e_update_interrupt_state(core); } =20 --=20 2.8.1.185.gdc0db2c