From nobody Fri May 3 15:50:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1494949278924414.7587992632557; Tue, 16 May 2017 08:41:18 -0700 (PDT) Received: from localhost ([::1]:42813 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dAeb5-0003ml-Tb for importer@patchew.org; Tue, 16 May 2017 11:41:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42103) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dAeZP-0002UL-15 for qemu-devel@nongnu.org; Tue, 16 May 2017 11:39:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dAeZL-0001W1-4v for qemu-devel@nongnu.org; Tue, 16 May 2017 11:39:31 -0400 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:33239) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dAeZK-0001Vj-So; Tue, 16 May 2017 11:39:27 -0400 Received: by mail-pg0-x243.google.com with SMTP id s62so21858212pgc.0; Tue, 16 May 2017 08:39:26 -0700 (PDT) Received: from localhost.localdomain ([124.123.70.3]) by smtp.gmail.com with ESMTPSA id d86sm27874895pfj.75.2017.05.16.08.39.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 16 May 2017 08:39:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uVIXKKG3rSIAYq9JHnA59qmlPozqI15rCmuIpRIh8HE=; b=AmNUZ8j0uc+khjwYGmcENZZJQJVxvwkBTgTWMalYGkoQnFHwFe3rYW31r+CpmTpIDK aDaFAkwdY7NYPZlWYhFvj+XcrwXjXNKaPowlyZt4J1LPZfhzZ6T/mNMRBkXjsTxgYAkp T167sq+eS/SaKIjx5i/LZvLoQEvl55c/Dni7y3v2nMuLJPnYAlWX02fC8nnKkREGxGAk o/WDcPdtxDZyDEpxJ20YSLbVzIwKOuRFbE2tvH2NrHhl7Ick6AUmIMk3VBQQjBKq3B2n CPo/0jttu3+D/0TOLD/Q3In1P0jCVi+/2OyZ/7BxOmBUFFlyO+3TBS8yaKu562tHMste TgYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uVIXKKG3rSIAYq9JHnA59qmlPozqI15rCmuIpRIh8HE=; b=KPLTN3audRVXMGfiY1g2DOnLh6ZCfPWInZbwa7vgNg0dnJoa99dGCFcEqESkXiOqhw MplAKgKFMVQgPMeaVcuANzUFyUQ1izdXa+ditEDbOudDU3cBSdzUWaZJR6jTX5QQg2Sr ODal1Yz7Eii+ziYhUD//sYobF5F+d+XPCKkX/lvxK+ICKzgn3tvekELAMzEPJ7eIqCoU Kxw0Q89lCUUwkrt4YsA5GRQvkcZ652U+/D2fBYPo3pJ/P+L0/cLsd5n1kt4mRTLXlAp8 uBmOsGX/umgeI3vSwLAayCJJcjM/zLmU1B+plSuA4KpSmMed23pzrhyBOIt5rrlvjaQg 45Uw== X-Gm-Message-State: AODbwcCnEghpKYANJrLRxoaJvSRLwuXuwI8xRTSVYb0MtkHPYE8K/pQF ERB7WYK9jIqgWg== X-Received: by 10.84.213.2 with SMTP id f2mr16675399pli.22.1494949165521; Tue, 16 May 2017 08:39:25 -0700 (PDT) From: Subbaraya Sundeep To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Tue, 16 May 2017 21:08:49 +0530 Message-Id: <1494949133-2202-2-git-send-email-sundeep.lkml@gmail.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1494949133-2202-1-git-send-email-sundeep.lkml@gmail.com> References: <1494949133-2202-1-git-send-email-sundeep.lkml@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [Qemu devel v5 PATCH 1/5] msf2: Add Smartfusion2 System timer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Subbaraya Sundeep , f4bug@amsat.org, alistair23@gmail.com, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Modelled System Timer in Microsemi's Smartfusion2 Soc. Timer has two 32bit down counters and two interrupts. Signed-off-by: Subbaraya Sundeep --- hw/timer/Makefile.objs | 1 + hw/timer/mss-timer.c | 249 +++++++++++++++++++++++++++++++++++++++= ++++ include/hw/timer/mss-timer.h | 80 ++++++++++++++ 3 files changed, 330 insertions(+) create mode 100644 hw/timer/mss-timer.c create mode 100644 include/hw/timer/mss-timer.h diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs index dd6f27e..fc4d2da 100644 --- a/hw/timer/Makefile.objs +++ b/hw/timer/Makefile.objs @@ -41,3 +41,4 @@ common-obj-$(CONFIG_STM32F2XX_TIMER) +=3D stm32f2xx_timer= .o common-obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_timer.o =20 common-obj-$(CONFIG_SUN4V_RTC) +=3D sun4v-rtc.o +common-obj-$(CONFIG_MSF2) +=3D mss-timer.o diff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c new file mode 100644 index 0000000..7041965 --- /dev/null +++ b/hw/timer/mss-timer.c @@ -0,0 +1,249 @@ +/* + * Block model of System timer present in + * Microsemi's SmartFusion2 and SmartFusion SoCs. + * + * Copyright (c) 2017 Subbaraya Sundeep . + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "hw/timer/mss-timer.h" + +#ifndef MSS_TIMER_ERR_DEBUG +#define MSS_TIMER_ERR_DEBUG 0 +#endif + +#define DB_PRINT_L(lvl, fmt, args...) do { \ + if (MSS_TIMER_ERR_DEBUG >=3D lvl) { \ + qemu_log("%s: " fmt, __func__, ## args); \ + } \ +} while (0); + +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) + +static void timer_update_irq(struct Msf2Timer *st) +{ + bool isr, ier; + + isr =3D !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK); + ier =3D !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR); + + qemu_set_irq(st->irq, (ier && isr)); +} + +static void timer_update(struct Msf2Timer *st) +{ + uint64_t count; + + if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL)) { + ptimer_stop(st->ptimer); + return; + } + + count =3D st->regs[R_TIM_LOADVAL]; + ptimer_set_limit(st->ptimer, count, 1); + ptimer_run(st->ptimer, 1); +} + +static uint64_t +timer_read(void *opaque, hwaddr offset, unsigned int size) +{ + MSSTimerState *t =3D opaque; + hwaddr addr; + struct Msf2Timer *st; + uint32_t ret =3D 0; + int timer =3D 0; + int isr; + int ier; + + addr =3D offset >> 2; + /* + * Two independent timers has same base address. + * Based on address passed figure out which timer is being used. + */ + if ((addr >=3D R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) { + timer =3D 1; + addr -=3D R_TIM1_MAX; + } + + st =3D &t->timers[timer]; + + switch (addr) { + case R_TIM_VAL: + ret =3D ptimer_get_count(st->ptimer); + break; + + case R_TIM_MIS: + isr =3D !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK); + ier =3D !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR); + ret =3D ier & isr; + break; + + default: + if (addr < NUM_TIMERS * R_TIM1_MAX) { + ret =3D st->regs[addr]; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + TYPE_MSS_TIMER": 64-bit mode not supported\n"); + } + break; + } + + DB_PRINT("timer=3D%d 0x%" HWADDR_PRIx "=3D0x%" PRIx32 "\n", timer, off= set, + ret); + return ret; +} + +static void +timer_write(void *opaque, hwaddr offset, + uint64_t val64, unsigned int size) +{ + MSSTimerState *t =3D opaque; + hwaddr addr; + struct Msf2Timer *st; + int timer =3D 0; + uint32_t value =3D val64; + + addr =3D offset >> 2; + /* + * Two independent timers has same base address. + * Based on addr passed figure out which timer is being used. + */ + if ((addr >=3D R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) { + timer =3D 1; + addr -=3D R_TIM1_MAX; + } + + st =3D &t->timers[timer]; + + DB_PRINT("addr=3D0x%" HWADDR_PRIx " val=3D0x%" PRIx32 " (timer=3D%d)\n= ", offset, + value, timer); + + switch (addr) { + case R_TIM_CTRL: + st->regs[R_TIM_CTRL] =3D value; + timer_update(st); + break; + + case R_TIM_RIS: + if (value & TIMER_RIS_ACK) { + st->regs[R_TIM_RIS] &=3D ~TIMER_RIS_ACK; + } + break; + + case R_TIM_LOADVAL: + st->regs[R_TIM_LOADVAL] =3D value; + if (st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL) { + timer_update(st); + } + break; + + case R_TIM_BGLOADVAL: + st->regs[R_TIM_BGLOADVAL] =3D value; + st->regs[R_TIM_LOADVAL] =3D value; + break; + + case R_TIM_VAL: + case R_TIM_MIS: + break; + + default: + if (addr < NUM_TIMERS * R_TIM1_MAX) { + st->regs[addr] =3D value; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + TYPE_MSS_TIMER": 64-bit mode not supported\n"); + return; + } + break; + } + timer_update_irq(st); +} + +static const MemoryRegionOps timer_ops =3D { + .read =3D timer_read, + .write =3D timer_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4 + } +}; + +static void timer_hit(void *opaque) +{ + struct Msf2Timer *st =3D opaque; + + st->regs[R_TIM_RIS] |=3D TIMER_RIS_ACK; + + if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ONESHOT)) { + timer_update(st); + } + timer_update_irq(st); +} + +static void mss_timer_init(Object *obj) +{ + MSSTimerState *t =3D MSS_TIMER(obj); + int i; + + /* Init all the ptimers. */ + t->timers =3D g_malloc0((sizeof t->timers[0]) * NUM_TIMERS); + for (i =3D 0; i < NUM_TIMERS; i++) { + struct Msf2Timer *st =3D &t->timers[i]; + + st->bh =3D qemu_bh_new(timer_hit, st); + st->ptimer =3D ptimer_init(st->bh, PTIMER_POLICY_DEFAULT); + ptimer_set_freq(st->ptimer, t->freq_hz); + sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq); + } + + memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, TYPE_MSS_TIM= ER, + NUM_TIMERS * R_TIM1_MAX * 4); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &t->mmio); +} + +static Property mss_timer_properties[] =3D { + /* Libero GUI shows 100Mhz as default for clocks */ + DEFINE_PROP_UINT32("clock-frequency", MSSTimerState, freq_hz, + 100 * 1000000), + DEFINE_PROP_END_OF_LIST(), +}; + +static void mss_timer_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->props =3D mss_timer_properties; +} + +static const TypeInfo mss_timer_info =3D { + .name =3D TYPE_MSS_TIMER, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(MSSTimerState), + .instance_init =3D mss_timer_init, + .class_init =3D mss_timer_class_init, +}; + +static void mss_timer_register_types(void) +{ + type_register_static(&mss_timer_info); +} + +type_init(mss_timer_register_types) diff --git a/include/hw/timer/mss-timer.h b/include/hw/timer/mss-timer.h new file mode 100644 index 0000000..4caacfd --- /dev/null +++ b/include/hw/timer/mss-timer.h @@ -0,0 +1,80 @@ +/* + * Microsemi SmartFusion2 Timer. + * + * Copyright (c) 2017 Subbaraya Sundeep + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef HW_MSS_TIMER_H +#define HW_MSS_TIMER_H + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/ptimer.h" +#include "sysemu/sysemu.h" +#include "qemu/log.h" + +#define TYPE_MSS_TIMER "mss-timer" +#define MSS_TIMER(obj) OBJECT_CHECK(MSSTimerState, \ + (obj), TYPE_MSS_TIMER) + +/* + * There are two 32-bit down counting timers. + * Timers 1 and 2 can be concatenated into a single 64-bit Timer + * that operates either in Periodic mode or in One-shot mode. + * Writing 1 to the TIM64_MODE register bit 0 sets the Timers in 64-bit mo= de. + * In 64-bit mode, writing to the 32-bit registers has no effect. + * Similarly, in 32-bit mode, writing to the 64-bit mode registers + * has no effect. Only two 32-bit timers are supported currently. + */ +#define NUM_TIMERS 2 + +#define R_TIM_VAL 0 +#define R_TIM_LOADVAL 1 +#define R_TIM_BGLOADVAL 2 +#define R_TIM_CTRL 3 +#define R_TIM_RIS 4 +#define R_TIM_MIS 5 +#define R_TIM1_MAX 6 + +#define TIMER_CTRL_ENBL (1 << 0) +#define TIMER_CTRL_ONESHOT (1 << 1) +#define TIMER_CTRL_INTR (1 << 2) +#define TIMER_RIS_ACK (1 << 0) +#define TIMER_RST_CLR (1 << 6) +#define TIMER_MODE (1 << 0) + +struct Msf2Timer { + QEMUBH *bh; + ptimer_state *ptimer; + + uint32_t regs[NUM_TIMERS * R_TIM1_MAX]; + qemu_irq irq; +}; + +typedef struct MSSTimerState { + SysBusDevice parent_obj; + + MemoryRegion mmio; + uint32_t freq_hz; + struct Msf2Timer *timers; +} MSSTimerState; + +#endif /* HW_MSS_TIMER_H */ --=20 2.5.0 From nobody Fri May 3 15:50:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1494949427739476.28539923646827; Tue, 16 May 2017 08:43:47 -0700 (PDT) Received: from localhost ([::1]:42829 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dAedV-0006Cz-83 for importer@patchew.org; Tue, 16 May 2017 11:43:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42108) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dAeZP-0002UM-Gt for qemu-devel@nongnu.org; Tue, 16 May 2017 11:39:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dAeZN-0001WP-MV for qemu-devel@nongnu.org; Tue, 16 May 2017 11:39:31 -0400 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:34130) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dAeZN-0001WI-EZ; Tue, 16 May 2017 11:39:29 -0400 Received: by mail-pg0-x244.google.com with SMTP id u187so21807687pgb.1; Tue, 16 May 2017 08:39:29 -0700 (PDT) Received: from localhost.localdomain ([124.123.70.3]) by smtp.gmail.com with ESMTPSA id d86sm27874895pfj.75.2017.05.16.08.39.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 16 May 2017 08:39:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ISWA1TqbRyQqQmE6EamIaok0CpLt3yDrkaMBwUYZc+w=; b=NGPXx/qdYdzHPaKSfcHseFsQ9EdFl4Pty4oXZO0yH3UZEPvz/qRH7hR85AYWYvjBXc OWKDlD5P1mmlOS6sd9l7kL6myqR2dhiCP67LiFJhYK2v5N6+udvCUenR/WsJHnzGPBnt X5JCsxjPlFl/mQw0JXZm9CdB6+7W/a0RotbeGWDvlVSMJ35oSdPan+4wBLKixFPYTR/4 BVOi7rVv5nAXt+oaKS+h1N+etch7gVI3ZQYlFxFkwhg2IHzKOTsJwiJpo/ZWcu4DWEpM 7CROkdzvMVU1ZXne2cHFgaAkAeFazHinkPVybK2CE80XKsL+XRy8UmJcRsQCg5crLfhN uYPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ISWA1TqbRyQqQmE6EamIaok0CpLt3yDrkaMBwUYZc+w=; b=nFD9dnmZRjpuYVuuHWulasSKrNxzS0XDrnr2PLxTx5RUGq60ucJaFEdyMovdfA7Kl/ Urjz25HCZ5OmGOWKBVVAU66Bozc5EC/fnaeQvkjMeSFBtR2vA+yqKCBgGWUyyUDFSLtp bfKJwmChQn50fLU71D9EJFls39i68C2xAKpkzZLlei34ia/f+rY7lyz6jDInDn/lXpat oh6XZw7L6iL7Frn8FB8WMNxUUcnW9/Y4HeHBlAmp7/ZOMwJ5+M62RD0QCaTLwBl6VwsG mLReyc4AVlxda6m6H+HBF5mtq9AHHZJPrdcwDbEC5blKcJphoBLPM6QK695IUXlEGI3I NnsA== X-Gm-Message-State: AODbwcC9ZOGT3i0OMp9QNuCNeSEVWBMr4MzNLG9KsYBpeZhc+5ABl/uX HaDBETBA5TnpCw== X-Received: by 10.99.104.136 with SMTP id d130mr13004134pgc.27.1494949168437; Tue, 16 May 2017 08:39:28 -0700 (PDT) From: Subbaraya Sundeep To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Tue, 16 May 2017 21:08:50 +0530 Message-Id: <1494949133-2202-3-git-send-email-sundeep.lkml@gmail.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1494949133-2202-1-git-send-email-sundeep.lkml@gmail.com> References: <1494949133-2202-1-git-send-email-sundeep.lkml@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [Qemu devel v5 PATCH 2/5] msf2: Microsemi Smartfusion2 System Register block. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Subbaraya Sundeep , f4bug@amsat.org, alistair23@gmail.com, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Added Sytem register block of Smartfusion2. This block has PLL registers which are accessed by guest. Signed-off-by: Subbaraya Sundeep --- hw/misc/Makefile.objs | 1 + hw/misc/msf2-sysreg.c | 161 ++++++++++++++++++++++++++++++++++++++= ++++ include/hw/misc/msf2-sysreg.h | 80 +++++++++++++++++++++ 3 files changed, 242 insertions(+) create mode 100644 hw/misc/msf2-sysreg.c create mode 100644 include/hw/misc/msf2-sysreg.h diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index c8b4893..0f52354 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -56,3 +56,4 @@ obj-$(CONFIG_EDU) +=3D edu.o obj-$(CONFIG_HYPERV_TESTDEV) +=3D hyperv_testdev.o obj-$(CONFIG_AUX) +=3D auxbus.o obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_scu.o aspeed_sdmc.o +obj-$(CONFIG_MSF2) +=3D msf2-sysreg.o diff --git a/hw/misc/msf2-sysreg.c b/hw/misc/msf2-sysreg.c new file mode 100644 index 0000000..8d3118f --- /dev/null +++ b/hw/misc/msf2-sysreg.c @@ -0,0 +1,161 @@ +/* + * System Register block model of Microsemi SmartFusion2. + * + * Copyright (c) 2017 Subbaraya Sundeep + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "hw/misc/msf2-sysreg.h" + +#ifndef MSF2_SYSREG_ERR_DEBUG +#define MSF2_SYSREG_ERR_DEBUG 0 +#endif + +#define DB_PRINT_L(lvl, fmt, args...) do { \ + if (MSF2_SYSREG_ERR_DEBUG >=3D lvl) { \ + qemu_log("%s: " fmt, __func__, ## args); \ + } \ +} while (0); + +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) + +static void msf2_sysreg_reset(DeviceState *d) +{ + MSF2SysregState *s =3D MSF2_SYSREG(d); + + DB_PRINT("RESET\n"); + + s->regs[MSSDDR_PLL_STATUS_LOW_CR] =3D 0x021A2358; + s->regs[MSSDDR_FACC1_CR] =3D 0x0B800124; + s->regs[MSSDDR_PLL_STATUS] =3D 0x3; +} + +static uint64_t msf2_sysreg_read(void *opaque, hwaddr offset, + unsigned size) +{ + MSF2SysregState *s =3D opaque; + offset /=3D 4; + uint32_t ret =3D 0; + + if (offset < ARRAY_SIZE(s->regs)) { + ret =3D s->regs[offset]; + DB_PRINT("addr: 0x%08" HWADDR_PRIx " data: 0x%08" PRIx32 "\n", + offset * 4, ret); + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%08" HWADDR_PRIx "\n", __func__, + offset * 4); + } + + return ret; +} + +static void msf2_sysreg_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + MSF2SysregState *s =3D (MSF2SysregState *)opaque; + uint32_t newval =3D val; + uint32_t oldval; + + offset /=3D 4; + + DB_PRINT("addr: 0x%08" HWADDR_PRIx " data: 0x%08" PRIx64 "\n", + offset * 4, val); + + switch (offset) { + case MSSDDR_PLL_STATUS: + break; + + case ESRAM_CR: + oldval =3D s->regs[ESRAM_CR]; + if (oldval ^ newval) { + qemu_log_mask(LOG_GUEST_ERROR, + TYPE_MSF2_SYSREG": eSRAM remapping not supported\n"= ); + abort(); + } + break; + + case DDR_CR: + oldval =3D s->regs[DDR_CR]; + if (oldval ^ newval) { + qemu_log_mask(LOG_GUEST_ERROR, + TYPE_MSF2_SYSREG": DDR remapping not supported\n"); + abort(); + } + break; + + case ENVM_REMAP_BASE_CR: + oldval =3D s->regs[ENVM_REMAP_BASE_CR]; + if (oldval ^ newval) { + qemu_log_mask(LOG_GUEST_ERROR, + TYPE_MSF2_SYSREG": eNVM remapping not supported\n"); + abort(); + } + break; + + default: + if (offset < ARRAY_SIZE(s->regs)) { + s->regs[offset] =3D val; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%08" HWADDR_PRIx "\n", __func__, + offset * 4); + } + break; + } +} + +static const MemoryRegionOps sysreg_ops =3D { + .read =3D msf2_sysreg_read, + .write =3D msf2_sysreg_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; + +static void msf2_sysreg_init(Object *obj) +{ + MSF2SysregState *s =3D MSF2_SYSREG(obj); + + memory_region_init_io(&s->iomem, obj, &sysreg_ops, s, TYPE_MSF2_SYSREG, + MSF2_SYSREG_MMIO_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); +} + +static const VMStateDescription vmstate_msf2_sysreg =3D { + .name =3D TYPE_MSF2_SYSREG, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, MSF2SysregState, MSF2_SYSREG_NUM_REGS), + VMSTATE_END_OF_LIST() + } +}; + +static void msf2_sysreg_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->vmsd =3D &vmstate_msf2_sysreg; + dc->reset =3D msf2_sysreg_reset; +} + +static const TypeInfo msf2_sysreg_info =3D { + .name =3D TYPE_MSF2_SYSREG, + .parent =3D TYPE_SYS_BUS_DEVICE, + .class_init =3D msf2_sysreg_class_init, + .instance_size =3D sizeof(MSF2SysregState), + .instance_init =3D msf2_sysreg_init, +}; + +static void msf2_sysreg_register_types(void) +{ + type_register_static(&msf2_sysreg_info); +} + +type_init(msf2_sysreg_register_types) diff --git a/include/hw/misc/msf2-sysreg.h b/include/hw/misc/msf2-sysreg.h new file mode 100644 index 0000000..a485ed6 --- /dev/null +++ b/include/hw/misc/msf2-sysreg.h @@ -0,0 +1,80 @@ +/* + * Microsemi SmartFusion2 SYSREG + * + * Copyright (c) 2017 Subbaraya Sundeep + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef HW_MSF2_SYSREG_H +#define HW_MSF2_SYSREG_H + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/hw.h" +#include "sysemu/sysemu.h" +#include "qemu/log.h" + +enum { + ESRAM_CR =3D 0x00 / 4, + ESRAM_MAX_LAT, + DDR_CR, + ENVM_CR, + ENVM_REMAP_BASE_CR, + ENVM_REMAP_FAB_CR, + CC_CR, + CC_REGION_CR, + CC_LOCK_BASE_ADDR_CR, + CC_FLUSH_INDX_CR, + DDRB_BUF_TIMER_CR, + DDRB_NB_ADDR_CR, + DDRB_NB_SIZE_CR, + DDRB_CR, + + SOFT_RESET_CR =3D 0x48 / 4, + M3_CR, + + GPIO_SYSRESET_SEL_CR =3D 0x58 / 4, + + MDDR_CR =3D 0x60 / 4, + + MSSDDR_PLL_STATUS_LOW_CR =3D 0x90 / 4, + MSSDDR_PLL_STATUS_HIGH_CR, + MSSDDR_FACC1_CR, + MSSDDR_FACC2_CR, + + MSSDDR_PLL_STATUS =3D 0x150 / 4, + +}; + +#define MSF2_SYSREG_MMIO_SIZE 0x300 +#define MSF2_SYSREG_NUM_REGS (MSF2_SYSREG_MMIO_SIZE / 4) + +#define TYPE_MSF2_SYSREG "msf2-sysreg" +#define MSF2_SYSREG(obj) OBJECT_CHECK(MSF2SysregState, (obj), TYPE_MSF2_S= YSREG) + +typedef struct MSF2SysregState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + + uint32_t regs[MSF2_SYSREG_NUM_REGS]; +} MSF2SysregState; + +#endif /* HW_MSF2_SYSREG_H */ --=20 2.5.0 From nobody Fri May 3 15:50:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1494949433172468.79314726342716; Tue, 16 May 2017 08:43:53 -0700 (PDT) Received: from localhost ([::1]:42830 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dAedb-0006I3-GW for importer@patchew.org; Tue, 16 May 2017 11:43:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42163) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dAeZT-0002Vt-3W for qemu-devel@nongnu.org; Tue, 16 May 2017 11:39:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dAeZR-0001Xr-12 for qemu-devel@nongnu.org; Tue, 16 May 2017 11:39:35 -0400 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:34849) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dAeZQ-0001XI-OW; Tue, 16 May 2017 11:39:32 -0400 Received: by mail-pf0-x242.google.com with SMTP id u26so20334860pfd.2; Tue, 16 May 2017 08:39:32 -0700 (PDT) Received: from localhost.localdomain ([124.123.70.3]) by smtp.gmail.com with ESMTPSA id d86sm27874895pfj.75.2017.05.16.08.39.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 16 May 2017 08:39:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=t9FCvCns8yhFbFyNsCLXQw03HcRRoEgmfPGNPbbk1Xo=; b=ZqaIHWI4HMxStVXXOGsCsHqA5l7H17LT5V0AuXxJuocTbZ6anGtUQ1PH/MhjpZvNrK S27sFRbOUkQB0PI8gZ8N3X/BmR23oM5l7DI0/4UIEc/ueOoAzyEAdtM+FVd9ZtrP7IKN MxmVyb1OrdWNaA09UMy/62PaWN49wDC0oqemHiBvWqk0qw0MWIi01HVxjAVtXL3h5pdC A2MQ7bIYS+5O9lsAOIhjkI4Wm0dO+RMaLFgvSMh15HTnbAuauACOXq0ky6Bs7alyB4nS bm2JNRqlma7t2I1kPznIZCP3InzrDcpltHzfH0pe8Ehnd2l/itoL2MxtEUKdRNCJ7xIp DEUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=t9FCvCns8yhFbFyNsCLXQw03HcRRoEgmfPGNPbbk1Xo=; b=depRReHgLxZOqMy7apOqN9Y1tkFouqEE/jTVcmp64GhBINliAzM44fgc/x0ExqDLyL orcthSB0OPKr7TIMMBWbBkOQwfYmGR5zjapikDW4tp/URs3it6KsbGy1RMuKooyT90fA RolXiq39yVeephSVXhFj/RuKF+aHPJaHhx4PB2YQlg130EbAFj9T9VvfcR1OKGP7O7hj FbgLqIoHnV4q/CB2vLLskqrVxgJN/+5DfG1MEAGAZ1ZZwcws6If7ZS9cTWtTYvp1VQld r9YT1L9QWCHDLUVxs8Tl2w50oaXfxC/L5uYFbvBu5mq79zq06BxuVxVOFaqcqp7kbdM7 7qrA== X-Gm-Message-State: AODbwcByC+fI3GUGQFdZKP8rqVhC4if6bsWwhhJvys3Q/I8kYY79NLEI pK14dWVufKTSunhj X-Received: by 10.99.141.76 with SMTP id z73mr12837427pgd.118.1494949171298; Tue, 16 May 2017 08:39:31 -0700 (PDT) From: Subbaraya Sundeep To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Tue, 16 May 2017 21:08:51 +0530 Message-Id: <1494949133-2202-4-git-send-email-sundeep.lkml@gmail.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1494949133-2202-1-git-send-email-sundeep.lkml@gmail.com> References: <1494949133-2202-1-git-send-email-sundeep.lkml@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [Qemu devel v5 PATCH 3/5] msf2: Add Smartfusion2 SPI controller X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Subbaraya Sundeep , f4bug@amsat.org, alistair23@gmail.com, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Modelled Microsemi's Smartfusion2 SPI controller. Signed-off-by: Subbaraya Sundeep --- hw/ssi/Makefile.objs | 1 + hw/ssi/mss-spi.c | 378 +++++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/ssi/mss-spi.h | 104 +++++++++++++ 3 files changed, 483 insertions(+) create mode 100644 hw/ssi/mss-spi.c create mode 100644 include/hw/ssi/mss-spi.h diff --git a/hw/ssi/Makefile.objs b/hw/ssi/Makefile.objs index 487add2..f5bcc65 100644 --- a/hw/ssi/Makefile.objs +++ b/hw/ssi/Makefile.objs @@ -4,6 +4,7 @@ common-obj-$(CONFIG_XILINX_SPI) +=3D xilinx_spi.o common-obj-$(CONFIG_XILINX_SPIPS) +=3D xilinx_spips.o common-obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_smc.o common-obj-$(CONFIG_STM32F2XX_SPI) +=3D stm32f2xx_spi.o +common-obj-$(CONFIG_MSF2) +=3D mss-spi.o =20 obj-$(CONFIG_OMAP) +=3D omap_spi.o obj-$(CONFIG_IMX) +=3D imx_spi.o diff --git a/hw/ssi/mss-spi.c b/hw/ssi/mss-spi.c new file mode 100644 index 0000000..0b88ec9 --- /dev/null +++ b/hw/ssi/mss-spi.c @@ -0,0 +1,378 @@ +/* + * Block model of SPI controller present in + * Microsemi's SmartFusion2 and SmartFusion SoCs. + * + * Copyright (C) 2017 Subbaraya Sundeep + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "hw/ssi/mss-spi.h" + +#ifndef MSS_SPI_ERR_DEBUG +#define MSS_SPI_ERR_DEBUG 0 +#endif + +#define DB_PRINT_L(lvl, fmt, args...) do { \ + if (MSS_SPI_ERR_DEBUG >=3D lvl) { \ + qemu_log("%s: " fmt, __func__, ## args); \ + } \ +} while (0); + +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) + +static void txfifo_reset(MSSSpiState *s) +{ + fifo32_reset(&s->tx_fifo); + + s->regs[R_SPI_STATUS] &=3D ~S_TXFIFOFUL; + s->regs[R_SPI_STATUS] |=3D S_TXFIFOEMP; +} + +static void rxfifo_reset(MSSSpiState *s) +{ + fifo32_reset(&s->rx_fifo); + + s->regs[R_SPI_STATUS] &=3D ~S_RXFIFOFUL; + s->regs[R_SPI_STATUS] |=3D S_RXFIFOEMP; +} + +static void set_fifodepth(MSSSpiState *s) +{ + int size =3D s->regs[R_SPI_DFSIZE] & FRAMESZ_MASK; + + if (0 <=3D size && size <=3D 8) { + s->fifo_depth =3D 32; + } + if (9 <=3D size && size <=3D 16) { + s->fifo_depth =3D 16; + } + if (17 <=3D size && size <=3D 32) { + s->fifo_depth =3D 8; + } +} + +static void mss_spi_do_reset(MSSSpiState *s) +{ + memset(s->regs, 0, sizeof s->regs); + s->regs[R_SPI_CONTROL] =3D 0x80000102; + s->regs[R_SPI_DFSIZE] =3D 0x4; + s->regs[R_SPI_STATUS] =3D 0x2440; + s->regs[R_SPI_CLKGEN] =3D 0x7; + s->regs[R_SPI_RIS] =3D 0x0; + + s->fifo_depth =3D 4; + s->frame_count =3D 1; + s->enabled =3D false; + + rxfifo_reset(s); + txfifo_reset(s); +} + +static void update_mis(MSSSpiState *s) +{ + uint32_t reg =3D s->regs[R_SPI_CONTROL]; + uint32_t tmp; + + /* + * form the Control register interrupt enable bits + * same as RIS, MIS and Interrupt clear registers for simplicity + */ + tmp =3D ((reg & C_INTRXOVRFLO) >> 4) | ((reg & C_INTRXDATA) >> 3) | + ((reg & C_INTTXDATA) >> 5); + s->regs[R_SPI_MIS] |=3D tmp & s->regs[R_SPI_RIS]; +} + +static void spi_update_irq(MSSSpiState *s) +{ + int irq; + + update_mis(s); + irq =3D !!(s->regs[R_SPI_MIS]); + + qemu_set_irq(s->irq, irq); +} + +static void mss_spi_reset(DeviceState *d) +{ + mss_spi_do_reset(MSS_SPI(d)); +} + +static uint64_t +spi_read(void *opaque, hwaddr addr, unsigned int size) +{ + MSSSpiState *s =3D opaque; + uint32_t ret =3D 0; + + addr >>=3D 2; + switch (addr) { + case R_SPI_RX: + s->regs[R_SPI_STATUS] &=3D ~S_RXFIFOFUL; + s->regs[R_SPI_STATUS] &=3D ~RXCHOVRF; + ret =3D fifo32_pop(&s->rx_fifo); + if (fifo32_is_empty(&s->rx_fifo)) { + s->regs[R_SPI_STATUS] |=3D S_RXFIFOEMP; + } + break; + + case R_SPI_MIS: + update_mis(s); + ret =3D s->regs[R_SPI_MIS]; + break; + + default: + if (addr < ARRAY_SIZE(s->regs)) { + ret =3D s->regs[addr]; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, + addr * 4); + } + break; + } + + DB_PRINT("addr=3D0x%" HWADDR_PRIx " =3D 0x%" PRIx32 "\n", addr * 4, re= t); + spi_update_irq(s); + return ret; +} + +static void assert_cs(MSSSpiState *s) +{ + qemu_set_irq(s->cs_line, 0); +} + +static void deassert_cs(MSSSpiState *s) +{ + qemu_set_irq(s->cs_line, 1); +} + +static void spi_flush_txfifo(MSSSpiState *s) +{ + uint32_t tx; + uint32_t rx; + bool sps =3D !!(s->regs[R_SPI_CONTROL] & C_SPS); + + /* + * Chip Select(CS) is automatically controlled by this controller. + * If SPS bit is set in Control register then CS is asserted + * until all the frames set in frame count of Control register are + * transferred. If SPS is not set then CS pulses between frames. + * Note that Slave Select register specifies which of the CS line + * has to be controlled automatically by controller. Bits SS[7:1] are = for + * masters in FPGA fabric since we model only Microcontroller subsystem + * of Smartfusion2 we control only one CS(SS[0]) line. + */ + while (!fifo32_is_empty(&s->tx_fifo) && s->frame_count) { + assert_cs(s); + + s->regs[R_SPI_STATUS] &=3D ~TXDONE; + s->regs[R_SPI_STATUS] &=3D ~RXRDY; + + tx =3D fifo32_pop(&s->tx_fifo); + DB_PRINT("data tx:0x%" PRIx32 "\n", tx); + rx =3D ssi_transfer(s->spi, tx); + DB_PRINT("data rx:0x%" PRIx32 "\n", rx); + + if (fifo32_num_used(&s->rx_fifo) =3D=3D s->fifo_depth) { + s->regs[R_SPI_STATUS] |=3D RXCHOVRF; + s->regs[R_SPI_RIS] |=3D RXCHOVRF; + } else { + fifo32_push(&s->rx_fifo, rx); + s->regs[R_SPI_STATUS] &=3D ~S_RXFIFOEMP; + if (fifo32_num_used(&s->rx_fifo) =3D=3D (s->fifo_depth - 1)) { + s->regs[R_SPI_STATUS] |=3D S_RXFIFOFULNXT; + } + if (fifo32_num_used(&s->rx_fifo) =3D=3D s->fifo_depth) { + s->regs[R_SPI_STATUS] |=3D S_RXFIFOFUL; + } + } + s->frame_count--; + if (!sps) { + deassert_cs(s); + assert_cs(s); + } + } + + if (!sps) { + deassert_cs(s); + } + + if (!s->frame_count) { + s->frame_count =3D (s->regs[R_SPI_CONTROL] & FMCOUNT_MASK) >> + FMCOUNT_SHIFT; + if (sps) { + deassert_cs(s); + } + s->regs[R_SPI_RIS] |=3D TXDONE; + s->regs[R_SPI_RIS] |=3D RXRDY; + s->regs[R_SPI_STATUS] |=3D TXDONE; + s->regs[R_SPI_STATUS] |=3D RXRDY; + } +} + +static void spi_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + MSSSpiState *s =3D opaque; + uint32_t value =3D val64; + + DB_PRINT("addr=3D0x%" HWADDR_PRIx " =3D0x%" PRIx32 "\n", addr, value); + addr >>=3D 2; + + switch (addr) { + case R_SPI_TX: + /* adding to already full FIFO */ + if (fifo32_num_used(&s->tx_fifo) =3D=3D s->fifo_depth) { + break; + } + s->regs[R_SPI_STATUS] &=3D ~S_TXFIFOEMP; + fifo32_push(&s->tx_fifo, value); + if (fifo32_num_used(&s->tx_fifo) =3D=3D (s->fifo_depth - 1)) { + s->regs[R_SPI_STATUS] |=3D S_TXFIFOFULNXT; + } + if (fifo32_num_used(&s->tx_fifo) =3D=3D s->fifo_depth) { + s->regs[R_SPI_STATUS] |=3D S_TXFIFOFUL; + } + if (s->enabled) { + spi_flush_txfifo(s); + } + break; + + case R_SPI_CONTROL: + s->regs[R_SPI_CONTROL] =3D value; + if (value & C_BIGFIFO) { + set_fifodepth(s); + } else { + s->fifo_depth =3D 4; + } + if (value & C_ENABLE) { + s->enabled =3D true; + } else { + s->enabled =3D false; + } + s->frame_count =3D (value & FMCOUNT_MASK) >> FMCOUNT_SHIFT; + if (value & C_RESET) { + mss_spi_do_reset(s); + } + break; + + case R_SPI_DFSIZE: + if (s->enabled) { + break; + } + s->regs[R_SPI_DFSIZE] =3D value; + break; + + case R_SPI_INTCLR: + s->regs[R_SPI_INTCLR] =3D value; + if (value & TXDONE) { + s->regs[R_SPI_RIS] &=3D ~TXDONE; + } + if (value & RXRDY) { + s->regs[R_SPI_RIS] &=3D ~RXRDY; + } + if (value & RXCHOVRF) { + s->regs[R_SPI_RIS] &=3D ~RXCHOVRF; + } + break; + + case R_SPI_MIS: + case R_SPI_STATUS: + case R_SPI_RIS: + break; + + default: + if (addr < ARRAY_SIZE(s->regs)) { + s->regs[addr] =3D value; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, + addr * 4); + } + break; + } + + spi_update_irq(s); +} + +static const MemoryRegionOps spi_ops =3D { + .read =3D spi_read, + .write =3D spi_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4 + } +}; + +static void mss_spi_realize(DeviceState *dev, Error **errp) +{ + MSSSpiState *s =3D MSS_SPI(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + + DB_PRINT("\n"); + + s->spi =3D ssi_create_bus(dev, "spi0"); + + sysbus_init_irq(sbd, &s->irq); + ssi_auto_connect_slaves(dev, &s->cs_line, s->spi); + sysbus_init_irq(sbd, &s->cs_line); + + memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s, + TYPE_MSS_SPI, R_SPI_MAX * 4); + sysbus_init_mmio(sbd, &s->mmio); + + fifo32_create(&s->tx_fifo, FIFO_CAPACITY); + fifo32_create(&s->rx_fifo, FIFO_CAPACITY); +} + +static const VMStateDescription vmstate_mss_spi =3D { + .name =3D TYPE_MSS_SPI, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_FIFO32(tx_fifo, MSSSpiState), + VMSTATE_FIFO32(rx_fifo, MSSSpiState), + VMSTATE_UINT32_ARRAY(regs, MSSSpiState, R_SPI_MAX), + VMSTATE_END_OF_LIST() + } +}; + +static void mss_spi_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D mss_spi_realize; + dc->reset =3D mss_spi_reset; + dc->vmsd =3D &vmstate_mss_spi; +} + +static const TypeInfo mss_spi_info =3D { + .name =3D TYPE_MSS_SPI, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(MSSSpiState), + .class_init =3D mss_spi_class_init, +}; + +static void mss_spi_register_types(void) +{ + type_register_static(&mss_spi_info); +} + +type_init(mss_spi_register_types) diff --git a/include/hw/ssi/mss-spi.h b/include/hw/ssi/mss-spi.h new file mode 100644 index 0000000..091307a --- /dev/null +++ b/include/hw/ssi/mss-spi.h @@ -0,0 +1,104 @@ +/* + * Microsemi SmartFusion2 SPI + * + * Copyright (c) 2017 Subbaraya Sundeep + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef HW_MSS_SPI_H +#define HW_MSS_SPI_H + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/hw.h" +#include "hw/ssi/ssi.h" +#include "qemu/fifo32.h" +#include "sysemu/sysemu.h" +#include "qemu/log.h" + +#define FIFO_CAPACITY 32 +#define FIFO_CAPACITY 32 + +#define R_SPI_CONTROL 0 +#define R_SPI_DFSIZE 1 +#define R_SPI_STATUS 2 +#define R_SPI_INTCLR 3 +#define R_SPI_RX 4 +#define R_SPI_TX 5 +#define R_SPI_CLKGEN 6 +#define R_SPI_SS 7 +#define R_SPI_MIS 8 +#define R_SPI_RIS 9 +#define R_SPI_MAX 16 + +#define S_RXFIFOFUL (1 << 4) +#define S_RXFIFOFULNXT (1 << 5) +#define S_RXFIFOEMP (1 << 6) +#define S_RXFIFOEMPNXT (1 << 7) +#define S_TXFIFOFUL (1 << 8) +#define S_TXFIFOFULNXT (1 << 9) +#define S_TXFIFOEMP (1 << 10) +#define S_TXFIFOEMPNXT (1 << 11) +#define S_FRAMESTART (1 << 12) +#define S_SSEL (1 << 13) +#define S_ACTIVE (1 << 14) + +#define C_ENABLE (1 << 0) +#define C_MODE (1 << 1) +#define C_INTRXDATA (1 << 4) +#define C_INTTXDATA (1 << 5) +#define C_INTRXOVRFLO (1 << 6) +#define C_SPS (1 << 26) +#define C_BIGFIFO (1 << 29) +#define C_RESET (1 << 31) + +#define FRAMESZ_MASK 0x1F +#define FMCOUNT_MASK 0x00FFFF00 +#define FMCOUNT_SHIFT 8 + +#define TXDONE (1 << 0) +#define RXRDY (1 << 1) +#define RXCHOVRF (1 << 2) + +#define TYPE_MSS_SPI "mss-spi" +#define MSS_SPI(obj) OBJECT_CHECK(MSSSpiState, (obj), TYPE_MSS_SPI) + +typedef struct MSSSpiState { + SysBusDevice parent_obj; + + MemoryRegion mmio; + + qemu_irq irq; + + qemu_irq cs_line; + + SSIBus *spi; + + Fifo32 rx_fifo; + Fifo32 tx_fifo; + + int fifo_depth; + uint32_t frame_count; + bool enabled; + + uint32_t regs[R_SPI_MAX]; +} MSSSpiState; + +#endif /* HW_MSS_SPI_H */ --=20 2.5.0 From nobody Fri May 3 15:50:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1494949556932470.50571478567235; Tue, 16 May 2017 08:45:56 -0700 (PDT) Received: from localhost ([::1]:42846 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dAefa-0008AG-Jo for importer@patchew.org; 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Tue, 16 May 2017 08:39:34 -0700 (PDT) From: Subbaraya Sundeep To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Tue, 16 May 2017 21:08:52 +0530 Message-Id: <1494949133-2202-5-git-send-email-sundeep.lkml@gmail.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1494949133-2202-1-git-send-email-sundeep.lkml@gmail.com> References: <1494949133-2202-1-git-send-email-sundeep.lkml@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [Qemu devel v5 PATCH 4/5] msf2: Add Smartfusion2 SoC. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Subbaraya Sundeep , f4bug@amsat.org, alistair23@gmail.com, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Smartfusion2 SoC has hardened Microcontroller subsystem and flash based FPGA fabric. This patch adds support for Microcontroller subsystem in the SoC. Signed-off-by: Subbaraya Sundeep --- default-configs/arm-softmmu.mak | 1 + hw/arm/Makefile.objs | 1 + hw/arm/msf2-soc.c | 201 ++++++++++++++++++++++++++++++++++++= ++++ include/hw/arm/msf2-soc.h | 69 ++++++++++++++ 4 files changed, 272 insertions(+) create mode 100644 hw/arm/msf2-soc.c create mode 100644 include/hw/arm/msf2-soc.h diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.= mak index 78d7af0..7062512 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -122,3 +122,4 @@ CONFIG_ACPI=3Dy CONFIG_SMBIOS=3Dy CONFIG_ASPEED_SOC=3Dy CONFIG_GPIO_KEY=3Dy +CONFIG_MSF2=3Dy diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index 4c5c4ee..c828061 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -18,3 +18,4 @@ obj-$(CONFIG_FSL_IMX25) +=3D fsl-imx25.o imx25_pdk.o obj-$(CONFIG_FSL_IMX31) +=3D fsl-imx31.o kzm.o obj-$(CONFIG_FSL_IMX6) +=3D fsl-imx6.o sabrelite.o obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_soc.o aspeed.o +obj-$(CONFIG_MSF2) +=3D msf2-soc.o diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c new file mode 100644 index 0000000..329e30c --- /dev/null +++ b/hw/arm/msf2-soc.c @@ -0,0 +1,201 @@ +/* + * SmartFusion2 SoC emulation. + * + * Copyright (c) 2017 Subbaraya Sundeep + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu-common.h" +#include "hw/arm/arm.h" +#include "exec/address-spaces.h" +#include "hw/char/serial.h" +#include "hw/boards.h" +#include "sysemu/block-backend.h" +#include "hw/arm/msf2-soc.h" + +#define MSF2_TIMER_BASE 0x40004000 +#define MSF2_SYSREG_BASE 0x40038000 + +#define MSF2_TIMER_IRQ0 14 +#define MSF2_TIMER_IRQ1 15 + +static const uint32_t spi_addr[MSF2_NUM_SPIS] =3D { 0x40001000 , 0x4001100= 0 }; +static const uint32_t uart_addr[MSF2_NUM_UARTS] =3D { 0x40000000 , 0x40010= 000 }; + +static const int spi_irq[MSF2_NUM_SPIS] =3D { 2, 3 }; +static const int uart_irq[MSF2_NUM_UARTS] =3D { 10, 11 }; + +static void m2sxxx_soc_initfn(Object *obj) +{ + MSF2State *s =3D MSF2_SOC(obj); + int i; + + object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M); + qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default()); + + object_initialize(&s->sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG); + qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default()); + + object_initialize(&s->timer, sizeof(s->timer), TYPE_MSS_TIMER); + qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default()); + + for (i =3D 0; i < MSF2_NUM_SPIS; i++) { + object_initialize(&s->spi[i], sizeof(s->spi[i]), + TYPE_MSS_SPI); + qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); + } +} + +static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp) +{ + MSF2State *s =3D MSF2_SOC(dev_soc); + DeviceState *dev, *armv7m; + SysBusDevice *busdev; + Error *err =3D NULL; + int i; + + MemoryRegion *system_memory =3D get_system_memory(); + MemoryRegion *nvm =3D g_new(MemoryRegion, 1); + MemoryRegion *nvm_alias =3D g_new(MemoryRegion, 1); + MemoryRegion *sram =3D g_new(MemoryRegion, 1); + + memory_region_init_ram(nvm, NULL, "MSF2.eNVM", s->envm_size, + &error_fatal); + + /* + * On power-on, the eNVM region 0x60000000 is automatically + * remapped to the Cortex-M3 processor executable region + * start address (0x0). We do not support remapping other eNVM, + * eSRAM and DDR regions by guest(via Sysreg) currently. + */ + memory_region_init_alias(nvm_alias, NULL, "MSF2.eNVM.alias", + nvm, 0, s->envm_size); + vmstate_register_ram_global(nvm); + + memory_region_set_readonly(nvm, true); + memory_region_set_readonly(nvm_alias, true); + + memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm); + memory_region_add_subregion(system_memory, 0, nvm_alias); + + memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size, + &error_fatal); + vmstate_register_ram_global(sram); + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram); + + armv7m =3D DEVICE(&s->armv7m); + qdev_prop_set_uint32(armv7m, "num-irq", 81); + qdev_prop_set_string(armv7m, "cpu-model", "cortex-m3"); + object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory(= )), + "memory", &error_abort); + object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err); + if (err !=3D NULL) { + error_propagate(errp, err); + return; + } + + for (i =3D 0; i < MSF2_NUM_UARTS; i++) { + if (serial_hds[i]) { + serial_mm_init(get_system_memory(), uart_addr[i], 2, + qdev_get_gpio_in(armv7m, uart_irq[i]), + 115200, serial_hds[i], DEVICE_NATIVE_ENDIAN); + } + } + + dev =3D DEVICE(&s->timer); + /* pclk0 is the timer input clock */ + qdev_prop_set_uint32(dev, "clock-frequency", s->pclk0); + object_property_set_bool(OBJECT(&s->timer), true, "realized", &err); + if (err !=3D NULL) { + error_propagate(errp, err); + return; + } + busdev =3D SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE); + sysbus_connect_irq(busdev, 0, + qdev_get_gpio_in(armv7m, MSF2_TIMER_IRQ0)); + sysbus_connect_irq(busdev, 1, + qdev_get_gpio_in(armv7m, MSF2_TIMER_IRQ1)); + + dev =3D DEVICE(&s->sysreg); + object_property_set_bool(OBJECT(&s->sysreg), true, "realized", &err); + if (err !=3D NULL) { + error_propagate(errp, err); + return; + } + busdev =3D SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE); + + for (i =3D 0; i < MSF2_NUM_SPIS; i++) { + gchar *bus_name =3D g_strdup_printf("spi%d", i); + + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &er= r); + if (err !=3D NULL) { + g_free(bus_name); + error_propagate(errp, err); + return; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, + qdev_get_gpio_in(armv7m, spi_irq[i])); + + /* Alias controller SPI bus to the SoC itself */ + object_property_add_alias(OBJECT(s), bus_name, + OBJECT(&s->spi[i]), "spi0", + &error_abort); + g_free(bus_name); + } +} + +static Property m2sxxx_soc_properties[] =3D { + DEFINE_PROP_STRING("part-name", MSF2State, part_name), + DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_SIZE), + DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size, MSF2_ESRAM_SIZ= E), + /* Libero GUI shows 100Mhz as default for clocks */ + DEFINE_PROP_UINT32("pclk0", MSF2State, pclk0, 100 * 1000000), + DEFINE_PROP_UINT32("pclk1", MSF2State, pclk1, 100 * 1000000), + DEFINE_PROP_END_OF_LIST(), +}; + +static void m2sxxx_soc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D m2sxxx_soc_realize; + dc->props =3D m2sxxx_soc_properties; +} + +static const TypeInfo m2sxxx_soc_info =3D { + .name =3D TYPE_MSF2_SOC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(MSF2State), + .instance_init =3D m2sxxx_soc_initfn, + .class_init =3D m2sxxx_soc_class_init, +}; + +static void m2sxxx_soc_types(void) +{ + type_register_static(&m2sxxx_soc_info); +} + +type_init(m2sxxx_soc_types) diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h new file mode 100644 index 0000000..67adddb --- /dev/null +++ b/include/hw/arm/msf2-soc.h @@ -0,0 +1,69 @@ +/* + * Microsemi Smartfusion2 SoC + * + * Copyright (c) 2017 Subbaraya Sundeep + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef HW_ARM_MSF2_SOC_H +#define HW_ARM_MSF2_SOC_H + +#include "hw/misc/msf2-sysreg.h" +#include "hw/timer/mss-timer.h" +#include "hw/ssi/mss-spi.h" +#include "hw/arm/armv7m.h" +#include "qemu/cutils.h" + +#define TYPE_MSF2_SOC "msf2-soc" +#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC) + +#define MSF2_NUM_SPIS 2 +#define MSF2_NUM_UARTS 2 + +#define ENVM_BASE_ADDRESS 0x60000000 + +#define SRAM_BASE_ADDRESS 0x20000000 + +#define MSF2_ENVM_SIZE (512 * K_BYTE) +#define MSF2_ESRAM_SIZE (64 * K_BYTE) + +#define M2S010_ENVM_SIZE (256 * K_BYTE) +#define M2S010_ESRAM_SIZE (64 * K_BYTE) + +typedef struct MSF2State { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + ARMv7MState armv7m; + + char *part_name; + uint64_t envm_size; + uint64_t esram_size; + + uint32_t pclk0; + uint32_t pclk1; + + MSF2SysregState sysreg; + MSSTimerState timer; + MSSSpiState spi[MSF2_NUM_SPIS]; +} MSF2State; + +#endif --=20 2.5.0 From nobody Fri May 3 15:50:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 14949492945143.7645147270402504; Tue, 16 May 2017 08:41:34 -0700 (PDT) Received: from localhost ([::1]:42815 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dAebL-00040g-Rj for importer@patchew.org; Tue, 16 May 2017 11:41:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42264) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dAeZZ-0002ch-AT for qemu-devel@nongnu.org; Tue, 16 May 2017 11:39:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dAeZW-0001bu-5Y for qemu-devel@nongnu.org; Tue, 16 May 2017 11:39:41 -0400 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:35585) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dAeZV-0001bB-U1; Tue, 16 May 2017 11:39:38 -0400 Received: by mail-pg0-x243.google.com with SMTP id i63so21845124pgd.2; Tue, 16 May 2017 08:39:37 -0700 (PDT) Received: from localhost.localdomain ([124.123.70.3]) by smtp.gmail.com with ESMTPSA id d86sm27874895pfj.75.2017.05.16.08.39.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 16 May 2017 08:39:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aywxKvK/yIN6/uD5W+MJ5laPhT1Atki/l/dyC9AM01M=; b=kIOYkmQJ9ZMU0uEELBJDdNU4DIJFxwGWcX3jHRGAFM5xUMTDhA5AZ1u79T0JkQnXgn NP525+TTIh80tMx5iPRt+ca9koUvgJeVLsjbJ2VTSUwkX4cVcYPUPBEXkTalTw6yBdWq 1FVD6/pVwXfUgkVRImWM5QpmPJGnhiyRb3YdvZ0bbv/DeAwGatmz73Ee844A8FgSlOrn eGQA1ZVZK9HZ9jWKNeGQt0sST6tXG7KLCZihtxA/02njADCx14imYyIpgTX0T+Byy4R1 woot0HGXyBm57Kz9nv8iDxUQNEjkOqPp/xJJ8TkEdlXtYV6rr6Zvt8IViNBrx21BOIts 6HwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aywxKvK/yIN6/uD5W+MJ5laPhT1Atki/l/dyC9AM01M=; b=dB22MQZjKFdbmZvXa7o+ZLBewy9nq0o1U41mW3pzX0o9Ghdup0xO/2kWqSqDJs7ek0 JZ1V1VWjlBhVfCvLJj6tDRC6yCM+rNDNMveE/wwNV0BqBdkhtDlOp/R1Z8w2RX/RS0C1 K/VvXl5Wc5yj5ikCDOvgrzNaf/cMk5i2QfIv905pIo/VRDmPANHZVM1mfQkFoZYFCQRN UmpN1rqHKWZvSkdxrIbaemvYYzPRvjI/k6Q8xk+GVmLMzI99fVdK809XksGDeHoq6aal nwV0u+vY1cTavTrFHCWyl/2qepATFW6fM36xIqucJWaX6huSOpknt3cmesrqSAI/CWal 1UYA== X-Gm-Message-State: AODbwcARzRJrjh8A0HnR3X6M+vzI2WXabiQeqUetp3PQ/hacXRDvY4Kc dNIIpOtBu9Eb4g== X-Received: by 10.98.65.216 with SMTP id g85mr13205260pfd.187.1494949177022; Tue, 16 May 2017 08:39:37 -0700 (PDT) From: Subbaraya Sundeep To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Tue, 16 May 2017 21:08:53 +0530 Message-Id: <1494949133-2202-6-git-send-email-sundeep.lkml@gmail.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1494949133-2202-1-git-send-email-sundeep.lkml@gmail.com> References: <1494949133-2202-1-git-send-email-sundeep.lkml@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [Qemu devel v5 PATCH 5/5] msf2: Add Emcraft's Smartfusion2 SOM kit. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Subbaraya Sundeep , f4bug@amsat.org, alistair23@gmail.com, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Emulated Emcraft's Smartfusion2 System On Module starter kit. Signed-off-by: Subbaraya Sundeep --- hw/arm/Makefile.objs | 1 + hw/arm/msf2-som.c | 89 ++++++++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 90 insertions(+) create mode 100644 hw/arm/msf2-som.c diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index c828061..4b02093 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -5,6 +5,7 @@ obj-y +=3D omap_sx1.o palm.o realview.o spitz.o stellaris.o obj-y +=3D tosa.o versatilepb.o vexpress.o virt.o xilinx_zynq.o z2.o obj-$(CONFIG_ACPI) +=3D virt-acpi-build.o obj-y +=3D netduino2.o +obj-y +=3D msf2-som.o obj-y +=3D sysbus-fdt.o =20 obj-y +=3D armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c new file mode 100644 index 0000000..cd2b759 --- /dev/null +++ b/hw/arm/msf2-som.c @@ -0,0 +1,89 @@ +/* + * SmartFusion2 SOM starter kit(from Emcraft) emulation. + * + * Copyright (c) 2017 Subbaraya Sundeep + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/boards.h" +#include "hw/arm/msf2-soc.h" +#include "hw/arm/arm.h" +#include "exec/address-spaces.h" + +#define DDR_BASE_ADDRESS 0xA0000000 +#define DDR_SIZE (64 * M_BYTE) + +static void emcraft_sf2_init(MachineState *machine) +{ + DeviceState *dev; + DeviceState *spi_flash; + MSF2State *soc; + DriveInfo *dinfo =3D drive_get_next(IF_MTD); + qemu_irq cs_line; + SSIBus *spi_bus; + MemoryRegion *sysmem =3D get_system_memory(); + MemoryRegion *ddr =3D g_new(MemoryRegion, 1); + + memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE, + &error_fatal); + vmstate_register_ram_global(ddr); + memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr); + + dev =3D qdev_create(NULL, TYPE_MSF2_SOC); + qdev_prop_set_string(dev, "part-name", "M2S010"); + qdev_prop_set_uint64(dev, "eNVM-size", M2S010_ENVM_SIZE); + qdev_prop_set_uint64(dev, "eSRAM-size", M2S010_ESRAM_SIZE); + + /* + * pclk0 and pclk1 are configurable in Libero. + * Emcraft's SoM kit comes with these settings by default. + */ + qdev_prop_set_uint32(dev, "pclk0", 71 * 1000000); + qdev_prop_set_uint32(dev, "pclk1", 71 * 1000000); + + object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal); + + soc =3D MSF2_SOC(dev); + + /* Attach SPI flash to SPI0 controller */ + spi_bus =3D (SSIBus *)qdev_get_child_bus(dev, "spi0"); + spi_flash =3D ssi_create_slave_no_init(spi_bus, "s25sl12801"); + qdev_prop_set_uint8(spi_flash, "spansion-cr2nv", 1); + if (dinfo) { + qdev_prop_set_drive(spi_flash, "drive", blk_by_legacy_dinfo(dinfo), + &error_fatal); + } + qdev_init_nofail(spi_flash); + cs_line =3D qdev_get_gpio_in_named(spi_flash, SSI_GPIO_CS, 0); + sysbus_connect_irq(SYS_BUS_DEVICE(&soc->spi[0]), 1, cs_line); + + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, + soc->envm_size); +} + +static void emcraft_sf2_machine_init(MachineClass *mc) +{ + mc->desc =3D "SmartFusion2 SOM kit from Emcraft"; + mc->init =3D emcraft_sf2_init; +} + +DEFINE_MACHINE("smartfusion2-som", emcraft_sf2_machine_init) --=20 2.5.0