From nobody Tue Feb 10 19:47:49 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1494348421244660.3324586846181; Tue, 9 May 2017 09:47:01 -0700 (PDT) Received: from localhost ([::1]:38209 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d88Hq-0000Sp-Sx for importer@patchew.org; Tue, 09 May 2017 12:46:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56356) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d88GX-00083f-CW for qemu-devel@nongnu.org; Tue, 09 May 2017 12:45:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d88GW-0005HS-1E for qemu-devel@nongnu.org; Tue, 09 May 2017 12:45:37 -0400 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:36139) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d88GV-0005H8-P4; Tue, 09 May 2017 12:45:35 -0400 Received: by mail-pf0-x243.google.com with SMTP id v14so656174pfd.3; Tue, 09 May 2017 09:45:35 -0700 (PDT) Received: from localhost.localdomain ([124.123.70.3]) by smtp.gmail.com with ESMTPSA id o194sm833320pfg.117.2017.05.09.09.45.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 09 May 2017 09:45:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KSqFnZq1mB7E8jcbye0DiOzX4pzyus6JLfpLA+L0UgU=; b=fpZdbu5G4wtZUoCGTS2eZDJwr0fdOVy24E85WLL+yWHf4Zor6DtdCBJCYeQZ4bRIvT v2rlzsO6NeXpGYshbpQJyCXk2YceOkm8HusXRyvcQOBiEZdI9UJjlqJ8KOl7B7glkOTA uB9a0VpMY2jpyKtGJBEJPwCb7fPIPfT3IOBCFDVdn/5Un0yzukTD/kQUFsYeTvN4PusP e/4Uq5l1I8YhP2ZbSviGyOgzN//s4FiNbupjMWjmSSiGitmmbGOWr2kHuKooeKYk0uTS Q7mdhug97rSZPyq+PCXNq0Z0FbrARxjXhfqLCTQSd2O55cbzixAl83sOYXiIbKa3/yyF or6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KSqFnZq1mB7E8jcbye0DiOzX4pzyus6JLfpLA+L0UgU=; b=WvaKOICBc+pVlDUbxzUNw+bLfVp0lkpfP4NYGLiS+M9LgCEPAiLfYLF9KwLZPiM087 d72QsZ43upT+6PCgYI5qaCF04IyKwNKPe2VW3Fv4d8raOPa87kgS0Gg84ZHpMZbqR2eU CmZs/bTmkYG2zpjxToYWSDE+SdbW4zZBox9M1W4nWSHDUqB/88KNqiKiHcFewmu6/GF1 AyJCw962ociZoz08vQIpSYdp2n10suUT94XDhksbO9yZG96ZfpZkSdBJdJljtFz39Whb E9hgZtEBF+t3+yJwBPXkJ9zvlx0MktlCgYBeze+pkwXg83XtX8ZOSAgBOLb+CEey+K0b V5PQ== X-Gm-Message-State: AODbwcDwasbk6UfbTr1u7I/+AB3K9zBisYEfVnlUPILYTbgVHvgN7tSa RdrIjdbUEh9aud+Z X-Received: by 10.99.55.65 with SMTP id g1mr1196728pgn.208.1494348334551; Tue, 09 May 2017 09:45:34 -0700 (PDT) From: Subbaraya Sundeep To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Tue, 9 May 2017 22:14:43 +0530 Message-Id: <1494348286-10253-3-git-send-email-sundeep.lkml@gmail.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1494348286-10253-1-git-send-email-sundeep.lkml@gmail.com> References: <1494348286-10253-1-git-send-email-sundeep.lkml@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [Qemu-devel PATCH 2/5] msf2: Microsemi Smartfusion2 System Register block. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Subbaraya Sundeep , alistair23@gmail.com, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Added Sytem register block of Smartfusion2. This block has PLL registers which are accessed by guest. Signed-off-by: Subbaraya Sundeep --- hw/misc/Makefile.objs | 1 + hw/misc/msf2-sysreg.c | 131 ++++++++++++++++++++++++++++++++++++++= ++++ include/hw/misc/msf2-sysreg.h | 80 ++++++++++++++++++++++++++ 3 files changed, 212 insertions(+) create mode 100644 hw/misc/msf2-sysreg.c create mode 100644 include/hw/misc/msf2-sysreg.h diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index c8b4893..0f52354 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -56,3 +56,4 @@ obj-$(CONFIG_EDU) +=3D edu.o obj-$(CONFIG_HYPERV_TESTDEV) +=3D hyperv_testdev.o obj-$(CONFIG_AUX) +=3D auxbus.o obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_scu.o aspeed_sdmc.o +obj-$(CONFIG_MSF2) +=3D msf2-sysreg.o diff --git a/hw/misc/msf2-sysreg.c b/hw/misc/msf2-sysreg.c new file mode 100644 index 0000000..53e9cba --- /dev/null +++ b/hw/misc/msf2-sysreg.c @@ -0,0 +1,131 @@ +/* + * System Register block model of Microsemi SmartFusion2. + * + * Copyright (c) 2017 Subbaraya Sundeep + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "hw/misc/msf2-sysreg.h" + +#ifndef MSF2_SYSREG_ERR_DEBUG +#define MSF2_SYSREG_ERR_DEBUG 0 +#endif + +#define DB_PRINT_L(lvl, fmt, args...) do { \ + if (MSF2_SYSREG_ERR_DEBUG >=3D lvl) { \ + qemu_log("%s: " fmt, __func__, ## args); \ + } \ +} while (0); + +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) + +static void msf2_sysreg_reset(DeviceState *d) +{ + MSF2SysregState *s =3D MSF2_SYSREG(d); + + DB_PRINT("RESET\n"); + + s->regs[MSSDDR_PLL_STATUS_LOW_CR] =3D 0x02420041; + s->regs[MSSDDR_FACC1_CR] =3D 0x0A482124; + s->regs[MSSDDR_PLL_STATUS] =3D 0x3; +} + +static uint64_t msf2_sysreg_read(void *opaque, hwaddr offset, + unsigned size) +{ + MSF2SysregState *s =3D opaque; + offset /=3D 4; + uint32_t ret =3D 0; + + if (offset < ARRAY_SIZE(s->regs)) { + ret =3D s->regs[offset]; + DB_PRINT("addr: 0x%08" HWADDR_PRIx " data: 0x%08" PRIx32 "\n", + offset * 4, ret); + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%08" HWADDR_PRIx "\n", __func__, + offset * 4); + } + + return ret; +} + +static void msf2_sysreg_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + MSF2SysregState *s =3D (MSF2SysregState *)opaque; + offset /=3D 4; + + DB_PRINT("addr: 0x%08" HWADDR_PRIx " data: 0x%08" PRIx64 "\n", + offset * 4, val); + + switch (offset) { + case MSSDDR_PLL_STATUS: + break; + + default: + if (offset < ARRAY_SIZE(s->regs)) { + s->regs[offset] =3D val; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%08" HWADDR_PRIx "\n", __func__, + offset * 4); + } + break; + } +} + +static const MemoryRegionOps sysreg_ops =3D { + .read =3D msf2_sysreg_read, + .write =3D msf2_sysreg_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; + +static void msf2_sysreg_init(Object *obj) +{ + MSF2SysregState *s =3D MSF2_SYSREG(obj); + + memory_region_init_io(&s->iomem, obj, &sysreg_ops, s, TYPE_MSF2_SYSREG, + MSF2_SYSREG_MMIO_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); +} + +static const VMStateDescription vmstate_msf2_sysreg =3D { + .name =3D TYPE_MSF2_SYSREG, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, MSF2SysregState, MSF2_SYSREG_NUM_REGS), + VMSTATE_END_OF_LIST() + } +}; + +static void msf2_sysreg_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->vmsd =3D &vmstate_msf2_sysreg; + dc->reset =3D msf2_sysreg_reset; +} + +static const TypeInfo msf2_sysreg_info =3D { + .name =3D TYPE_MSF2_SYSREG, + .parent =3D TYPE_SYS_BUS_DEVICE, + .class_init =3D msf2_sysreg_class_init, + .instance_size =3D sizeof(MSF2SysregState), + .instance_init =3D msf2_sysreg_init, +}; + +static void msf2_sysreg_register_types(void) +{ + type_register_static(&msf2_sysreg_info); +} + +type_init(msf2_sysreg_register_types) diff --git a/include/hw/misc/msf2-sysreg.h b/include/hw/misc/msf2-sysreg.h new file mode 100644 index 0000000..a485ed6 --- /dev/null +++ b/include/hw/misc/msf2-sysreg.h @@ -0,0 +1,80 @@ +/* + * Microsemi SmartFusion2 SYSREG + * + * Copyright (c) 2017 Subbaraya Sundeep + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef HW_MSF2_SYSREG_H +#define HW_MSF2_SYSREG_H + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/hw.h" +#include "sysemu/sysemu.h" +#include "qemu/log.h" + +enum { + ESRAM_CR =3D 0x00 / 4, + ESRAM_MAX_LAT, + DDR_CR, + ENVM_CR, + ENVM_REMAP_BASE_CR, + ENVM_REMAP_FAB_CR, + CC_CR, + CC_REGION_CR, + CC_LOCK_BASE_ADDR_CR, + CC_FLUSH_INDX_CR, + DDRB_BUF_TIMER_CR, + DDRB_NB_ADDR_CR, + DDRB_NB_SIZE_CR, + DDRB_CR, + + SOFT_RESET_CR =3D 0x48 / 4, + M3_CR, + + GPIO_SYSRESET_SEL_CR =3D 0x58 / 4, + + MDDR_CR =3D 0x60 / 4, + + MSSDDR_PLL_STATUS_LOW_CR =3D 0x90 / 4, + MSSDDR_PLL_STATUS_HIGH_CR, + MSSDDR_FACC1_CR, + MSSDDR_FACC2_CR, + + MSSDDR_PLL_STATUS =3D 0x150 / 4, + +}; + +#define MSF2_SYSREG_MMIO_SIZE 0x300 +#define MSF2_SYSREG_NUM_REGS (MSF2_SYSREG_MMIO_SIZE / 4) + +#define TYPE_MSF2_SYSREG "msf2-sysreg" +#define MSF2_SYSREG(obj) OBJECT_CHECK(MSF2SysregState, (obj), TYPE_MSF2_S= YSREG) + +typedef struct MSF2SysregState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + + uint32_t regs[MSF2_SYSREG_NUM_REGS]; +} MSF2SysregState; + +#endif /* HW_MSF2_SYSREG_H */ --=20 2.5.0