From nobody Tue Feb 10 17:08:54 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1494309763838385.1021221517782; Mon, 8 May 2017 23:02:43 -0700 (PDT) Received: from localhost ([::1]:35175 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d7yEK-0003fm-Bb for importer@patchew.org; Tue, 09 May 2017 02:02:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46707) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d7yCj-0002WU-UV for qemu-devel@nongnu.org; Tue, 09 May 2017 02:01:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d7yCj-0001tC-7E for qemu-devel@nongnu.org; Tue, 09 May 2017 02:01:01 -0400 Received: from mx1.redhat.com ([209.132.183.28]:41654) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1d7yCi-0001st-VG for qemu-devel@nongnu.org; Tue, 09 May 2017 02:01:01 -0400 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id CAADA85547 for ; Tue, 9 May 2017 06:00:59 +0000 (UTC) Received: from pxdev.xzpeter.org.com (vpn1-5-50.pek2.redhat.com [10.72.5.50]) by smtp.corp.redhat.com (Postfix) with ESMTP id E901919652; Tue, 9 May 2017 06:00:57 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com CAADA85547 Authentication-Results: ext-mx04.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx04.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=peterx@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com CAADA85547 From: Peter Xu To: qemu-devel@nongnu.org Date: Tue, 9 May 2017 14:00:43 +0800 Message-Id: <1494309644-18743-3-git-send-email-peterx@redhat.com> In-Reply-To: <1494309644-18743-1-git-send-email-peterx@redhat.com> References: <1494309644-18743-1-git-send-email-peterx@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Tue, 09 May 2017 06:01:00 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2 2/3] msix: trace control bit write op X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , peterx@redhat.com, "Michael S . Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Meanwhile, abstract a function to detect msix masked bit. Signed-off-by: Peter Xu Acked-by: Michael S. Tsirkin Reviewed-by: Michael S. Tsirkin Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/pci/msix.c | 11 +++++++++-- hw/pci/trace-events | 3 +++ 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/hw/pci/msix.c b/hw/pci/msix.c index bb54e8b..fc5fe51 100644 --- a/hw/pci/msix.c +++ b/hw/pci/msix.c @@ -22,6 +22,7 @@ #include "hw/xen/xen.h" #include "qemu/range.h" #include "qapi/error.h" +#include "trace.h" =20 #define MSIX_CAP_LENGTH 12 =20 @@ -130,10 +131,14 @@ static void msix_handle_mask_update(PCIDevice *dev, i= nt vector, bool was_masked) } } =20 +static bool msix_masked(PCIDevice *dev) +{ + return dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL= _MASK; +} + static void msix_update_function_masked(PCIDevice *dev) { - dev->msix_function_masked =3D !msix_enabled(dev) || - (dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL_M= ASK); + dev->msix_function_masked =3D !msix_enabled(dev) || msix_masked(dev); } =20 /* Handle MSI-X capability config write. */ @@ -148,6 +153,8 @@ void msix_write_config(PCIDevice *dev, uint32_t addr, return; } =20 + trace_msix_write_config(dev->name, msix_enabled(dev), msix_masked(dev)= ); + was_masked =3D dev->msix_function_masked; msix_update_function_masked(dev); =20 diff --git a/hw/pci/trace-events b/hw/pci/trace-events index 2b9cf24..83c8f5a 100644 --- a/hw/pci/trace-events +++ b/hw/pci/trace-events @@ -7,3 +7,6 @@ pci_update_mappings_add(void *d, uint32_t bus, uint32_t slo= t, uint32_t func, int # hw/pci/pci_host.c pci_cfg_read(const char *dev, unsigned devid, unsigned fnid, unsigned offs= , unsigned val) "%s %02u:%u @0x%x -> 0x%x" pci_cfg_write(const char *dev, unsigned devid, unsigned fnid, unsigned off= s, unsigned val) "%s %02u:%u @0x%x <- 0x%x" + +# hw/pci/msix.c +msix_write_config(char *name, bool enabled, bool masked) "dev %s enabled %= d masked %d" --=20 2.7.4