From nobody Mon Feb 9 02:27:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1493816528368701.5047236606111; Wed, 3 May 2017 06:02:08 -0700 (PDT) Received: from localhost ([::1]:36600 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d5tux-0003B6-1a for importer@patchew.org; Wed, 03 May 2017 09:02:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39213) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d5tqY-0007xx-Aa for qemu-devel@nongnu.org; Wed, 03 May 2017 08:57:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d5tqX-0000aC-5o for qemu-devel@nongnu.org; Wed, 03 May 2017 08:57:34 -0400 Received: from mx1.redhat.com ([209.132.183.28]:52726) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1d5tqU-0000YY-A6; Wed, 03 May 2017 08:57:30 -0400 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 2112F61D0F; Wed, 3 May 2017 12:57:29 +0000 (UTC) Received: from dell-r430-03.lab.eng.brq.redhat.com (dell-r430-03.lab.eng.brq.redhat.com [10.34.112.60]) by smtp.corp.redhat.com (Postfix) with ESMTP id F1824182D8; Wed, 3 May 2017 12:57:26 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 2112F61D0F Authentication-Results: ext-mx10.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx10.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=imammedo@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com 2112F61D0F From: Igor Mammedov To: qemu-devel@nongnu.org Date: Wed, 3 May 2017 14:56:56 +0200 Message-Id: <1493816238-33120-3-git-send-email-imammedo@redhat.com> In-Reply-To: <1493816238-33120-1-git-send-email-imammedo@redhat.com> References: <1493816238-33120-1-git-send-email-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.39]); Wed, 03 May 2017 12:57:29 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2 02/24] hw/arm/virt: extract mp-affinity calculation in separate function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Andrew Jones , Eduardo Habkost , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Shannon Zhao , Paolo Bonzini , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Igor Mammedov Reviewed-by: Andrew Jones --- v2: (Drew) - s/virt_idx2mp_affinity/virt_cpu_mp_affinity/ - add arm_cpu_mp_affinity() to reduce code duplication --- target/arm/cpu.h | 2 ++ hw/arm/virt.c | 43 ++++++++++++++++++++++++++----------------- target/arm/cpu.c | 12 +++++++++--- 3 files changed, 37 insertions(+), 20 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1055bfe..048faed 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -710,6 +710,8 @@ static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) return container_of(env, ARMCPU, env); } =20 +uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); + #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e)) =20 #define ENV_OFFSET offsetof(ARMCPU, env) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 5f62a03..61ae437 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1194,6 +1194,29 @@ void virt_machine_done(Notifier *notifier, void *dat= a) virt_build_smbios(vms); } =20 +static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) +{ + uint8_t clustersz =3D ARM_DEFAULT_CPUS_PER_CLUSTER; + VirtMachineClass *vmc =3D VIRT_MACHINE_GET_CLASS(vms); + + if (!vmc->disallow_affinity_adjustment) { + /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the + * GIC's target-list limitations. 32-bit KVM hosts currently + * always create clusters of 4 CPUs, but that is expected to + * change when they gain support for gicv3. When KVM is enabled + * it will override the changes we make here, therefore our + * purposes are to make TCG consistent (with 64-bit KVM hosts) + * and to improve SGI efficiency. + */ + if (vms->gic_version =3D=3D 3) { + clustersz =3D GICV3_TARGETLIST_BITS; + } else { + clustersz =3D GIC_TARGETLIST_BITS; + } + } + return arm_cpu_mp_affinity(idx, clustersz); +} + static void machvirt_init(MachineState *machine) { VirtMachineState *vms =3D VIRT_MACHINE(machine); @@ -1210,7 +1233,6 @@ static void machvirt_init(MachineState *machine) CPUClass *cc; Error *err =3D NULL; bool firmware_loaded =3D bios_name || drive_get(IF_PFLASH, 0, 0); - uint8_t clustersz; =20 if (!cpu_model) { cpu_model =3D "cortex-a15"; @@ -1263,10 +1285,8 @@ static void machvirt_init(MachineState *machine) */ if (vms->gic_version =3D=3D 3) { virt_max_cpus =3D vms->memmap[VIRT_GIC_REDIST].size / 0x20000; - clustersz =3D GICV3_TARGETLIST_BITS; } else { virt_max_cpus =3D GIC_NCPU; - clustersz =3D GIC_TARGETLIST_BITS; } =20 if (max_cpus > virt_max_cpus) { @@ -1326,20 +1346,9 @@ static void machvirt_init(MachineState *machine) =20 for (n =3D 0; n < smp_cpus; n++) { Object *cpuobj =3D object_new(typename); - if (!vmc->disallow_affinity_adjustment) { - /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the - * GIC's target-list limitations. 32-bit KVM hosts currently - * always create clusters of 4 CPUs, but that is expected to - * change when they gain support for gicv3. When KVM is enabled - * it will override the changes we make here, therefore our - * purposes are to make TCG consistent (with 64-bit KVM hosts) - * and to improve SGI efficiency. - */ - uint8_t aff1 =3D n / clustersz; - uint8_t aff0 =3D n % clustersz; - object_property_set_int(cpuobj, (aff1 << ARM_AFF1_SHIFT) | aff= 0, - "mp-affinity", NULL); - } + + object_property_set_int(cpuobj, virt_cpu_mp_affinity(vms, n), + "mp-affinity", NULL); =20 if (!vms->secure) { object_property_set_bool(cpuobj, false, "has_el3", NULL); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b357aee..ee1406d 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -458,6 +458,13 @@ static void arm_disas_set_info(CPUState *cpu, disassem= ble_info *info) } } =20 +uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) +{ + uint32_t Aff1 =3D idx / clustersz; + uint32_t Aff0 =3D idx % clustersz; + return (Aff1 << ARM_AFF1_SHIFT) | Aff0; +} + static void arm_cpu_initfn(Object *obj) { CPUState *cs =3D CPU(obj); @@ -709,9 +716,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error *= *errp) * so these bits always RAZ. */ if (cpu->mp_affinity =3D=3D ARM64_AFFINITY_INVALID) { - uint32_t Aff1 =3D cs->cpu_index / ARM_DEFAULT_CPUS_PER_CLUSTER; - uint32_t Aff0 =3D cs->cpu_index % ARM_DEFAULT_CPUS_PER_CLUSTER; - cpu->mp_affinity =3D (Aff1 << ARM_AFF1_SHIFT) | Aff0; + cpu->mp_affinity =3D arm_cpu_mp_affinity(cs->cpu_index, + ARM_DEFAULT_CPUS_PER_CLUSTE= R); } =20 if (cpu->reset_hivecs) { --=20 2.7.4