From nobody Thu Mar 28 14:52:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1493398458004319.38747074171965; Fri, 28 Apr 2017 09:54:18 -0700 (PDT) Received: from localhost ([::1]:38030 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d499s-0004uA-ND for importer@patchew.org; Fri, 28 Apr 2017 12:54:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60757) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d498J-0003qw-OI for qemu-devel@nongnu.org; Fri, 28 Apr 2017 12:52:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d498I-00065o-28 for qemu-devel@nongnu.org; Fri, 28 Apr 2017 12:52:39 -0400 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:36092) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d498H-00065E-PY; Fri, 28 Apr 2017 12:52:37 -0400 Received: by mail-pg0-x242.google.com with SMTP id v1so6206805pgv.3; Fri, 28 Apr 2017 09:52:37 -0700 (PDT) Received: from localhost.localdomain ([124.123.70.3]) by smtp.gmail.com with ESMTPSA id r86sm11383528pfb.24.2017.04.28.09.52.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 28 Apr 2017 09:52:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3xGDtmkf8VCwL9uDsyBLKPnhh4JaVvF/8ZemmZ52mWU=; b=orzSPl2/2cy7h80EmnWoL0DSUMJb/2ceDRGj3HlhkVahjqta/Clahr6lHx1fMhKXF8 hX8DZNLaI8tFJNKtLHYEI8CQw8BT4pk3ZcyTFOR3qT6U2OeahT7Il9ruiK9VMv5O9YMl mNAsUXs8ETuJ+2GZXinTKkmZP3ONinAk/UOzcFcYjwMrNYpWNsTi6jkZyTG37as5V7VX XprCzr8PSCE644sTFZcfS57cugEOzbnWowLQ2gdTc/JO16vSWi3Tb539UwHT0arXomlT yMnQcs8hZT+Vqd8o9vNpQBnCKLb24S2WUUh2i08/pcofJzznm9Zv490XG1axW8zIENlM +vDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3xGDtmkf8VCwL9uDsyBLKPnhh4JaVvF/8ZemmZ52mWU=; b=nB54GkqWvlzDU9hLDE/1qc6t0JUmqiojRLUbFW+SymnVfE4jzDU13lB8aIcKN7ULPa kr4FWJwTskoWibsO9P8hO6W1cmFo6fIoQi1qRqXAxuT9WKlhMi99EGxeXbAe2vixek9l ovLo0UW4SauPxy5f4HRuGSUfc4PHW1VsmlxccIqnnBDw2FA0ZUqgeGYpEpChU8tczAId bcBfViB41IWFEBV72G7e3PKnZNgkqcImzge6Bdq8bl+GsJfphIQvl2KFMxtiKnV7bPIB PvJfC2R6ORlC22t7GFRqpS/IoNFMbtItomHPyOHxJv+47H4J5dCJweswfVk/VwtKMn8f mJ6w== X-Gm-Message-State: AN3rC/7qpht5oZ2zcfDo7y0SAzLkqo6Rq8UM5a7gOc6UudQs6VbtWnZj O6RznVz/Mdrbmg== X-Received: by 10.84.222.135 with SMTP id x7mr16536690pls.50.1493398356652; Fri, 28 Apr 2017 09:52:36 -0700 (PDT) From: Subbaraya Sundeep To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Fri, 28 Apr 2017 22:21:49 +0530 Message-Id: <1493398313-6673-2-git-send-email-sundeep.lkml@gmail.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1493398313-6673-1-git-send-email-sundeep.lkml@gmail.com> References: <1493398313-6673-1-git-send-email-sundeep.lkml@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [Qemu-devel RFC v3 1/5] msf2: Add Smartfusion2 System timer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Subbaraya Sundeep , alistair23@gmail.com, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Modelled System Timer in Microsemi's Smartfusion2 Soc. Timer has two 32bit down counters and two interrupts. Signed-off-by: Subbaraya Sundeep --- hw/timer/Makefile.objs | 1 + hw/timer/msf2_timer.c | 250 ++++++++++++++++++++++++++++++++++++++= ++++ include/hw/timer/msf2_timer.h | 82 ++++++++++++++ 3 files changed, 333 insertions(+) create mode 100644 hw/timer/msf2_timer.c create mode 100644 include/hw/timer/msf2_timer.h diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs index dd6f27e..0bdf1e1 100644 --- a/hw/timer/Makefile.objs +++ b/hw/timer/Makefile.objs @@ -41,3 +41,4 @@ common-obj-$(CONFIG_STM32F2XX_TIMER) +=3D stm32f2xx_timer= .o common-obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_timer.o =20 common-obj-$(CONFIG_SUN4V_RTC) +=3D sun4v-rtc.o +common-obj-$(CONFIG_MSF2) +=3D msf2_timer.o diff --git a/hw/timer/msf2_timer.c b/hw/timer/msf2_timer.c new file mode 100644 index 0000000..d1dbde5 --- /dev/null +++ b/hw/timer/msf2_timer.c @@ -0,0 +1,250 @@ +/* + * Timer block model of Microsemi SmartFusion2. + * + * Copyright (c) 2017 Subbaraya Sundeep . + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/timer/msf2_timer.h" +#include "hw/sysbus.h" +#include "qemu/log.h" +#include "qemu/main-loop.h" + +#ifndef MSF2_TIMER_ERR_DEBUG +#define MSF2_TIMER_ERR_DEBUG 0 +#endif + +#define DB_PRINT_L(lvl, fmt, args...) do { \ + if (MSF2_TIMER_ERR_DEBUG >=3D lvl) { \ + qemu_log("%s: " fmt, __func__, ## args); \ + } \ +} while (0); + +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) + +static void timer_update_irq(struct Msf2Timer *st) +{ + bool isr, ier; + + isr =3D !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK); + ier =3D !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR); + + qemu_set_irq(st->irq, (ier && isr)); +} + +static void timer_update(struct Msf2Timer *st) +{ + uint64_t count; + + DB_PRINT("timer=3D%d\n", st->nr); + + if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL)) { + ptimer_stop(st->ptimer); + return; + } + + count =3D st->regs[R_TIM_LOADVAL]; + ptimer_set_limit(st->ptimer, count, 1); + ptimer_run(st->ptimer, 1); +} + +static uint64_t +timer_read(void *opaque, hwaddr addr, unsigned int size) +{ + MSF2TimerState *t =3D opaque; + struct Msf2Timer *st; + uint32_t r =3D 0; + unsigned int timer =3D 0; + int isr; + int ier; + + addr >>=3D 2; + /* + * Two independent timers has same base address. + * Based on addr passed figure out which timer is being used. + */ + if (addr >=3D R_TIM1_MAX) { + timer =3D 1; + addr -=3D R_TIM1_MAX; + } + + st =3D &t->timers[timer]; + + switch (addr) { + case R_TIM_VAL: + r =3D ptimer_get_count(st->ptimer); + DB_PRINT("msf2_timer t=3D%d read counter=3D%x\n", timer, r); + break; + + case R_TIM_MIS: + isr =3D !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK); + ier =3D !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR); + r =3D ier && isr; + break; + + default: + if (addr < ARRAY_SIZE(st->regs)) { + r =3D st->regs[addr]; + } + break; + } + DB_PRINT("timer=3D%d %lu=3D%x\n", timer, addr * 4, r); + return r; +} + +static void +timer_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + MSF2TimerState *t =3D opaque; + struct Msf2Timer *st; + unsigned int timer =3D 0; + uint32_t value =3D val64; + + addr >>=3D 2; + /* + * Two independent timers has same base address. + * Based on addr passed figure out which timer is being used. + */ + if (addr >=3D R_TIM1_MAX) { + timer =3D 1; + addr -=3D R_TIM1_MAX; + } + + st =3D &t->timers[timer]; + + DB_PRINT("addr=3D%lu val=3D%x (timer=3D%d)\n", addr * 4, value, timer); + + switch (addr) { + case R_TIM_CTRL: + st->regs[R_TIM_CTRL] =3D value; + timer_update(st); + break; + + case R_TIM_RIS: + if (value & TIMER_RIS_ACK) { + st->regs[R_TIM_RIS] &=3D ~TIMER_RIS_ACK; + } + break; + + case R_TIM_LOADVAL: + st->regs[R_TIM_LOADVAL] =3D value; + if (st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL) { + timer_update(st); + } + break; + + case R_TIM_BGLOADVAL: + st->regs[R_TIM_BGLOADVAL] =3D value; + st->regs[R_TIM_LOADVAL] =3D value; + break; + + case R_TIM_VAL: + case R_TIM_MIS: + break; + + case R_TIM_MODE: + if (value & TIMER_MODE) { + DB_PRINT("64-bit mode not supported\n"); + } + break; + + default: + if (addr < ARRAY_SIZE(st->regs)) { + st->regs[addr] =3D value; + } + break; + } + timer_update_irq(st); +} + +static const MemoryRegionOps timer_ops =3D { + .read =3D timer_read, + .write =3D timer_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4 + } +}; + +static void timer_hit(void *opaque) +{ + struct Msf2Timer *st =3D opaque; + + DB_PRINT("%d\n", st->nr); + st->regs[R_TIM_RIS] |=3D TIMER_RIS_ACK; + + if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ONESHOT)) { + timer_update(st); + } + timer_update_irq(st); +} + +static void msf2_timer_init(Object *obj) +{ + MSF2TimerState *t =3D MSF2_TIMER(obj); + unsigned int i; + + /* Init all the ptimers. */ + t->timers =3D g_malloc0((sizeof t->timers[0]) * NUM_TIMERS); + for (i =3D 0; i < NUM_TIMERS; i++) { + struct Msf2Timer *st =3D &t->timers[i]; + + st->nr =3D i; + st->bh =3D qemu_bh_new(timer_hit, st); + st->ptimer =3D ptimer_init(st->bh, PTIMER_POLICY_DEFAULT); + ptimer_set_freq(st->ptimer, t->freq_hz); + sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq); + } + + memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, TYPE_MSF2_TI= MER, + R_TIM_MAX * 4); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &t->mmio); +} + +static Property msf2_timer_properties[] =3D { + DEFINE_PROP_UINT32("clock-frequency", MSF2TimerState, freq_hz, + 83 * 1000000), + DEFINE_PROP_END_OF_LIST(), +}; + +static void msf2_timer_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->props =3D msf2_timer_properties; +} + +static const TypeInfo msf2_timer_info =3D { + .name =3D TYPE_MSF2_TIMER, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(MSF2TimerState), + .instance_init =3D msf2_timer_init, + .class_init =3D msf2_timer_class_init, +}; + +static void msf2_timer_register_types(void) +{ + type_register_static(&msf2_timer_info); +} + +type_init(msf2_timer_register_types) diff --git a/include/hw/timer/msf2_timer.h b/include/hw/timer/msf2_timer.h new file mode 100644 index 0000000..93d9fb3 --- /dev/null +++ b/include/hw/timer/msf2_timer.h @@ -0,0 +1,82 @@ +/* + * Microsemi SmartFusion2 Timer. + * + * Copyright (c) 2017 Subbaraya Sundeep + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef HW_MSF2_TIMER_H +#define HW_MSF2_TIMER_H + +#include "hw/sysbus.h" +#include "hw/ptimer.h" +#include "sysemu/sysemu.h" + +#define TYPE_MSF2_TIMER "msf2-timer" +#define MSF2_TIMER(obj) OBJECT_CHECK(MSF2TimerState, \ + (obj), TYPE_MSF2_TIMER) + +/* + * There are two 32-bit down counting timers. + * Timers 1 and 2 can be concatenated into a single 64-bit Timer + * that operates either in Periodic mode or in One-shot mode. + * Writing 1 to the TIM64_MODE register bit 0 sets the Timers in 64-bit mo= de. + * In 64-bit mode, writing to the 32-bit registers has no effect. + * Similarly, in 32-bit mode, writing to the 64-bit mode registers + * has no effect. Only two 32-bit timers are supported currently. + */ +#define NUM_TIMERS 2 + +#define R_TIM_VAL 0 +#define R_TIM_LOADVAL 1 +#define R_TIM_BGLOADVAL 2 +#define R_TIM_CTRL 3 +#define R_TIM_RIS 4 +#define R_TIM_MIS 5 +#define R_TIM1_MAX 6 + +#define R_TIM_MODE 21 +#define R_TIM_MAX 22 /* including 64-bit timer registers */ + +#define TIMER_CTRL_ENBL (1 << 0) +#define TIMER_CTRL_ONESHOT (1 << 1) +#define TIMER_CTRL_INTR (1 << 2) +#define TIMER_RIS_ACK (1 << 0) +#define TIMER_RST_CLR (1 << 6) +#define TIMER_MODE (1 << 0) + +struct Msf2Timer { + QEMUBH *bh; + ptimer_state *ptimer; + int nr; /* for debug. */ + + uint32_t regs[R_TIM_MAX]; + qemu_irq irq; +}; + +typedef struct MSF2TimerState { + SysBusDevice parent_obj; + + MemoryRegion mmio; + uint32_t freq_hz; + struct Msf2Timer *timers; +} MSF2TimerState; + +#endif /* HW_MSF2_TIMER_H */ --=20 2.5.0 From nobody Thu Mar 28 14:52:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1493398468992595.4907916563442; Fri, 28 Apr 2017 09:54:28 -0700 (PDT) Received: from localhost ([::1]:38031 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d49A3-00052b-OL for importer@patchew.org; Fri, 28 Apr 2017 12:54:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60792) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d498M-0003r7-LM for qemu-devel@nongnu.org; Fri, 28 Apr 2017 12:52:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d498K-000685-W1 for qemu-devel@nongnu.org; Fri, 28 Apr 2017 12:52:42 -0400 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:35007) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d498K-00067J-Nl; Fri, 28 Apr 2017 12:52:40 -0400 Received: by mail-pf0-x242.google.com with SMTP id i4so4767324pfc.2; Fri, 28 Apr 2017 09:52:40 -0700 (PDT) Received: from localhost.localdomain ([124.123.70.3]) by smtp.gmail.com with ESMTPSA id r86sm11383528pfb.24.2017.04.28.09.52.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 28 Apr 2017 09:52:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/3ENvz4jhrTBD/mO9IOgkUU5S7jO+DjGPfaUm9BwM3k=; b=NylMpfRbrOAHjsCQJTS9RXYoFYKkksIiINj4lEXigbn7xZ2CP/iAmq3hdPlZNlSQzX nnNCpVvL5i/FTIO26P/FhGhWaXGOuc/AdOfmwttRCyvkY6Pvru+zwFr0I+a3rEONl68D TzxRNIVDpDoLuDuJIzRRSMIiYMaIwBK+iDWLjWFDFWvofvL8bDzCe+dV62VlbbqVn7VU Kq0ll2Mt90Dw1vxYERa0hizIvQgFu6iH4gi1411TbVJqNewDBBvECUqhVk+qCOYFT3+W kXmsmuCXDi3igDKk6/RAa9wrnkHtamF/1qnbi1DkxApO5nG/xhPd14j2G7yfadsNvkY9 ccHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/3ENvz4jhrTBD/mO9IOgkUU5S7jO+DjGPfaUm9BwM3k=; b=cN/Q7W1d3Cq/O4jdBULwPpt3iylUrxiCk9zcr/rucSkK/3cTl5LFhs9Zb8zrl4B9TC 33MMD4l+D8oN+0uO8d634ubuXhkqBksITzF8AGxRMlfDIdRipx4lJw0Hp77F6udWFrRm V65sWbtkQK3GgsZ6pWHQwuO6jqufmoeit0JnlooQfnZ66hJ2E4XZcGSoyHnLidNoVEUs eREigvuaOGpXGy6+NlX/d0TWa4sr3K3sNorzcpqh3+74ooe3uBDLWGejFAbOqwVWEtgu 4JEEI400tVSSV2uvycAZzzbadVnS3P1aZHNRpQ+g+Jkz/uOIW+3KOmFqcOLyWghsCP0F NuRQ== X-Gm-Message-State: AN3rC/5FfnK3QRK9dbc75nI606EkW/uPGcuRdCG0hn8u8YNJ+CoFhWb2 51pYxWBnhoAxqxg1 X-Received: by 10.99.117.19 with SMTP id q19mr12660253pgc.106.1493398359180; Fri, 28 Apr 2017 09:52:39 -0700 (PDT) From: Subbaraya Sundeep To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Fri, 28 Apr 2017 22:21:50 +0530 Message-Id: <1493398313-6673-3-git-send-email-sundeep.lkml@gmail.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1493398313-6673-1-git-send-email-sundeep.lkml@gmail.com> References: <1493398313-6673-1-git-send-email-sundeep.lkml@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [Qemu-devel RFC v3 2/5] msf2: Microsemi Smartfusion2 System Register block. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Subbaraya Sundeep , alistair23@gmail.com, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Added Sytem register block of Smartfusion2. This block has PLL registers which are accessed by guest. Signed-off-by: Subbaraya Sundeep --- hw/misc/Makefile.objs | 1 + hw/misc/msf2_sysreg.c | 127 ++++++++++++++++++++++++++++++++++++++= ++++ include/hw/misc/msf2_sysreg.h | 77 +++++++++++++++++++++++++ 3 files changed, 205 insertions(+) create mode 100644 hw/misc/msf2_sysreg.c create mode 100644 include/hw/misc/msf2_sysreg.h diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index c8b4893..aee53df 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -56,3 +56,4 @@ obj-$(CONFIG_EDU) +=3D edu.o obj-$(CONFIG_HYPERV_TESTDEV) +=3D hyperv_testdev.o obj-$(CONFIG_AUX) +=3D auxbus.o obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_scu.o aspeed_sdmc.o +obj-$(CONFIG_MSF2) +=3D msf2_sysreg.o diff --git a/hw/misc/msf2_sysreg.c b/hw/misc/msf2_sysreg.c new file mode 100644 index 0000000..6386953 --- /dev/null +++ b/hw/misc/msf2_sysreg.c @@ -0,0 +1,127 @@ +/* + * System Register block model of Microsemi SmartFusion2. + * + * Copyright (c) 2017 Subbaraya Sundeep + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "hw/misc/msf2_sysreg.h" +#include "sysemu/sysemu.h" +#include "qemu/log.h" + +#ifndef MSF2_SYSREG_ERR_DEBUG +#define MSF2_SYSREG_ERR_DEBUG 0 +#endif + +#define DB_PRINT_L(lvl, fmt, args...) do { \ + if (MSF2_SYSREG_ERR_DEBUG >=3D lvl) { \ + qemu_log("%s: " fmt, __func__, ## args); \ + } \ +} while (0); + +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) + +static void msf2_sysreg_reset(DeviceState *d) +{ + MSF2SysregState *s =3D MSF2_SYSREG(d); + + DB_PRINT("RESET\n"); + + s->regs[MSSDDR_PLL_STATUS_LOW_CR] =3D 0x02420041; + s->regs[MSSDDR_FACC1_CR] =3D 0x0A482124; + s->regs[MSSDDR_PLL_STATUS] =3D 0x3; +} + +static uint64_t msf2_sysreg_read(void *opaque, hwaddr offset, + unsigned size) +{ + MSF2SysregState *s =3D opaque; + offset /=3D 4; + uint32_t ret =3D 0; + + if (offset < ARRAY_SIZE(s->regs)) { + ret =3D s->regs[offset]; + DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx32 "\n", + offset * 4, ret); + } else { + DB_PRINT("addr: %08" HWADDR_PRIx " not valid\n", offset * 4); + } + + return ret; +} + +static void msf2_sysreg_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + MSF2SysregState *s =3D (MSF2SysregState *)opaque; + offset /=3D 4; + + DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx64 "\n", offset * 4,= val); + + switch (offset) { + case MSSDDR_PLL_STATUS: + break; + + default: + if (offset < ARRAY_SIZE(s->regs)) { + s->regs[offset] =3D val; + } + break; + } +} + +static const MemoryRegionOps sysreg_ops =3D { + .read =3D msf2_sysreg_read, + .write =3D msf2_sysreg_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; + +static void msf2_sysreg_init(Object *obj) +{ + MSF2SysregState *s =3D MSF2_SYSREG(obj); + + memory_region_init_io(&s->iomem, obj, &sysreg_ops, s, TYPE_MSF2_SYSREG, + MSF2_SYSREG_MMIO_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); +} + +static const VMStateDescription vmstate_msf2_sysreg =3D { + .name =3D TYPE_MSF2_SYSREG, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, MSF2SysregState, MSF2_SYSREG_NUM_REGS), + VMSTATE_END_OF_LIST() + } +}; + +static void msf2_sysreg_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->vmsd =3D &vmstate_msf2_sysreg; + dc->reset =3D msf2_sysreg_reset; +} + +static const TypeInfo msf2_sysreg_info =3D { + .name =3D TYPE_MSF2_SYSREG, + .parent =3D TYPE_SYS_BUS_DEVICE, + .class_init =3D msf2_sysreg_class_init, + .instance_size =3D sizeof(MSF2SysregState), + .instance_init =3D msf2_sysreg_init, +}; + +static void msf2_sysreg_register_types(void) +{ + type_register_static(&msf2_sysreg_info); +} + +type_init(msf2_sysreg_register_types) diff --git a/include/hw/misc/msf2_sysreg.h b/include/hw/misc/msf2_sysreg.h new file mode 100644 index 0000000..03c5773 --- /dev/null +++ b/include/hw/misc/msf2_sysreg.h @@ -0,0 +1,77 @@ +/* + * Microsemi SmartFusion2 SYSREG + * + * Copyright (c) 2017 Subbaraya Sundeep + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef HW_MSF2_SYSREG_H +#define HW_MSF2_SYSREG_H + +#include "hw/sysbus.h" +#include "hw/hw.h" + +enum { + ESRAM_CR =3D 0x00 / 4, + ESRAM_MAX_LAT, + DDR_CR, + ENVM_CR, + ENVM_REMAP_BASE_CR, + ENVM_REMAP_FAB_CR, + CC_CR, + CC_REGION_CR, + CC_LOCK_BASE_ADDR_CR, + CC_FLUSH_INDX_CR, + DDRB_BUF_TIMER_CR, + DDRB_NB_ADDR_CR, + DDRB_NB_SIZE_CR, + DDRB_CR, + + SOFT_RESET_CR =3D 0x48 / 4, + M3_CR, + + GPIO_SYSRESET_SEL_CR =3D 0x58 / 4, + + MDDR_CR =3D 0x60 / 4, + + MSSDDR_PLL_STATUS_LOW_CR =3D 0x90 / 4, + MSSDDR_PLL_STATUS_HIGH_CR, + MSSDDR_FACC1_CR, + MSSDDR_FACC2_CR, + + MSSDDR_PLL_STATUS =3D 0x150 / 4, + +}; + +#define MSF2_SYSREG_MMIO_SIZE 0x300 +#define MSF2_SYSREG_NUM_REGS (MSF2_SYSREG_MMIO_SIZE / 4) + +#define TYPE_MSF2_SYSREG "msf2-sysreg" +#define MSF2_SYSREG(obj) OBJECT_CHECK(MSF2SysregState, (obj), TYPE_MSF2_S= YSREG) + +typedef struct MSF2SysregState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + + uint32_t regs[MSF2_SYSREG_NUM_REGS]; +} MSF2SysregState; + +#endif /* HW_MSF2_SYSREG_H */ --=20 2.5.0 From nobody Thu Mar 28 14:52:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1493398576707863.0060330846652; Fri, 28 Apr 2017 09:56:16 -0700 (PDT) Received: from localhost ([::1]:38044 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d49Bn-0006NM-0t for importer@patchew.org; Fri, 28 Apr 2017 12:56:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60834) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d498P-0003t8-JQ for qemu-devel@nongnu.org; Fri, 28 Apr 2017 12:52:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d498N-00069e-77 for qemu-devel@nongnu.org; Fri, 28 Apr 2017 12:52:45 -0400 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:35219) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d498M-00068u-UX; Fri, 28 Apr 2017 12:52:43 -0400 Received: by mail-pg0-x241.google.com with SMTP id s1so3752217pgc.2; Fri, 28 Apr 2017 09:52:42 -0700 (PDT) Received: from localhost.localdomain ([124.123.70.3]) by smtp.gmail.com with ESMTPSA id r86sm11383528pfb.24.2017.04.28.09.52.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 28 Apr 2017 09:52:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3Ilyuvl/6XSB0OArCmJlr142tnvzIes9sdf1yxe6DVc=; b=krDyrOU+kDIZkf12MC5djaUWUM/F63g0Jrl+Zw/DfhHjBrvHOiQJ7FaLn/rdCqxEMP 0CNJf+jsYOZ0aIC3NfyvKFQ2AC+Sk/voOCRrTe1ydZNzeaP57b5cagjMYHrm9iqd1NBo 2tpimj0J7S/aNhrmTGtcXs8RBxVE0Wpc8RHgfzMv+TqFXo0OiyU7m1op0Tk3s4CraWrJ RZKCJxvpIeLmy39im618G8L6WeCmPse2bhSwalAgVHu7Wyc1m2MyjK8Bc1uYEsXoPCWw 0BsdPZygLsPKY2bWANhUThFjqpe+GV0vNgMDMU8lXpz1dIU78y0wPTB8/r42qQesccNd J2pA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3Ilyuvl/6XSB0OArCmJlr142tnvzIes9sdf1yxe6DVc=; b=TdPOFAcS//KoRqzCLCE5jyl6sI84WSUrcV5MFlR6/Gdo+2sRVAiqlvajegS7b9HuTz YBtXLKPgp1Pii5glZ455T8ckzclB6j0k9U2rTkGw8OSo46Pdg54shu98cfIOFPvvFYSk VjqTZgK1MYlznMqOCcTXqS7l6i43du5FJHJadLOo+4vRjIlwDffuKg8bphPlZ1SjWrZO AA5dzNI65nYO42hBgKo8QonR4rSO03n9NbYcql02Ybd3gN48DdDz0uoQWvcaA2+SLPES bCDV4MpBWbgS6s4QlHsB3ntMnISSfqgesTo7HjPUEwjnhxfk9JHNTK3GDY0gwEod1bGO PjNg== X-Gm-Message-State: AN3rC/63gS/txIRI/ghN+2l1Hsi2N9UnVkjwnrh6sFKUdTtfJBE14Dd3 qMvpHXESkItDbQ== X-Received: by 10.84.141.3 with SMTP id 3mr9076277plu.8.1493398361813; Fri, 28 Apr 2017 09:52:41 -0700 (PDT) From: Subbaraya Sundeep To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Fri, 28 Apr 2017 22:21:51 +0530 Message-Id: <1493398313-6673-4-git-send-email-sundeep.lkml@gmail.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1493398313-6673-1-git-send-email-sundeep.lkml@gmail.com> References: <1493398313-6673-1-git-send-email-sundeep.lkml@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [Qemu-devel RFC v3 3/5] msf2: Add Smartfusion2 SPI controller X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Subbaraya Sundeep , alistair23@gmail.com, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Modelled Microsemi's Smartfusion2 SPI controller. Signed-off-by: Subbaraya Sundeep --- Hi Peter and Alistair, I created two SPI controllers as per SoC spec=20 in hw/arm/msf2_soc.c. I am assuming there has to be two busses spi0 and spi1 one for each controller. In board file (hw/arm/msf2_som.c) attached SPI flash to SPI0 controller. I am not able to understand(from hw/ssi/xilinx_spips.c) how to create two busses in hw/ssi/msf2_spi.c.=20 Please help me here. Below is the output of info qtree: (qemu) info qtree bus: main-system-bus type System dev: msf2-soc, id "" cpu-model =3D "cortex-m3" dev: msf2-spi, id "" gpio-out "sysbus-irq" 2 mmio 0000000040011000/0000000000000040 bus: spi0 type SSI dev: msf2-spi, id "" gpio-out "sysbus-irq" 2 mmio 0000000040001000/0000000000000040 bus: spi0 type SSI dev: s25sl12801, id "" gpio-in "ssi-gpio-cs" 1 nonvolatile-cfg =3D 36863 (0x8fff) spansion-cr1nv =3D 0 (0x0) spansion-cr2nv =3D 1 (0x1) spansion-cr3nv =3D 2 (0x2) spansion-cr4nv =3D 16 (0x10) drive =3D "mtd0" Thanks, Sundeep hw/ssi/Makefile.objs | 1 + hw/ssi/msf2_spi.c | 373 ++++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/ssi/msf2_spi.h | 102 +++++++++++++ 3 files changed, 476 insertions(+) create mode 100644 hw/ssi/msf2_spi.c create mode 100644 include/hw/ssi/msf2_spi.h diff --git a/hw/ssi/Makefile.objs b/hw/ssi/Makefile.objs index 487add2..86445d7 100644 --- a/hw/ssi/Makefile.objs +++ b/hw/ssi/Makefile.objs @@ -4,6 +4,7 @@ common-obj-$(CONFIG_XILINX_SPI) +=3D xilinx_spi.o common-obj-$(CONFIG_XILINX_SPIPS) +=3D xilinx_spips.o common-obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_smc.o common-obj-$(CONFIG_STM32F2XX_SPI) +=3D stm32f2xx_spi.o +common-obj-$(CONFIG_MSF2) +=3D msf2_spi.o =20 obj-$(CONFIG_OMAP) +=3D omap_spi.o obj-$(CONFIG_IMX) +=3D imx_spi.o diff --git a/hw/ssi/msf2_spi.c b/hw/ssi/msf2_spi.c new file mode 100644 index 0000000..e7ffa21 --- /dev/null +++ b/hw/ssi/msf2_spi.c @@ -0,0 +1,373 @@ +/* + * SPI controller model of Microsemi SmartFusion2. + * + * Copyright (C) 2017 Subbaraya Sundeep + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/ssi/msf2_spi.h" +#include "sysemu/sysemu.h" +#include "qemu/log.h" + +#ifndef MSF2_SPI_ERR_DEBUG +#define MSF2_SPI_ERR_DEBUG 0 +#endif + +#define DB_PRINT_L(lvl, fmt, args...) do { \ + if (MSF2_SPI_ERR_DEBUG >=3D lvl) { \ + qemu_log("%s: " fmt, __func__, ## args); \ + } \ +} while (0); + +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) + +static void txfifo_reset(MSF2SpiState *s) +{ + fifo32_reset(&s->tx_fifo); + + s->regs[R_SPI_STATUS] &=3D ~S_TXFIFOFUL; + s->regs[R_SPI_STATUS] |=3D S_TXFIFOEMP; +} + +static void rxfifo_reset(MSF2SpiState *s) +{ + fifo32_reset(&s->rx_fifo); + + s->regs[R_SPI_STATUS] &=3D ~S_RXFIFOFUL; + s->regs[R_SPI_STATUS] |=3D S_RXFIFOEMP; +} + +static void set_fifodepth(MSF2SpiState *s) +{ + int size =3D s->regs[R_SPI_DFSIZE] & FRAMESZ_MASK; + + if (0 <=3D size && size <=3D 8) { + s->fifo_depth =3D 32; + } + if (9 <=3D size && size <=3D 16) { + s->fifo_depth =3D 16; + } + if (17 <=3D size && size <=3D 32) { + s->fifo_depth =3D 8; + } +} + +static void msf2_spi_do_reset(MSF2SpiState *s) +{ + memset(s->regs, 0, sizeof s->regs); + s->regs[R_SPI_CONTROL] =3D 0x80000102; + s->regs[R_SPI_DFSIZE] =3D 0x4; + s->regs[R_SPI_STATUS] =3D 0x2440; + s->regs[R_SPI_CLKGEN] =3D 0x7; + s->regs[R_SPI_STAT8] =3D 0x7; + s->regs[R_SPI_RIS] =3D 0x0; + + s->fifo_depth =3D 4; + s->frame_count =3D 1; + s->enabled =3D false; + + rxfifo_reset(s); + txfifo_reset(s); +} + +static void update_mis(MSF2SpiState *s) +{ + uint32_t reg =3D s->regs[R_SPI_CONTROL]; + uint32_t tmp; + + /* + * form the Control register interrupt enable bits + * same as RIS, MIS and Interrupt clear registers for simplicity + */ + tmp =3D ((reg & C_INTRXOVRFLO) >> 4) | ((reg & C_INTRXDATA) >> 3) | + ((reg & C_INTTXDATA) >> 5); + s->regs[R_SPI_MIS] |=3D tmp & s->regs[R_SPI_RIS]; +} + +static void spi_update_irq(MSF2SpiState *s) +{ + int irq; + + update_mis(s); + irq =3D !!(s->regs[R_SPI_MIS]); + + qemu_set_irq(s->irq, irq); +} + +static void msf2_spi_reset(DeviceState *d) +{ + msf2_spi_do_reset(MSF2_SPI(d)); +} + +static uint64_t +spi_read(void *opaque, hwaddr addr, unsigned int size) +{ + MSF2SpiState *s =3D opaque; + uint32_t r =3D 0; + + addr >>=3D 2; + switch (addr) { + case R_SPI_RX: + s->regs[R_SPI_STATUS] &=3D ~S_RXFIFOFUL; + s->regs[R_SPI_STATUS] &=3D ~RXCHOVRF; + r =3D fifo32_pop(&s->rx_fifo); + if (fifo32_is_empty(&s->rx_fifo)) { + s->regs[R_SPI_STATUS] |=3D S_RXFIFOEMP; + } + break; + + case R_SPI_MIS: + update_mis(s); + r =3D s->regs[R_SPI_MIS]; + break; + + default: + if (addr < ARRAY_SIZE(s->regs)) { + r =3D s->regs[addr]; + } + break; + } + + DB_PRINT("addr=3D" TARGET_FMT_plx " =3D %x\n", addr * 4, r); + spi_update_irq(s); + return r; +} + +static void assert_cs(MSF2SpiState *s) +{ + qemu_set_irq(s->cs_line, 0); +} + +static void deassert_cs(MSF2SpiState *s) +{ + qemu_set_irq(s->cs_line, 1); +} + +static void spi_flush_txfifo(MSF2SpiState *s) +{ + uint32_t tx; + uint32_t rx; + bool sps =3D !!(s->regs[R_SPI_CONTROL] & C_SPS); + + /* + * Chip Select(CS) is automatically controlled by this controller. + * If SPS bit is set in Control register then CS is asserted + * until all the frames set in frame count of Control register are + * transferred. If SPS is not set then CS pulses between frames. + * Note that Slave Select register specifies which of the CS line + * has to be controlled automatically by controller. Bits SS[7:1] are = for + * masters in FPGA fabric since we model only Microcontroller subsystem + * of Smartfusion2 we control only one CS(SS[0]) line. + */ + while (!fifo32_is_empty(&s->tx_fifo) && s->frame_count) { + assert_cs(s); + + s->regs[R_SPI_STATUS] &=3D ~TXDONE; + s->regs[R_SPI_STATUS] &=3D ~RXRDY; + + tx =3D fifo32_pop(&s->tx_fifo); + DB_PRINT("data tx:%x\n", tx); + rx =3D ssi_transfer(s->spi, tx); + DB_PRINT("data rx:%x\n", rx); + + if (fifo32_num_used(&s->rx_fifo) =3D=3D s->fifo_depth) { + s->regs[R_SPI_STATUS] |=3D RXCHOVRF; + s->regs[R_SPI_RIS] |=3D RXCHOVRF; + } else { + fifo32_push(&s->rx_fifo, rx); + s->regs[R_SPI_STATUS] &=3D ~S_RXFIFOEMP; + if (fifo32_num_used(&s->rx_fifo) =3D=3D (s->fifo_depth - 1)) { + s->regs[R_SPI_STATUS] |=3D S_RXFIFOFULNXT; + } + if (fifo32_num_used(&s->rx_fifo) =3D=3D s->fifo_depth) { + s->regs[R_SPI_STATUS] |=3D S_RXFIFOFUL; + } + } + s->frame_count--; + if (!sps) { + deassert_cs(s); + assert_cs(s); + } + } + + if (!sps) { + deassert_cs(s); + } + + if (!s->frame_count) { + s->frame_count =3D (s->regs[R_SPI_CONTROL] & FMCOUNT_MASK) >> + FMCOUNT_SHIFT; + if (sps) { + deassert_cs(s); + } + s->regs[R_SPI_RIS] |=3D TXDONE; + s->regs[R_SPI_RIS] |=3D RXRDY; + s->regs[R_SPI_STATUS] |=3D TXDONE; + s->regs[R_SPI_STATUS] |=3D RXRDY; + } +} + +static void spi_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + MSF2SpiState *s =3D opaque; + uint32_t value =3D val64; + + DB_PRINT("addr=3D" TARGET_FMT_plx " =3D %x\n", addr, value); + addr >>=3D 2; + + switch (addr) { + case R_SPI_TX: + /* adding to already full FIFO */ + if (fifo32_num_used(&s->tx_fifo) =3D=3D s->fifo_depth) { + break; + } + s->regs[R_SPI_STATUS] &=3D ~S_TXFIFOEMP; + fifo32_push(&s->tx_fifo, value); + if (fifo32_num_used(&s->tx_fifo) =3D=3D (s->fifo_depth - 1)) { + s->regs[R_SPI_STATUS] |=3D S_TXFIFOFULNXT; + } + if (fifo32_num_used(&s->tx_fifo) =3D=3D s->fifo_depth) { + s->regs[R_SPI_STATUS] |=3D S_TXFIFOFUL; + } + if (s->enabled) { + spi_flush_txfifo(s); + } + break; + + case R_SPI_CONTROL: + s->regs[R_SPI_CONTROL] =3D value; + if (value & C_BIGFIFO) { + set_fifodepth(s); + } else { + s->fifo_depth =3D 4; + } + if (value & C_ENABLE) { + s->enabled =3D true; + } else { + s->enabled =3D false; + } + s->frame_count =3D (value & FMCOUNT_MASK) >> FMCOUNT_SHIFT; + if (value & C_RESET) { + msf2_spi_do_reset(s); + } + break; + + case R_SPI_DFSIZE: + if (s->enabled) { + break; + } + s->regs[R_SPI_DFSIZE] =3D value; + break; + + case R_SPI_INTCLR: + s->regs[R_SPI_INTCLR] =3D value; + if (value & TXDONE) { + s->regs[R_SPI_RIS] &=3D ~TXDONE; + } + if (value & RXRDY) { + s->regs[R_SPI_RIS] &=3D ~RXRDY; + } + if (value & RXCHOVRF) { + s->regs[R_SPI_RIS] &=3D ~RXCHOVRF; + } + break; + + case R_SPI_MIS: + case R_SPI_STATUS: + case R_SPI_RIS: + break; + + default: + if (addr < ARRAY_SIZE(s->regs)) { + s->regs[addr] =3D value; + } + break; + } + + spi_update_irq(s); +} + +static const MemoryRegionOps spi_ops =3D { + .read =3D spi_read, + .write =3D spi_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4 + } +}; + +static void msf2_spi_realize(DeviceState *dev, Error **errp) +{ + MSF2SpiState *s =3D MSF2_SPI(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + + DB_PRINT("\n"); + + s->spi =3D ssi_create_bus(dev, "spi0"); + + sysbus_init_irq(sbd, &s->irq); + ssi_auto_connect_slaves(dev, &s->cs_line, s->spi); + sysbus_init_irq(sbd, &s->cs_line); + + memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s, + TYPE_MSF2_SPI, R_SPI_MAX * 4); + sysbus_init_mmio(sbd, &s->mmio); + + fifo32_create(&s->tx_fifo, FIFO_CAPACITY); + fifo32_create(&s->rx_fifo, FIFO_CAPACITY); +} + +static const VMStateDescription vmstate_msf2_spi =3D { + .name =3D TYPE_MSF2_SPI, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_FIFO32(tx_fifo, MSF2SpiState), + VMSTATE_FIFO32(rx_fifo, MSF2SpiState), + VMSTATE_UINT32_ARRAY(regs, MSF2SpiState, R_SPI_MAX), + VMSTATE_END_OF_LIST() + } +}; + +static void msf2_spi_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D msf2_spi_realize; + dc->reset =3D msf2_spi_reset; + dc->vmsd =3D &vmstate_msf2_spi; +} + +static const TypeInfo msf2_spi_info =3D { + .name =3D TYPE_MSF2_SPI, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(MSF2SpiState), + .class_init =3D msf2_spi_class_init, +}; + +static void msf2_spi_register_types(void) +{ + type_register_static(&msf2_spi_info); +} + +type_init(msf2_spi_register_types) diff --git a/include/hw/ssi/msf2_spi.h b/include/hw/ssi/msf2_spi.h new file mode 100644 index 0000000..7f266c2 --- /dev/null +++ b/include/hw/ssi/msf2_spi.h @@ -0,0 +1,102 @@ +/* + * Microsemi SmartFusion2 SPI + * + * Copyright (c) 2017 Subbaraya Sundeep + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef HW_MSF2_SPI_H +#define HW_MSF2_SPI_H + +#include "hw/sysbus.h" +#include "hw/hw.h" +#include "hw/ssi/ssi.h" +#include "qemu/fifo32.h" + +#define FIFO_CAPACITY 32 +#define FIFO_CAPACITY 32 + +#define R_SPI_CONTROL 0 +#define R_SPI_DFSIZE 1 +#define R_SPI_STATUS 2 +#define R_SPI_INTCLR 3 +#define R_SPI_RX 4 +#define R_SPI_TX 5 +#define R_SPI_CLKGEN 6 +#define R_SPI_SS 7 +#define R_SPI_MIS 8 +#define R_SPI_RIS 9 +#define R_SPI_STAT8 15 +#define R_SPI_MAX 16 + +#define S_RXFIFOFUL (1 << 4) +#define S_RXFIFOFULNXT (1 << 5) +#define S_RXFIFOEMP (1 << 6) +#define S_RXFIFOEMPNXT (1 << 7) +#define S_TXFIFOFUL (1 << 8) +#define S_TXFIFOFULNXT (1 << 9) +#define S_TXFIFOEMP (1 << 10) +#define S_TXFIFOEMPNXT (1 << 11) +#define S_FRAMESTART (1 << 12) +#define S_SSEL (1 << 13) +#define S_ACTIVE (1 << 14) + +#define C_ENABLE (1 << 0) +#define C_MODE (1 << 1) +#define C_INTRXDATA (1 << 4) +#define C_INTTXDATA (1 << 5) +#define C_INTRXOVRFLO (1 << 6) +#define C_SPS (1 << 26) +#define C_BIGFIFO (1 << 29) +#define C_RESET (1 << 31) + +#define FRAMESZ_MASK 0x1F +#define FMCOUNT_MASK 0x00FFFF00 +#define FMCOUNT_SHIFT 8 + +#define TXDONE (1 << 0) +#define RXRDY (1 << 1) +#define RXCHOVRF (1 << 2) + +#define TYPE_MSF2_SPI "msf2-spi" +#define MSF2_SPI(obj) OBJECT_CHECK(MSF2SpiState, (obj), TYPE_MSF2_SPI) + +typedef struct MSF2SpiState { + SysBusDevice parent_obj; + + MemoryRegion mmio; + + qemu_irq irq; + + qemu_irq cs_line; + + SSIBus *spi; + + Fifo32 rx_fifo; + Fifo32 tx_fifo; + + int fifo_depth; + uint32_t frame_count; + bool enabled; + + uint32_t regs[R_SPI_MAX]; +} MSF2SpiState; + +#endif /* HW_MSF2_SPI_H */ --=20 2.5.0 From nobody Thu Mar 28 14:52:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1493398662035164.1205867292265; Fri, 28 Apr 2017 09:57:42 -0700 (PDT) Received: from localhost ([::1]:38049 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d49DA-0007kX-Mc for importer@patchew.org; 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Fri, 28 Apr 2017 09:52:44 -0700 (PDT) From: Subbaraya Sundeep To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Fri, 28 Apr 2017 22:21:52 +0530 Message-Id: <1493398313-6673-5-git-send-email-sundeep.lkml@gmail.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1493398313-6673-1-git-send-email-sundeep.lkml@gmail.com> References: <1493398313-6673-1-git-send-email-sundeep.lkml@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [Qemu-devel RFC v3 4/5] msf2: Add Smartfusion2 SoC. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Subbaraya Sundeep , alistair23@gmail.com, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Smartfusion2 SoC has hardened Microcontroller subsystem and flash based FPGA fabric. This patch adds support for Microcontroller subsystem in the SoC. Signed-off-by: Subbaraya Sundeep --- default-configs/arm-softmmu.mak | 1 + hw/arm/Makefile.objs | 2 +- hw/arm/msf2_soc.c | 194 ++++++++++++++++++++++++++++++++++++= ++++ include/hw/arm/msf2_soc.h | 62 +++++++++++++ 4 files changed, 258 insertions(+), 1 deletion(-) create mode 100644 hw/arm/msf2_soc.c create mode 100644 include/hw/arm/msf2_soc.h diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.= mak index 78d7af0..7062512 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -122,3 +122,4 @@ CONFIG_ACPI=3Dy CONFIG_SMBIOS=3Dy CONFIG_ASPEED_SOC=3Dy CONFIG_GPIO_KEY=3Dy +CONFIG_MSF2=3Dy diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index 4c5c4ee..cce2759 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -1,7 +1,7 @@ obj-y +=3D boot.o collie.o exynos4_boards.o gumstix.o highbank.o obj-$(CONFIG_DIGIC) +=3D digic_boards.o obj-y +=3D integratorcp.o mainstone.o musicpal.o nseries.o -obj-y +=3D omap_sx1.o palm.o realview.o spitz.o stellaris.o +obj-y +=3D omap_sx1.o palm.o realview.o spitz.o stellaris.o msf2_soc.o obj-y +=3D tosa.o versatilepb.o vexpress.o virt.o xilinx_zynq.o z2.o obj-$(CONFIG_ACPI) +=3D virt-acpi-build.o obj-y +=3D netduino2.o diff --git a/hw/arm/msf2_soc.c b/hw/arm/msf2_soc.c new file mode 100644 index 0000000..a470872 --- /dev/null +++ b/hw/arm/msf2_soc.c @@ -0,0 +1,194 @@ +/* + * SmartFusion2 SoC emulation. + * + * Copyright (c) 2017 Subbaraya Sundeep + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu-common.h" +#include "hw/arm/arm.h" +#include "exec/address-spaces.h" +#include "hw/char/serial.h" +#include "hw/boards.h" +#include "sysemu/block-backend.h" +#include "hw/arm/msf2_soc.h" + +#define MSF2_TIMER_BASE 0x40004000 +#define MSF2_SYSREG_BASE 0x40038000 + +#define MSF2_TIMER_IRQ0 14 +#define MSF2_TIMER_IRQ1 15 + +static const uint32_t spi_addr[MSF2_NUM_SPIS] =3D { 0x40001000 , 0x4001100= 0 }; +static const uint32_t uart_addr[MSF2_NUM_UARTS] =3D { 0x40000000 , 0x40010= 000 }; + +static const int spi_irq[MSF2_NUM_SPIS] =3D { 2, 3 }; +static const int uart_irq[MSF2_NUM_UARTS] =3D { 10, 11 }; + +static void msf2_soc_initfn(Object *obj) +{ + MSF2State *s =3D MSF2_SOC(obj); + int i; + + object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M); + qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default()); + + object_initialize(&s->sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG); + qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default()); + + object_initialize(&s->timer, sizeof(s->timer), TYPE_MSF2_TIMER); + qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default()); + + for (i =3D 0; i < MSF2_NUM_SPIS; i++) { + object_initialize(&s->spi[i], sizeof(s->spi[i]), + TYPE_MSF2_SPI); + qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); + } +} + +static void msf2_soc_realize(DeviceState *dev_soc, Error **errp) +{ + MSF2State *s =3D MSF2_SOC(dev_soc); + DeviceState *dev, *armv7m; + SysBusDevice *busdev; + Error *err =3D NULL; + int i; + + MemoryRegion *system_memory =3D get_system_memory(); + MemoryRegion *nvm =3D g_new(MemoryRegion, 1); + MemoryRegion *nvm_alias =3D g_new(MemoryRegion, 1); + MemoryRegion *sram =3D g_new(MemoryRegion, 1); + MemoryRegion *ddr =3D g_new(MemoryRegion, 1); + + memory_region_init_ram(nvm, NULL, "MSF2.envm", ENVM_SIZE, + &error_fatal); + memory_region_init_alias(nvm_alias, NULL, "MSF2.flash.alias", + nvm, 0, ENVM_SIZE); + vmstate_register_ram_global(nvm); + + memory_region_set_readonly(nvm, true); + memory_region_set_readonly(nvm_alias, true); + + memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm); + memory_region_add_subregion(system_memory, 0, nvm_alias); + + memory_region_init_ram(ddr, NULL, "MSF2.ddr", DDR_SIZE, + &error_fatal); + vmstate_register_ram_global(ddr); + memory_region_add_subregion(system_memory, DDR_BASE_ADDRESS, ddr); + + memory_region_init_ram(sram, NULL, "MSF2.sram", SRAM_SIZE, + &error_fatal); + vmstate_register_ram_global(sram); + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram); + + armv7m =3D DEVICE(&s->armv7m); + qdev_prop_set_uint32(armv7m, "num-irq", 96); + qdev_prop_set_string(armv7m, "cpu-model", s->cpu_model); + object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory(= )), + "memory", &error_abort); + object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err); + if (err !=3D NULL) { + error_propagate(errp, err); + return; + } + + for (i =3D 0; i < MSF2_NUM_UARTS; i++) { + if (serial_hds[i]) { + serial_mm_init(get_system_memory(), uart_addr[i], 2, + qdev_get_gpio_in(armv7m, uart_irq[i]), + 115200, serial_hds[i], DEVICE_NATIVE_ENDIAN); + } + } + + dev =3D DEVICE(&s->timer); + qdev_prop_set_uint32(dev, "clock-frequency", 83 * 1000000); + object_property_set_bool(OBJECT(&s->timer), true, "realized", &err); + if (err !=3D NULL) { + error_propagate(errp, err); + return; + } + busdev =3D SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE); + sysbus_connect_irq(busdev, 0, + qdev_get_gpio_in(armv7m, MSF2_TIMER_IRQ0)); + sysbus_connect_irq(busdev, 1, + qdev_get_gpio_in(armv7m, MSF2_TIMER_IRQ1)); + + dev =3D DEVICE(&s->sysreg); + object_property_set_bool(OBJECT(&s->sysreg), true, "realized", &err); + if (err !=3D NULL) { + error_propagate(errp, err); + return; + } + busdev =3D SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE); + + for (i =3D 0; i < MSF2_NUM_SPIS; i++) { + gchar *bus_name =3D g_strdup_printf("spi%d", i); + + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &er= r); + if (err !=3D NULL) { + g_free(bus_name); + error_propagate(errp, err); + return; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, + qdev_get_gpio_in(armv7m, spi_irq[i])); + + /* Alias controller SPI bus to the SoC itself */ + object_property_add_alias(OBJECT(s), bus_name, + OBJECT(&s->spi[i]), "spi0", + &error_abort); + g_free(bus_name); + } +} + +static Property msf2_soc_properties[] =3D { + DEFINE_PROP_STRING("cpu-model", MSF2State, cpu_model), + DEFINE_PROP_END_OF_LIST(), +}; + +static void msf2_soc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D msf2_soc_realize; + dc->props =3D msf2_soc_properties; +} + +static const TypeInfo msf2_soc_info =3D { + .name =3D TYPE_MSF2_SOC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(MSF2State), + .instance_init =3D msf2_soc_initfn, + .class_init =3D msf2_soc_class_init, +}; + +static void msf2_soc_types(void) +{ + type_register_static(&msf2_soc_info); +} + +type_init(msf2_soc_types) diff --git a/include/hw/arm/msf2_soc.h b/include/hw/arm/msf2_soc.h new file mode 100644 index 0000000..1184d9a --- /dev/null +++ b/include/hw/arm/msf2_soc.h @@ -0,0 +1,62 @@ +/* + * Microsemi Smartfusion2 SoC + * + * Copyright (c) 2017 Subbaraya Sundeep + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef HW_ARM_MSF2_SOC_H +#define HW_ARM_MSF2_SOC_H + +#include "hw/misc/msf2_sysreg.h" +#include "hw/timer/msf2_timer.h" +#include "hw/ssi/msf2_spi.h" +#include "hw/arm/armv7m.h" + +#define TYPE_MSF2_SOC "msf2-soc" +#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC) + +#define MSF2_NUM_SPIS 2 +#define MSF2_NUM_UARTS 2 + +#define ENVM_BASE_ADDRESS 0x60000000 +#define ENVM_SIZE (128 * 1024) + +#define DDR_BASE_ADDRESS 0xA0000000 +#define DDR_SIZE (64 * 1024 * 1024) + +#define SRAM_BASE_ADDRESS 0x20000000 +#define SRAM_SIZE (64 * 1024) + +typedef struct MSF2State { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + char *cpu_model; + + ARMv7MState armv7m; + + MSF2SysregState sysreg; + MSF2TimerState timer; + MSF2SpiState spi[MSF2_NUM_SPIS]; +} MSF2State; + +#endif --=20 2.5.0 From nobody Thu Mar 28 14:52:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1493398753931342.53278922126503; Fri, 28 Apr 2017 09:59:13 -0700 (PDT) Received: from localhost ([::1]:38054 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d49Ee-00009C-KR for importer@patchew.org; Fri, 28 Apr 2017 12:59:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60881) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d498T-0003wh-0Y for qemu-devel@nongnu.org; Fri, 28 Apr 2017 12:52:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d498R-0006Cc-TQ for qemu-devel@nongnu.org; Fri, 28 Apr 2017 12:52:49 -0400 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:33244) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d498R-0006C4-O6; Fri, 28 Apr 2017 12:52:47 -0400 Received: by mail-pg0-x242.google.com with SMTP id v20so3743076pgn.0; Fri, 28 Apr 2017 09:52:47 -0700 (PDT) Received: from localhost.localdomain ([124.123.70.3]) by smtp.gmail.com with ESMTPSA id r86sm11383528pfb.24.2017.04.28.09.52.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 28 Apr 2017 09:52:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/ZGleY/AklM7AW1THFbc8eJzJwhHSGrXZZNywEWEZ14=; b=jtRzLF+NF1HXx7sBeyy3YYpzU1EZrq/hRvPSZIprhq9vdQmBIdZEvJEWndizqd2xxb K7YlbXff37MnXLphjt9wwcWZtLHXYrxc1SuiT2Bk29aPFz1mek7x5h78D1VcX/djD3xs qMo+N4Dhjt49oZX4Rh//S0b442TGQB/mJZDx6OZI61HaoikvgwQuy+7K3gM8d+dX4Ji8 zKC1jYLfhsTRFbP+ET7ufYgZsmnCfJ3LYBFAvs+5ioYw5hlEwT+2yv4RJelAo/+H8BSf byqg9GUSizM9DnRbCqxF9+VaUEMANj6RI/Wg4w4fwy/ZmMP9exqGCEX+k069ZPUF2xsp yDPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/ZGleY/AklM7AW1THFbc8eJzJwhHSGrXZZNywEWEZ14=; b=ZaFcHno2kZr2jQmpuGQwcxNhG9X5GxBXH7Tmauewb8Ayis1oC53BTHdI9d4GPwCDcK zD608yF1n0x1gZN44sG4vZAw2jXbwnQMX2HXzHBNLQPOmxWP8rAAdcKcPep7k9/UxlGK rzySAri5yL9H1XHJxg+nZVRKjvD6M2o6wMtDVzzTwFFvAP1/Z2zNYyjAXBmEW0CsbuST 7rZF40hLZ2xRtna8K51Nw6BC66q4ZIajgaWV/0zj/QiFiBE/sFBfz7xnUnDuumDm+Ry5 4qO9m27KldZhS7T00z2kVGKwsW5LQy+QlonEEQC3oyaiZ2U3w3ZOIl5RPAxe8BnLN9ws sfCw== X-Gm-Message-State: AN3rC/55JlT8EbfMuJyC84CbHMJsd2bFYylile3nrJgYwJwGsid9AjCa Xn79Mgxo5UVniw== X-Received: by 10.84.224.70 with SMTP id a6mr16438618plt.25.1493398366838; Fri, 28 Apr 2017 09:52:46 -0700 (PDT) From: Subbaraya Sundeep To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Fri, 28 Apr 2017 22:21:53 +0530 Message-Id: <1493398313-6673-6-git-send-email-sundeep.lkml@gmail.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1493398313-6673-1-git-send-email-sundeep.lkml@gmail.com> References: <1493398313-6673-1-git-send-email-sundeep.lkml@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [Qemu-devel RFC v3 5/5] msf2: Add Emcraft's Smartfusion2 SOM kit. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Subbaraya Sundeep , alistair23@gmail.com, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Emulated Emcraft's Smartfusion2 System On Module starter kit. Signed-off-by: Subbaraya Sundeep --- hw/arm/Makefile.objs | 1 + hw/arm/msf2_som.c | 68 ++++++++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 69 insertions(+) create mode 100644 hw/arm/msf2_som.c diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index cce2759..d0b7093 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -5,6 +5,7 @@ obj-y +=3D omap_sx1.o palm.o realview.o spitz.o stellaris.o= msf2_soc.o obj-y +=3D tosa.o versatilepb.o vexpress.o virt.o xilinx_zynq.o z2.o obj-$(CONFIG_ACPI) +=3D virt-acpi-build.o obj-y +=3D netduino2.o +obj-y +=3D msf2_som.o obj-y +=3D sysbus-fdt.o =20 obj-y +=3D armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o diff --git a/hw/arm/msf2_som.c b/hw/arm/msf2_som.c new file mode 100644 index 0000000..c41edd5 --- /dev/null +++ b/hw/arm/msf2_som.c @@ -0,0 +1,68 @@ +/* + * SmartFusion2 SOM starter kit(from Emcraft) emulation. + * + * Copyright (c) 2017 Subbaraya Sundeep + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/boards.h" +#include "hw/arm/msf2_soc.h" +#include "hw/arm/arm.h" + +static void msf2_init(MachineState *machine) +{ + DeviceState *dev; + DeviceState *spi_flash; + MSF2State *soc; + DriveInfo *dinfo =3D drive_get_next(IF_MTD); + qemu_irq cs_line; + SSIBus *spi_bus; + + dev =3D qdev_create(NULL, TYPE_MSF2_SOC); + qdev_prop_set_string(dev, "cpu-model", "cortex-m3"); + object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal); + + soc =3D MSF2_SOC(dev); + + /* Attach SPI flash to SPI0 controller */ + spi_bus =3D (SSIBus *)qdev_get_child_bus(dev, "spi0"); + spi_flash =3D ssi_create_slave_no_init(spi_bus, "s25sl12801"); + qdev_prop_set_uint8(spi_flash, "spansion-cr2nv", 1); + if (dinfo) { + qdev_prop_set_drive(spi_flash, "drive", blk_by_legacy_dinfo(dinfo), + &error_fatal); + } + qdev_init_nofail(spi_flash); + cs_line =3D qdev_get_gpio_in_named(spi_flash, SSI_GPIO_CS, 0); + sysbus_connect_irq(SYS_BUS_DEVICE(&soc->spi[0]), 1, cs_line); + + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, + ENVM_SIZE); +} + +static void msf2_machine_init(MachineClass *mc) +{ + mc->desc =3D "SmartFusion2 SOM kit from Emcraft"; + mc->init =3D msf2_init; +} + +DEFINE_MACHINE("smartfusion2-som", msf2_machine_init) --=20 2.5.0