From nobody Mon Feb 9 17:24:36 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1493391958965152.16667634232385; Fri, 28 Apr 2017 08:05:58 -0700 (PDT) Received: from localhost ([::1]:37486 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d47T3-0006k4-IF for importer@patchew.org; Fri, 28 Apr 2017 11:05:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53205) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d47NA-0002A8-PS for qemu-devel@nongnu.org; Fri, 28 Apr 2017 10:59:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d47N9-0006zG-FL for qemu-devel@nongnu.org; Fri, 28 Apr 2017 10:59:52 -0400 Received: from greensocs.com ([193.104.36.180]:60096) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d47N9-0006z0-51 for qemu-devel@nongnu.org; Fri, 28 Apr 2017 10:59:51 -0400 Received: from localhost (localhost [127.0.0.1]) by greensocs.com (Postfix) with ESMTP id 6A39F40C5B7; Fri, 28 Apr 2017 16:59:50 +0200 (CEST) Received: from greensocs.com ([127.0.0.1]) by localhost (gs-01.greensocs.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 7ypWzcfc_UVg; Fri, 28 Apr 2017 16:59:49 +0200 (CEST) Received: from corsair.home (bd231-7-88-127-3-24.fbx.proxad.net [88.127.3.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: fred.konrad@greensocs.com) by greensocs.com (Postfix) with ESMTPSA id BC5F540C5A4; Fri, 28 Apr 2017 16:59:48 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1493391590; bh=URFO4OyUR3BwIwKRJ53g9mtlt3ZynO6etlEpERIHuM0=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=7S0MYEVejaXHVAMt97CWoOxdKflw5gUPl0lm+SI8ry4INZs4mefvAygIqFcGRla0s o+OlRRSCi4eIVeMrA6saVkdO6YIxZAgPArAG8TCW5Ia8pk4z9Azqcw3GtXvKRZfOkX 5rocDN9+1G1ZsciOg0qj4iWY0uvye8xfZJ278mwk= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1493391589; bh=URFO4OyUR3BwIwKRJ53g9mtlt3ZynO6etlEpERIHuM0=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=TjckvO4dwnpV3s5PHK7fEBVoqVFCjOWD3esGhflVW5LXqvVq7yBIjdMKmjcsmibcU NNUMhYgvyvz7/ej1S9UM7oPDzaJ79FbPL45qGX1HcN3dV7G+/z4vGp3z8RJCqFI9oc TjGIxVa9yA2fvFrrFBi1XlFhD6vyupupxrgyDBxw= From: fred.konrad@greensocs.com To: qemu-devel@nongnu.org Date: Fri, 28 Apr 2017 16:59:36 +0200 Message-Id: <1493391576-29401-8-git-send-email-fred.konrad@greensocs.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1493391576-29401-1-git-send-email-fred.konrad@greensocs.com> References: <1493391576-29401-1-git-send-email-fred.konrad@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH V3 7/7] xilinx_spips: allow mmio execution X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, mark.burton@greensocs.com, alistair.francis@xilinx.com, clg@kaod.org, pbonzini@redhat.com, fred.konrad@greensocs.com, rth@twiddle.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: KONRAD Frederic This allows to execute from the lqspi area. When the request_ptr is called the device loads 1024bytes from the SPI devi= ce. Then this code can be executed by the guest. Reviewed-by: Edgar E. Iglesias Signed-off-by: KONRAD Frederic --- hw/ssi/xilinx_spips.c | 74 ++++++++++++++++++++++++++++++++++++++---------= ---- 1 file changed, 55 insertions(+), 19 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index da8adfa..e833028 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -496,6 +496,18 @@ static const MemoryRegionOps spips_ops =3D { .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 +static void xilinx_qspips_invalidate_mmio_ptr(XilinxQSPIPS *q) +{ + XilinxSPIPS *s =3D &q->parent_obj; + + if (q->lqspi_cached_addr !=3D ~0ULL) { + /* Invalidate the current mapped mmio */ + memory_region_invalidate_mmio_ptr(&s->mmlqspi, q->lqspi_cached_add= r, + LQSPI_CACHE_SIZE); + q->lqspi_cached_addr =3D ~0ULL; + } +} + static void xilinx_qspips_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { @@ -505,7 +517,7 @@ static void xilinx_qspips_write(void *opaque, hwaddr ad= dr, addr >>=3D 2; =20 if (addr =3D=3D R_LQSPI_CFG) { - q->lqspi_cached_addr =3D ~0ULL; + xilinx_qspips_invalidate_mmio_ptr(q); } } =20 @@ -517,27 +529,20 @@ static const MemoryRegionOps qspips_ops =3D { =20 #define LQSPI_CACHE_SIZE 1024 =20 -static uint64_t -lqspi_read(void *opaque, hwaddr addr, unsigned int size) +static void lqspi_load_cache(void *opaque, hwaddr addr) { - int i; XilinxQSPIPS *q =3D opaque; XilinxSPIPS *s =3D opaque; - uint32_t ret; - - if (addr >=3D q->lqspi_cached_addr && - addr <=3D q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { - uint8_t *retp =3D &q->lqspi_buf[addr - q->lqspi_cached_addr]; - ret =3D cpu_to_le32(*(uint32_t *)retp); - DB_PRINT_L(1, "addr: %08x, data: %08x\n", (unsigned)addr, - (unsigned)ret); - return ret; - } else { - int flash_addr =3D (addr / num_effective_busses(s)); - int slave =3D flash_addr >> LQSPI_ADDRESS_BITS; - int cache_entry =3D 0; - uint32_t u_page_save =3D s->regs[R_LQSPI_STS] & ~LQSPI_CFG_U_PAGE; - + int i; + int flash_addr =3D ((addr & ~(LQSPI_CACHE_SIZE - 1)) + / num_effective_busses(s)); + int slave =3D flash_addr >> LQSPI_ADDRESS_BITS; + int cache_entry =3D 0; + uint32_t u_page_save =3D s->regs[R_LQSPI_STS] & ~LQSPI_CFG_U_PAGE; + + if (addr < q->lqspi_cached_addr || + addr > q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { + xilinx_qspips_invalidate_mmio_ptr(q); s->regs[R_LQSPI_STS] &=3D ~LQSPI_CFG_U_PAGE; s->regs[R_LQSPI_STS] |=3D slave ? LQSPI_CFG_U_PAGE : 0; =20 @@ -589,12 +594,43 @@ lqspi_read(void *opaque, hwaddr addr, unsigned int si= ze) xilinx_spips_update_cs_lines(s); =20 q->lqspi_cached_addr =3D flash_addr * num_effective_busses(s); + } +} + +static void *lqspi_request_mmio_ptr(void *opaque, hwaddr addr, unsigned *s= ize, + unsigned *offset) +{ + XilinxQSPIPS *q =3D opaque; + hwaddr offset_within_the_region =3D addr & ~(LQSPI_CACHE_SIZE - 1); + + lqspi_load_cache(opaque, offset_within_the_region); + *size =3D LQSPI_CACHE_SIZE; + *offset =3D offset_within_the_region; + return q->lqspi_buf; +} + +static uint64_t +lqspi_read(void *opaque, hwaddr addr, unsigned int size) +{ + XilinxQSPIPS *q =3D opaque; + uint32_t ret; + + if (addr >=3D q->lqspi_cached_addr && + addr <=3D q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { + uint8_t *retp =3D &q->lqspi_buf[addr - q->lqspi_cached_addr]; + ret =3D cpu_to_le32(*(uint32_t *)retp); + DB_PRINT_L(1, "addr: %08x, data: %08x\n", (unsigned)addr, + (unsigned)ret); + return ret; + } else { + lqspi_load_cache(opaque, addr); return lqspi_read(opaque, addr, size); } } =20 static const MemoryRegionOps lqspi_ops =3D { .read =3D lqspi_read, + .request_ptr =3D lqspi_request_mmio_ptr, .endianness =3D DEVICE_NATIVE_ENDIAN, .valid =3D { .min_access_size =3D 1, --=20 1.8.3.1