From nobody Mon Feb 9 02:28:06 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1493051793934718.2291071104607; Mon, 24 Apr 2017 09:36:33 -0700 (PDT) Received: from localhost ([::1]:45070 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d2gyW-0007di-KK for importer@patchew.org; Mon, 24 Apr 2017 12:36:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57807) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d2gvx-0005Tu-32 for qemu-devel@nongnu.org; Mon, 24 Apr 2017 12:33:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d2gvw-00036a-8t for qemu-devel@nongnu.org; Mon, 24 Apr 2017 12:33:53 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36910) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d2gvq-00031J-RN; Mon, 24 Apr 2017 12:33:46 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1d2gvg-0002pF-RV; Mon, 24 Apr 2017 17:33:36 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 24 Apr 2017 17:33:33 +0100 Message-Id: <1493051615-30715-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1493051615-30715-1-git-send-email-peter.maydell@linaro.org> References: <1493051615-30715-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [RFC 1/3] arm: Use the mmu_idx we're passed in arm_cpu_do_unaligned_access() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E. Iglesias" , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When identifying the DFSR format for an alignment fault, use the mmu index that we are passed, rather than calling cpu_mmu_index() to get the mmu index for the current CPU state. This doesn't actually make any difference since the only cases where the current MMU index differs from the index used for the load are the "unprivileged load/store" instructions, and in that case the mmu index may differ but the translation regime is the same (apart from the "use from Hyp mode" case which is UNPREDICTABLE). However it's the more logical thing to do. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/op_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 156b825..de24815 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -208,7 +208,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr va= ddr, /* the DFSR for an alignment fault depends on whether we're using * the LPAE long descriptor format, or the short descriptor format */ - if (arm_s1_regime_using_lpae_format(env, cpu_mmu_index(env, false))) { + if (arm_s1_regime_using_lpae_format(env, mmu_idx)) { env->exception.fsr =3D (1 << 9) | 0x21; } else { env->exception.fsr =3D 0x1; --=20 2.7.4