From nobody Sun Apr 28 02:37:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 149262384340670.25867951048019; Wed, 19 Apr 2017 10:44:03 -0700 (PDT) Received: from localhost ([::1]:49617 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d0te5-0001VR-RU for importer@patchew.org; Wed, 19 Apr 2017 13:44:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43931) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d0tc3-0008BY-RE for qemu-devel@nongnu.org; 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charset="utf-8" A53 advertises ARM_FEATURE_PMU, but wasn't initializing pmceid[01] Signed-off-by: Aaron Lindsay --- target/arm/cpu.c | 2 +- target/arm/cpu64.c | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 04b062c..921b028 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1342,7 +1342,7 @@ static void cortex_a15_initfn(Object *obj) cpu->id_pfr0 =3D 0x00001131; cpu->id_pfr1 =3D 0x00011011; cpu->id_dfr0 =3D 0x02010555; - cpu->pmceid0 =3D 0x0000000; + cpu->pmceid0 =3D 0x00000000; cpu->pmceid1 =3D 0x00000000; cpu->id_afr0 =3D 0x00000000; cpu->id_mmfr0 =3D 0x10201105; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 670c07a..7b1642e 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -198,6 +198,8 @@ static void aarch64_a53_initfn(Object *obj) cpu->id_isar5 =3D 0x00011121; cpu->id_aa64pfr0 =3D 0x00002222; cpu->id_aa64dfr0 =3D 0x10305106; + cpu->pmceid0 =3D 0x00000000; + cpu->pmceid1 =3D 0x00000000; cpu->id_aa64isar0 =3D 0x00011120; cpu->id_aa64mmfr0 =3D 0x00001122; /* 40 bit physical addr */ cpu->dbgdidr =3D 0x3516d000; --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From nobody Sun Apr 28 02:37:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1492623828232488.81815960532344; Wed, 19 Apr 2017 10:43:48 -0700 (PDT) Received: from localhost ([::1]:49615 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d0tdp-0001Fk-Hw for importer@patchew.org; Wed, 19 Apr 2017 13:43:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43928) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d0tc3-0008BV-Oh for qemu-devel@nongnu.org; Wed, 19 Apr 2017 13:41:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d0tc2-0004NV-Lp for qemu-devel@nongnu.org; Wed, 19 Apr 2017 13:41:55 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:37494) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1d0tby-0004Kl-E2; Wed, 19 Apr 2017 13:41:50 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 8408B6110F; Wed, 19 Apr 2017 17:41:49 +0000 (UTC) Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 8BE71610DB; Wed, 19 Apr 2017 17:41:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1492623709; bh=JglSadC0Al4BPQ25hgChOtMpAlVa9OJ8BceFBOsPFIs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=e8BlNJVfnPju4lBlapJsz226A4HuqhGTfYHR6qND/ngjo8H9MWA8KNoZ+Epq+JYmz u75wH8LH5DoH/tuP2iTZMOko/2srAP7LSWBjUBZHcvnV1QlVi3O4mCAxvQ7DXkxMOt fzgnW3oNTSdESrp7jPOE7E5Qywqxv1oZBI2jYLlc= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1492623709; bh=JglSadC0Al4BPQ25hgChOtMpAlVa9OJ8BceFBOsPFIs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=e8BlNJVfnPju4lBlapJsz226A4HuqhGTfYHR6qND/ngjo8H9MWA8KNoZ+Epq+JYmz u75wH8LH5DoH/tuP2iTZMOko/2srAP7LSWBjUBZHcvnV1QlVi3O4mCAxvQ7DXkxMOt fzgnW3oNTSdESrp7jPOE7E5Qywqxv1oZBI2jYLlc= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 8BE71610DB Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: Peter Maydell , qemu-arm@nongnu.org Date: Wed, 19 Apr 2017 13:41:13 -0400 Message-Id: <1492623684-25799-3-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1492623684-25799-1-git-send-email-alindsay@codeaurora.org> References: <1492623684-25799-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH 02/13] target/arm: Check PMCNTEN for whether PMCCNTR is enabled X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mspradli@codeaurora.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8cb7a94..8888391 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -964,7 +964,7 @@ static inline bool arm_ccnt_enabled(CPUARMState *env) { /* This does not support checking PMCCFILTR_EL0 register */ =20 - if (!(env->cp15.c9_pmcr & PMCRE)) { + if (!(env->cp15.c9_pmcr & PMCRE) || !(env->cp15.c9_pmcnten & (1 << 31)= )) { return false; } =20 --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From nobody Sun Apr 28 02:37:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1492623867887957.5749534079071; Wed, 19 Apr 2017 10:44:27 -0700 (PDT) Received: from localhost ([::1]:49618 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d0teU-0001rM-GA for importer@patchew.org; Wed, 19 Apr 2017 13:44:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43945) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d0tc4-0008CD-7d for qemu-devel@nongnu.org; Wed, 19 Apr 2017 13:41:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d0tc2-0004Nd-TV for qemu-devel@nongnu.org; Wed, 19 Apr 2017 13:41:56 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:37562) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1d0tbz-0004LQ-Dy; Wed, 19 Apr 2017 13:41:51 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 7F499610DB; Wed, 19 Apr 2017 17:41:50 +0000 (UTC) Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 7411B61112; Wed, 19 Apr 2017 17:41:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1492623710; bh=Ia3sU4E67QVZjgPv1oIPVXh5d7mskpcdU0b7G/qfj1s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QygXrUh3YOjPC3R/luXtW+VaGf6sazQGIHFkERUQbKj8oOPSTad39Ppyw/njFiu9H 0yEn/MyEP7W+7FDwfpHBa27OVYR5c1lzztJ0Qk9QyoiBuw1r4gumPSLjqkufYw7/Q8 J+ZKIdzTkS/nfTBfoZFs3ILRIB868cJPDW2jneIc= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1492623710; bh=Ia3sU4E67QVZjgPv1oIPVXh5d7mskpcdU0b7G/qfj1s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QygXrUh3YOjPC3R/luXtW+VaGf6sazQGIHFkERUQbKj8oOPSTad39Ppyw/njFiu9H 0yEn/MyEP7W+7FDwfpHBa27OVYR5c1lzztJ0Qk9QyoiBuw1r4gumPSLjqkufYw7/Q8 J+ZKIdzTkS/nfTBfoZFs3ILRIB868cJPDW2jneIc= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 7411B61112 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: Peter Maydell , qemu-arm@nongnu.org Date: Wed, 19 Apr 2017 13:41:14 -0400 Message-Id: <1492623684-25799-4-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1492623684-25799-1-git-send-email-alindsay@codeaurora.org> References: <1492623684-25799-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH 03/13] target/arm: Reorganize PMCCNTR read, write, sync X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mspradli@codeaurora.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" pmccntr_read and pmccntr_write contained duplicate code that was already being handled by pmccntr_sync. This also moves the calls to get the clock inside the 'if' statement so they are not executed if not needed. Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 55 ++++++++++++++++---------------------------------= ---- 1 file changed, 16 insertions(+), 39 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8888391..390256b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -973,17 +973,18 @@ static inline bool arm_ccnt_enabled(CPUARMState *env) =20 void pmccntr_sync(CPUARMState *env) { - uint64_t temp_ticks; + if (arm_ccnt_enabled(env) && + !pmu_counter_filtered(env, env->cp15.pmccfiltr_el0)) { + uint64_t temp_ticks; =20 - temp_ticks =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); + temp_ticks =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); =20 - if (env->cp15.c9_pmcr & PMCRD) { - /* Increment once every 64 processor clock cycles */ - temp_ticks /=3D 64; - } + if (env->cp15.c9_pmcr & PMCRD) { + /* Increment once every 64 processor clock cycles */ + temp_ticks /=3D 64; + } =20 - if (arm_ccnt_enabled(env)) { env->cp15.c15_ccnt =3D temp_ticks - env->cp15.c15_ccnt; } } @@ -1007,21 +1008,11 @@ static void pmcr_write(CPUARMState *env, const ARMC= PRegInfo *ri, =20 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) { - uint64_t total_ticks; - - if (!arm_ccnt_enabled(env)) { - /* Counter is disabled, do not change value */ - return env->cp15.c15_ccnt; - } - - total_ticks =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); - - if (env->cp15.c9_pmcr & PMCRD) { - /* Increment once every 64 processor clock cycles */ - total_ticks /=3D 64; - } - return total_ticks - env->cp15.c15_ccnt; + uint64_t ret; + pmccntr_sync(env); + ret =3D env->cp15.c15_ccnt; + pmccntr_sync(env); + return ret; } =20 static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1038,22 +1029,8 @@ static void pmselr_write(CPUARMState *env, const ARM= CPRegInfo *ri, static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - uint64_t total_ticks; - - if (!arm_ccnt_enabled(env)) { - /* Counter is disabled, set the absolute value */ - env->cp15.c15_ccnt =3D value; - return; - } - - total_ticks =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); - - if (env->cp15.c9_pmcr & PMCRD) { - /* Increment once every 64 processor clock cycles */ - total_ticks /=3D 64; - } - env->cp15.c15_ccnt =3D total_ticks - value; + env->cp15.c15_ccnt =3D value; + pmccntr_sync(env); } =20 static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. 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charset="utf-8" This is in preparation for enabling counters other than PMCCNTR Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 390256b..e8189b8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -30,11 +30,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_= ulong address, hwaddr *phys_ptr, MemTxAttrs *txattrs, int = *prot, target_ulong *page_size_ptr, uint32_t *fsr, ARMMMUFaultInfo *fi); - -/* Definitions for the PMCCNTR and PMCR registers */ -#define PMCRD 0x8 -#define PMCRC 0x4 -#define PMCRE 0x1 #endif =20 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) @@ -876,6 +871,17 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { REGINFO_SENTINEL }; =20 +/* Definitions for the PMU registers */ +#define PMCRN 0xf800 +#define PMCRN_SHIFT 11 +#define PMCRD 0x8 +#define PMCRC 0x4 +#define PMCRE 0x1 + +#define PMU_NUM_COUNTERS(env) ((env->cp15.c9_pmcr & PMCRN) >> PMCRN_SHIFT) +/* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */ +#define PMU_COUNTER_MASK(env) ((1 << 31) | ((1 << PMU_NUM_COUNTERS(env)) -= 1)) + static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *r= i, bool isread) { @@ -1060,14 +1066,14 @@ static void pmccfiltr_write(CPUARMState *env, const= ARMCPRegInfo *ri, static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - value &=3D (1 << 31); + value &=3D (PMU_COUNTER_MASK(env) | (1 << 31)); env->cp15.c9_pmcnten |=3D value; } =20 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - value &=3D (1 << 31); + value &=3D (PMU_COUNTER_MASK(env) | (1 << 31)); env->cp15.c9_pmcnten &=3D ~value; } =20 @@ -1115,14 +1121,14 @@ static void pmintenset_write(CPUARMState *env, cons= t ARMCPRegInfo *ri, uint64_t value) { /* We have no event counters so only the C bit can be changed */ - value &=3D (1 << 31); + value &=3D PMU_COUNTER_MASK(env); env->cp15.c9_pminten |=3D value; } =20 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - value &=3D (1 << 31); + value &=3D PMU_COUNTER_MASK(env); env->cp15.c9_pminten &=3D ~value; } =20 --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From nobody Sun Apr 28 02:37:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1492624000408331.4832867390098; Wed, 19 Apr 2017 10:46:40 -0700 (PDT) Received: from localhost ([::1]:49634 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d0tgc-0003nB-E9 for importer@patchew.org; Wed, 19 Apr 2017 13:46:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43988) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d0tc4-0008Cr-Sg for qemu-devel@nongnu.org; Wed, 19 Apr 2017 13:41:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d0tc3-0004OS-ME for qemu-devel@nongnu.org; Wed, 19 Apr 2017 13:41:56 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:37654) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1d0tc1-0004M7-3M; Wed, 19 Apr 2017 13:41:53 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 3B3ED610DB; Wed, 19 Apr 2017 17:41:52 +0000 (UTC) Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 3441B610D4; Wed, 19 Apr 2017 17:41:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1492623712; bh=rhqbJ39KYkzAH5VJWU/sowpPX/lF18hOLxDCI1xKXFA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nONByaA5jQSEum8w7195N0dtzKKJYp02z+O5rYE4Ky4blqfMGvnbTT0+NgIIDQ+Wj JXucVf5lsdN1b0mi+toyjY7qXTbcO4b228U6IsS5j9GyqBWLKB7FF1RJpkW6vaKTWY Q4QVBStNZ9Z/1jHsQ5HI7JAExR8B7iRzya2eNOHw= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1492623711; bh=rhqbJ39KYkzAH5VJWU/sowpPX/lF18hOLxDCI1xKXFA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CHOdmFrv7QZBEbacvrIwG1rjy4gmE5Ft+OJKUIa7jOTCFVl20P7gXmGCfjvu6R+M+ uUN55KJDKJ97LqfyswWzQsaK3U+1PmX29BiRGIm0xAfbsNURwryCT4VROnmxjLbPvn /lk/OokLE+J63p3zRVdVpGikOiXfclYHpOwL+eRk= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 3441B610D4 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: Peter Maydell , qemu-arm@nongnu.org Date: Wed, 19 Apr 2017 13:41:16 -0400 Message-Id: <1492623684-25799-6-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1492623684-25799-1-git-send-email-alindsay@codeaurora.org> References: <1492623684-25799-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH 05/13] target/arm: Allow AArch32 access for PMCCFILTR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mspradli@codeaurora.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Also fix the existing bitmask for writes. Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index e8189b8..530fc7c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1059,10 +1059,25 @@ static void pmccfiltr_write(CPUARMState *env, const= ARMCPRegInfo *ri, uint64_t value) { pmccntr_sync(env); - env->cp15.pmccfiltr_el0 =3D value & 0x7E000000; + env->cp15.pmccfiltr_el0 =3D value & 0xfc000000; pmccntr_sync(env); } =20 +static void pmccfiltr_write_a32(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + pmccntr_sync(env); + env->cp15.pmccfiltr_el0 =3D (env->cp15.pmccfiltr_el0 & 0x04000000) | + (value & 0xf8000000); /* M is not visible in AArch32 */ + pmccntr_sync(env); +} + +static uint64_t pmccfiltr_read_a32(CPUARMState *env, const ARMCPRegInfo *r= i) +{ + /* M is not visible in AArch32 */ + return env->cp15.pmccfiltr_el0 & 0xf8000000; +} + static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1280,6 +1295,12 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .type =3D ARM_CP_IO, .readfn =3D pmccntr_read, .writefn =3D pmccntr_write, }, #endif + { .name =3D "PMCCFILTR", .cp =3D 15, .opc1 =3D 0, .crn =3D 14, .crm = =3D 15, .opc2 =3D 7, + .writefn =3D pmccfiltr_write_a32, .readfn =3D pmccfiltr_read_a32, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.pmccfiltr_el0), + .resetvalue =3D 0, }, { .name =3D "PMCCFILTR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 15, .opc2 =3D 7, .writefn =3D pmccfiltr_write, --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From nobody Sun Apr 28 02:37:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1492624152181329.30740960518744; Wed, 19 Apr 2017 10:49:12 -0700 (PDT) Received: from localhost ([::1]:49654 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d0tj3-0005sG-RO for importer@patchew.org; Wed, 19 Apr 2017 13:49:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44085) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d0tc8-0008HR-Eb for qemu-devel@nongnu.org; Wed, 19 Apr 2017 13:42:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d0tc6-0004Qa-PT for qemu-devel@nongnu.org; Wed, 19 Apr 2017 13:42:00 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:37732) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1d0tc2-0004Mw-Rs; Wed, 19 Apr 2017 13:41:55 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id DF2846110D; Wed, 19 Apr 2017 17:41:53 +0000 (UTC) Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 116D5610DA; Wed, 19 Apr 2017 17:41:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1492623713; bh=o/HCWk+Dr1/2IiIoWTp7qo2KOLb17DcUYdGu3PSfWJs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Wh6RpaqJhIRlwUkNS+YyiGNBWAIKcfBwZvSoxmr2gs29HSFm2+M2Wxtm9sswe9fve Bk9VwTXR9Mk2FI1uLjPNucZknXQcEUmlyZmuvUJr4PtCFQwPjWoopJn4aQi95h+rO6 vbn5mMe6OCzSLTjbU+PfQ09CLDItjXhPso3aZfOQ= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1492623712; bh=o/HCWk+Dr1/2IiIoWTp7qo2KOLb17DcUYdGu3PSfWJs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QWNLON/0GmvLTNrH6WJ16yxVfDhPri8gRK6iqYXMI07YhxFVV6C3Wm9lghJfrIkyF E+Y2PqoOHw8j8b1QAbipon7cpNsxgR3uSuHPgjPmISnlwpHWS41ayz9p7QO22Pyl27 U0ump8aFvrLxgnFgnFg/pKVeewAz4Xyjz2Ag5VAY= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 116D5610DA Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: Peter Maydell , qemu-arm@nongnu.org Date: Wed, 19 Apr 2017 13:41:17 -0400 Message-Id: <1492623684-25799-7-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1492623684-25799-1-git-send-email-alindsay@codeaurora.org> References: <1492623684-25799-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH 06/13] target/arm: Filter cycle counter based on PMCCFILTR_EL0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mspradli@codeaurora.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The pmu_counter_filtered and pmu_sync functions are generic (as opposed to PMCCNTR-specific) to allow for the implementation of other events. RFC: I know that many of the locations of the calls to pmu_sync are problematic when icount is enabled because can_do_io will not be set. The documentation says that for deterministic execution, IO must only be performed by the last instruction of a thread block. Because cpu_handle_interrupt() and cpu_handle_exception() are actually made outside of a thread block, is it safe to set can_do_io=3D1 for them to allow this to succeed? Is there a better mechanism for handling this? Signed-off-by: Aaron Lindsay --- target/arm/cpu.c | 4 +++ target/arm/cpu.h | 15 +++++++++++ target/arm/helper.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++= +--- target/arm/kvm64.c | 2 ++ target/arm/machine.c | 2 ++ target/arm/op_helper.c | 4 +++ 6 files changed, 97 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 921b028..44c965c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -139,6 +139,8 @@ static void arm_cpu_reset(CPUState *s) env->iwmmxt.cregs[ARM_IWMMXT_wCID] =3D 0x69051000 | 'Q'; } =20 + pmu_sync(env); /* Surround writes to uncached_cpsr, pstate, and aarch6= 4 */ + if (arm_feature(env, ARM_FEATURE_AARCH64)) { /* 64 bit CPUs always start in 64 bit mode */ env->aarch64 =3D 1; @@ -180,6 +182,8 @@ static void arm_cpu_reset(CPUState *s) env->uncached_cpsr =3D ARM_CPU_MODE_SVC; env->daif =3D PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; =20 + pmu_sync(env); /* Surround writes to uncached_cpsr, pstate, and aarch6= 4 */ + if (arm_feature(env, ARM_FEATURE_M)) { uint32_t initial_msp; /* Loaded from 0x0 */ uint32_t initial_pc; /* Loaded from 0x4 */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a8aabce..ae2a294 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -767,6 +767,19 @@ int cpu_arm_signal_handler(int host_signum, void *pinf= o, */ void pmccntr_sync(CPUARMState *env); =20 +/** + * pmu_sync + * @env: CPUARMState + * + * Synchronises all PMU counters. This must always be called twice, once b= efore + * any action that might affect the filtering of all counters and again + * afterwards. The function is used to swap the state of the registers if + * required. This only happens when not in user mode (!CONFIG_USER_ONLY). = Any + * writes to env's aarch64, pstate, uncached_cpsr, cp15.scr_el3, or + * cp15.hcr_el2 must be protected by calls to this function. + */ +void pmu_sync(CPUARMState *env); + /* SCTLR bit meanings. Several bits have been reused in newer * versions of the architecture; in that case we define constants * for both old and new bit meanings. Code which tests against those @@ -947,7 +960,9 @@ static inline void pstate_write(CPUARMState *env, uint3= 2_t val) env->CF =3D (val >> 29) & 1; env->VF =3D (val << 3) & 0x80000000; env->daif =3D val & PSTATE_DAIF; + pmu_sync(env); env->pstate =3D val & ~CACHED_PSTATE_BITS; + pmu_sync(env); } =20 /* Return the current CPSR value. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 530fc7c..bf9f164 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -878,6 +878,15 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { #define PMCRC 0x4 #define PMCRE 0x1 =20 +#define PMXEVTYPER_P 0x80000000 +#define PMXEVTYPER_U 0x40000000 +#define PMXEVTYPER_NSK 0x20000000 +#define PMXEVTYPER_NSU 0x10000000 +#define PMXEVTYPER_NSH 0x08000000 +#define PMXEVTYPER_M 0x04000000 +#define PMXEVTYPER_MT 0x02000000 +#define PMXEVTYPER_EVTCOUNT 0x000003ff + #define PMU_NUM_COUNTERS(env) ((env->cp15.c9_pmcr & PMCRN) >> PMCRN_SHIFT) /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */ #define PMU_COUNTER_MASK(env) ((1 << 31) | ((1 << PMU_NUM_COUNTERS(env)) -= 1)) @@ -968,7 +977,7 @@ static CPAccessResult pmreg_access_ccntr(CPUARMState *e= nv, =20 static inline bool arm_ccnt_enabled(CPUARMState *env) { - /* This does not support checking PMCCFILTR_EL0 register */ + /* Does not check PMCCFILTR_EL0, which is handled by pmu_counter_filte= red */ =20 if (!(env->cp15.c9_pmcr & PMCRE) || !(env->cp15.c9_pmcnten & (1 << 31)= )) { return false; @@ -977,6 +986,43 @@ static inline bool arm_ccnt_enabled(CPUARMState *env) return true; } =20 +/* Returns true if the counter corresponding to the passed-in pmevtyper or + * pmccfiltr value is filtered using the current state */ +static inline bool pmu_counter_filtered(CPUARMState *env, uint64_t pmxevty= per) +{ + bool secure =3D arm_is_secure(env); + int el =3D arm_current_el(env); + + bool P =3D pmxevtyper & PMXEVTYPER_P; + bool U =3D pmxevtyper & PMXEVTYPER_U; + bool NSK =3D pmxevtyper & PMXEVTYPER_NSK; + bool NSU =3D pmxevtyper & PMXEVTYPER_NSU; + bool NSH =3D pmxevtyper & PMXEVTYPER_NSH; + bool M =3D pmxevtyper & PMXEVTYPER_M; + + if (el =3D=3D 1 && P) { + return true; + } else if (el =3D=3D 0 && U) { + return true; + } + + if (arm_feature(env, ARM_FEATURE_EL3)) { + if (el =3D=3D 1 && !secure && NSK !=3D P) { + return true; + } else if (el =3D=3D 0 && !secure && NSU !=3D U) { + return true; + } else if (el =3D=3D 3 && secure && M !=3D P) { + return true; + } + } + + if (arm_feature(env, ARM_FEATURE_EL2) && el =3D=3D 2 && !secure && !NS= H) { + return true; + } + + return false; +} + void pmccntr_sync(CPUARMState *env) { if (arm_ccnt_enabled(env) && @@ -995,10 +1041,15 @@ void pmccntr_sync(CPUARMState *env) } } =20 +void pmu_sync(CPUARMState *env) +{ + pmccntr_sync(env); +} + static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - pmccntr_sync(env); + pmu_sync(env); =20 if (value & PMCRC) { /* The counter has been reset */ @@ -1009,7 +1060,7 @@ static void pmcr_write(CPUARMState *env, const ARMCPR= egInfo *ri, env->cp15.c9_pmcr &=3D ~0x39; env->cp15.c9_pmcr |=3D (value & 0x39); =20 - pmccntr_sync(env); + pmu_sync(env); } =20 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -1053,6 +1104,10 @@ void pmccntr_sync(CPUARMState *env) { } =20 +void pmu_sync(CPUARMState *env) +{ +} + #endif =20 static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1184,7 +1239,9 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) =20 /* Clear all-context RES0 bits. */ value &=3D valid_mask; + pmu_sync(env); raw_write(env, ri, value); + pmu_sync(env); } =20 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -3735,7 +3792,9 @@ static void hcr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) { tlb_flush(CPU(cpu)); } + pmu_sync(env); raw_write(env, ri, value); + pmu_sync(env); } =20 static const ARMCPRegInfo el2_cp_reginfo[] =3D { @@ -5819,7 +5878,9 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint3= 2_t mask, } } mask &=3D ~CACHED_CPSR_BITS; + pmu_sync(env); env->uncached_cpsr =3D (env->uncached_cpsr & ~mask) | (val & mask); + pmu_sync(env); } =20 /* Sign/zero extend */ @@ -6702,6 +6763,8 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs) addr +=3D A32_BANKED_CURRENT_REG_GET(env, vbar); } =20 + pmu_sync(env); /* Surrounds updates to scr_el3 and uncached_cpsr */ + if ((env->uncached_cpsr & CPSR_M) =3D=3D ARM_CPU_MODE_MON) { env->cp15.scr_el3 &=3D ~SCR_NS; } @@ -6729,6 +6792,8 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs) } env->regs[14] =3D env->regs[15] + offset; env->regs[15] =3D addr; + + pmu_sync(env); /* Surrounds updates to scr_el3 and uncached_cpsr */ } =20 /* Handle exception entry to a target EL which is using AArch64 */ @@ -6818,7 +6883,9 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) env->elr_el[new_el]); =20 pstate_write(env, PSTATE_DAIF | new_mode); + pmu_sync(env); env->aarch64 =3D 1; + pmu_sync(env); aarch64_restore_sp(env, new_el); =20 env->pc =3D addr; diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 6111109..8ea9662 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -774,7 +774,9 @@ int kvm_arch_get_registers(CPUState *cs) return ret; } =20 + pmu_sync(env); env->aarch64 =3D ((val & PSTATE_nRW) =3D=3D 0); + pmu_sync(env); if (is_a64(env)) { pstate_write(env, val); } else { diff --git a/target/arm/machine.c b/target/arm/machine.c index d8094a8..833e400 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -177,7 +177,9 @@ static int get_cpsr(QEMUFile *f, void *opaque, size_t s= ize, CPUARMState *env =3D &cpu->env; uint32_t val =3D qemu_get_be32(f); =20 + pmu_sync(env); env->aarch64 =3D ((val & PSTATE_nRW) =3D=3D 0); + pmu_sync(env); =20 if (is_a64(env)) { pstate_write(env, val); diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index d64c867..8009c1c 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -997,7 +997,9 @@ void HELPER(exception_return)(CPUARMState *env) } =20 if (!return_to_aa64) { + pmu_sync(env); env->aarch64 =3D 0; + pmu_sync(env); /* We do a raw CPSR write because aarch64_sync_64_to_32() * will sort the register banks out for us, and we've already * caught all the bad-mode cases in el_from_spsr(). @@ -1017,7 +1019,9 @@ void HELPER(exception_return)(CPUARMState *env) "AArch32 EL%d PC 0x%" PRIx32 "\n", cur_el, new_el, env->regs[15]); } else { + pmu_sync(env); env->aarch64 =3D 1; + pmu_sync(env); pstate_write(env, spsr); if (!arm_singlestep_active(env)) { env->pstate &=3D ~PSTATE_SS; --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. 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charset="utf-8" Also modify it to be stored as a uint64_t Signed-off-by: Aaron Lindsay --- target/arm/cpu.h | 2 +- target/arm/helper.c | 27 ++++++++++++++++++++++++--- 2 files changed, 25 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ae2a294..f3524f6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -310,7 +310,7 @@ typedef struct CPUARMState { uint32_t c9_data; uint64_t c9_pmcr; /* performance monitor control register */ uint64_t c9_pmcnten; /* perf monitor counter enables */ - uint32_t c9_pmovsr; /* perf monitor overflow status */ + uint64_t c9_pmovsr; /* perf monitor overflow status */ uint32_t c9_pmuserenr; /* perf monitor user enable */ uint64_t c9_pmselr; /* perf monitor counter selection register */ uint64_t c9_pminten; /* perf monitor interrupt enables */ diff --git a/target/arm/helper.c b/target/arm/helper.c index bf9f164..9c01269 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1150,9 +1150,17 @@ static void pmcntenclr_write(CPUARMState *env, const= ARMCPRegInfo *ri, static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + value &=3D PMU_COUNTER_MASK(env); env->cp15.c9_pmovsr &=3D ~value; } =20 +static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + value &=3D PMU_COUNTER_MASK(env); + env->cp15.c9_pmovsr |=3D value; +} + static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1317,10 +1325,10 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcnten), .writefn =3D pmcntenclr_write }, { .name =3D "PMOVSR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 3, - .access =3D PL0_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_p= movsr), - .accessfn =3D pmreg_access, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmovsr), .writefn =3D pmovsr_write, - .raw_writefn =3D raw_write }, + .raw_writefn =3D raw_write, .resetvalue =3D 0 }, { .name =3D "PMOVSCLR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 3, .access =3D PL0_RW, .accessfn =3D pmreg_access, @@ -1328,6 +1336,19 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmovsr), .writefn =3D pmovsr_write, .raw_writefn =3D raw_write }, + { .name =3D "PMOVSSET", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 =3D= 0, .opc2 =3D 3, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmovsr), + .writefn =3D pmovsset_write, + .raw_writefn =3D raw_write }, + { .name =3D "PMOVSSET_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 14, .opc2 =3D 3, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmovsr), + .writefn =3D pmovsset_write, + .raw_writefn =3D raw_write }, /* Unimplemented so WI. */ { .name =3D "PMSWINC", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D = 0, .opc2 =3D 4, .access =3D PL0_W, .accessfn =3D pmreg_access_swinc, .type =3D ARM_C= P_NOP }, --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. 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charset="utf-8" Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 9c01269..5d07f72 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -975,17 +975,22 @@ static CPAccessResult pmreg_access_ccntr(CPUARMState = *env, return pmreg_access(env, ri, isread); } =20 -static inline bool arm_ccnt_enabled(CPUARMState *env) +static inline bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) { /* Does not check PMCCFILTR_EL0, which is handled by pmu_counter_filte= red */ - - if (!(env->cp15.c9_pmcr & PMCRE) || !(env->cp15.c9_pmcnten & (1 << 31)= )) { + if (!(env->cp15.c9_pmcr & PMCRE) || + !(env->cp15.c9_pmcnten & (1 << counter))) { return false; } =20 return true; } =20 +static inline bool arm_ccnt_enabled(CPUARMState *env) +{ + return pmu_counter_enabled(env, 31); +} + /* Returns true if the counter corresponding to the passed-in pmevtyper or * pmccfiltr value is filtered using the current state */ static inline bool pmu_counter_filtered(CPUARMState *env, uint64_t pmxevty= per) --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From nobody Sun Apr 28 02:37:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1492624308959833.7023064477439; Wed, 19 Apr 2017 10:51:48 -0700 (PDT) Received: from localhost ([::1]:49668 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d0tlb-00083w-Hm for importer@patchew.org; Wed, 19 Apr 2017 13:51:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44105) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d0tcA-0008Jq-1T for qemu-devel@nongnu.org; Wed, 19 Apr 2017 13:42:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d0tc7-0004RK-J6 for qemu-devel@nongnu.org; Wed, 19 Apr 2017 13:42:02 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:37842) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1d0tc4-0004P3-Np; Wed, 19 Apr 2017 13:41:56 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id DD146610DB; Wed, 19 Apr 2017 17:41:55 +0000 (UTC) Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id D2C9D610D4; Wed, 19 Apr 2017 17:41:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1492623715; bh=OTbX9A7wytE4wdwL05+NR5tWAO1elhLdDEHA/I2z1y4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ogwq6Rwm5mDk3OujlwrieV4/DkAgGKOyGVumWPL0FUC/ipvu3XJ80ehthDaXySP3C WR9mS/9WDAddk+AZhhsEIPJi3ID7Uj5VZK0cW6rBxtKHpf2ktVPxLzbYI/SY+fA5QF 3t++b1ThfpMoUT7TB5rb60XlHT4R03ih9tJGb5SE= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1492623715; bh=OTbX9A7wytE4wdwL05+NR5tWAO1elhLdDEHA/I2z1y4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ogwq6Rwm5mDk3OujlwrieV4/DkAgGKOyGVumWPL0FUC/ipvu3XJ80ehthDaXySP3C WR9mS/9WDAddk+AZhhsEIPJi3ID7Uj5VZK0cW6rBxtKHpf2ktVPxLzbYI/SY+fA5QF 3t++b1ThfpMoUT7TB5rb60XlHT4R03ih9tJGb5SE= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org D2C9D610D4 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: Peter Maydell , qemu-arm@nongnu.org Date: Wed, 19 Apr 2017 13:41:20 -0400 Message-Id: <1492623684-25799-10-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1492623684-25799-1-git-send-email-alindsay@codeaurora.org> References: <1492623684-25799-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH 09/13] target/arm: Add array for supported PMU events, generate PMCEID[01] X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mspradli@codeaurora.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This commit doesn't add any supported events, but provides the framework for adding them. We store the pm_event structs in a simple array, and provide the mapping from the event numbers to array indexes in the supported_event_map array. Signed-off-by: Aaron Lindsay --- target/arm/cpu.c | 4 ++++ target/arm/cpu.h | 10 ++++++++++ target/arm/helper.c | 37 +++++++++++++++++++++++++++++++++++++ 3 files changed, 51 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 44c965c..d61ea12 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -788,6 +788,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error = **errp) if (!cpu->has_pmu) { cpu->has_pmu =3D false; unset_feature(env, ARM_FEATURE_PMU); + } else { + uint64_t pmceid =3D get_pmceid(&cpu->env); + cpu->pmceid0 =3D pmceid & 0xffffffff; + cpu->pmceid1 =3D (pmceid >> 32) & 0xffffffff; } =20 if (!arm_feature(env, ARM_FEATURE_EL2)) { diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f3524f6..57ca684 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -780,6 +780,16 @@ void pmccntr_sync(CPUARMState *env); */ void pmu_sync(CPUARMState *env); =20 +/* + * get_pmceid + * @env: CPUARMState + * + * Return the PMCEID[01] register values corresponding to the counters whi= ch + * are supported given the current configuration (0 is low 32, 1 is high 32 + * bits) + */ +uint64_t get_pmceid(CPUARMState *env); + /* SCTLR bit meanings. Several bits have been reused in newer * versions of the architecture; in that case we define constants * for both old and new bit meanings. Code which tests against those diff --git a/target/arm/helper.c b/target/arm/helper.c index 5d07f72..a0ae201 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -891,6 +891,43 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */ #define PMU_COUNTER_MASK(env) ((1 << 31) | ((1 << PMU_NUM_COUNTERS(env)) -= 1)) =20 +typedef struct pm_event { + uint16_t number; /* PMEVTYPER.evtCount is 10 bits wide */ + /* If the event is supported on this CPU (used to generate PMCEID[01])= */ + bool (*supported)(CPUARMState *); + /* Retrieve the current count of the underlying event. The programmed + * counters hold a difference from the return value from this function= */ + uint64_t (*get_count)(CPUARMState *); +} pm_event; + +#define SUPPORTED_EVENT_SENTINEL UINT16_MAX +static const pm_event pm_events[] =3D { + { .number =3D SUPPORTED_EVENT_SENTINEL } +}; +static uint16_t supported_event_map[0x3f]; + +/* + * Called upon initialization to build PMCEID0 (low 32 bits) and PMCEID1 (= high + * 32). We also use it to build a map of ARM event numbers to indices in + * our pm_events array. + */ +uint64_t get_pmceid(CPUARMState *env) +{ + uint64_t pmceid =3D 0; + unsigned int i =3D 0; + while (pm_events[i].number !=3D SUPPORTED_EVENT_SENTINEL) { + const pm_event *cnt =3D &pm_events[i]; + if (cnt->number < 0x3f && cnt->supported(env)) { + pmceid |=3D (1 << cnt->number); + supported_event_map[cnt->number] =3D i; + } else { + supported_event_map[cnt->number] =3D SUPPORTED_EVENT_SENTINEL; + } + i++; + } + return pmceid; +} + static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *r= i, bool isread) { --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From nobody Sun Apr 28 02:37:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1492624369148772.1041886864659; Wed, 19 Apr 2017 10:52:49 -0700 (PDT) Received: from localhost ([::1]:49680 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d0tmZ-0000dy-Oe for importer@patchew.org; Wed, 19 Apr 2017 13:52:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44168) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d0tcC-0008N1-6u for qemu-devel@nongnu.org; Wed, 19 Apr 2017 13:42:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d0tcA-0004Sn-H6 for qemu-devel@nongnu.org; Wed, 19 Apr 2017 13:42:04 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:37942) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1d0tc6-0004Q4-Gt; Wed, 19 Apr 2017 13:41:58 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id A4A6261111; Wed, 19 Apr 2017 17:41:57 +0000 (UTC) Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id B12E0610DA; Wed, 19 Apr 2017 17:41:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1492623717; bh=q0DM7ZTvpSLpO4YfrvsBiNRJGH+NffQphZtYPTS6WCs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TuqZvdyIUEECK5oDtgsRgY0hD9b9vkxmsjfFU3khjCqzRaQczxEeCzScucg4DP570 ZNDW1/34e6dhUJt7ipsz4tv2gSYWelbHvHJ4XIxP3bm/CMJ8cdjFwvYDIU2iN/rPhS 7OhR7reuCbJg/s2eBcD4wq3zUqhRQL8OhYD0H0GU= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1492623716; bh=q0DM7ZTvpSLpO4YfrvsBiNRJGH+NffQphZtYPTS6WCs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OEeoFzga2rqY6OcuoR8ShnTo9ePyZZ1Kpka5AcdGMnLO9GJRs9/aiTq/OR7/Eejvt g5Bv5gdr2D0Y9MhayJJyKIF+KZltohhgOdui5J1dc1SgfLHED3zR13hmqTUNXgIVS+ /uXB1dseQPNr4V+sWvB3CdTR9mGJSYg68FvfMwks= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org B12E0610DA Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: Peter Maydell , qemu-arm@nongnu.org Date: Wed, 19 Apr 2017 13:41:21 -0400 Message-Id: <1492623684-25799-11-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1492623684-25799-1-git-send-email-alindsay@codeaurora.org> References: <1492623684-25799-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH 10/13] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mspradli@codeaurora.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add arrays to hold the registers, the definitions themselves, access functions, and add logic to reset counters when PMCR.P is set. Signed-off-by: Aaron Lindsay --- target/arm/cpu.h | 7 +- target/arm/helper.c | 187 ++++++++++++++++++++++++++++++++++++++++++++++++= ---- 2 files changed, 179 insertions(+), 15 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 57ca684..26df432 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -397,10 +397,13 @@ typedef struct CPUARMState { uint64_t oslsr_el1; /* OS Lock Status */ uint64_t mdcr_el2; uint64_t mdcr_el3; - /* If the counter is enabled, this stores the last time the counter - * was reset. Otherwise it stores the counter value + /* If the pmccntr and pmevcntr counters are enabled, they store the + * offset the last time the counter was reset. Otherwise they stor= e the + * counter value. */ uint64_t c15_ccnt; + uint64_t c14_pmevcntr[31]; + uint64_t c14_pmevtyper[31]; uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ uint64_t vpidr_el2; /* Virtualization Processor ID Register */ uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register = */ diff --git a/target/arm/helper.c b/target/arm/helper.c index a0ae201..66e576a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -876,6 +876,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { #define PMCRN_SHIFT 11 #define PMCRD 0x8 #define PMCRC 0x4 +#define PMCRP 0x2 #define PMCRE 0x1 =20 #define PMXEVTYPER_P 0x80000000 @@ -1020,6 +1021,21 @@ static inline bool pmu_counter_enabled(CPUARMState *= env, uint8_t counter) return false; } =20 + if (counter !=3D 31) { + /* If not checking PMCCNTR, ensure the counter is setup to an even= t we + * support */ + uint16_t event =3D env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_E= VTCOUNT; + if (event > 0x3f) { + return false; /* We only support common architectural and + microarchitectural events */ + } + + uint16_t event_idx =3D supported_event_map[event]; + if (event_idx =3D=3D SUPPORTED_EVENT_SENTINEL) { + return false; + } + } + return true; } =20 @@ -1083,8 +1099,26 @@ void pmccntr_sync(CPUARMState *env) } } =20 +static void pmu_sync_counter(CPUARMState *env, uint8_t counter) +{ + if (pmu_counter_enabled(env, counter) && + !pmu_counter_filtered(env, env->cp15.c14_pmevtyper[counter])) { + + uint16_t event =3D env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_E= VTCOUNT; + uint16_t event_idx =3D supported_event_map[event]; + + uint64_t count =3D pm_events[event_idx].get_count(env); + env->cp15.c14_pmevcntr[counter] =3D + count - env->cp15.c14_pmevcntr[counter]; + } +} + void pmu_sync(CPUARMState *env) { + unsigned int i; + for (i =3D 0; i < PMU_NUM_COUNTERS(env); i++) { + pmu_sync_counter(env, i); + } pmccntr_sync(env); } =20 @@ -1098,6 +1132,13 @@ static void pmcr_write(CPUARMState *env, const ARMCP= RegInfo *ri, env->cp15.c15_ccnt =3D 0; } =20 + if (value & PMCRP) { + unsigned int i; + for (i =3D 0; i < PMU_NUM_COUNTERS(env); i++) { + env->cp15.c14_pmevcntr[i] =3D 0; + } + } + /* only the DP, X, D and E bits are writable */ env->cp15.c9_pmcr &=3D ~0x39; env->cp15.c9_pmcr |=3D (value & 0x39); @@ -1203,30 +1244,112 @@ static void pmovsset_write(CPUARMState *env, const= ARMCPRegInfo *ri, env->cp15.c9_pmovsr |=3D value; } =20 -static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) +static void pmevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value, const uint8_t counter) { + if (counter =3D=3D 0x1f) { + pmccfiltr_write(env, ri, value); + } else if (counter < PMU_NUM_COUNTERS(env)) { + pmu_sync_counter(env, counter); + env->cp15.c14_pmevtyper[counter] =3D value & 0xfe0003ff; + pmu_sync_counter(env, counter); + } /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when * PMSELR value is equal to or greater than the number of implemented * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI. */ - if (env->cp15.c9_pmselr =3D=3D 0x1f) { - pmccfiltr_write(env, ri, value); +} + +static uint64_t pmevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri, + const uint8_t counter) +{ + if (counter =3D=3D 0x1f) { + return env->cp15.pmccfiltr_el0; + } else if (counter < PMU_NUM_COUNTERS(env)) { + return env->cp15.c14_pmevtyper[counter]; + } else { + /* We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER + * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write(). + */ + return 0; } } =20 +static void pmevtyper_writefn(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); + pmevtyper_write(env, ri, value, counter); +} + +static uint64_t pmevtyper_readfn(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); + return pmevtyper_read(env, ri, counter); +} + +static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + pmevtyper_write(env, ri, value, env->cp15.c9_pmselr & 31); +} + static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri) { - /* We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER - * are CONSTRAINED UNPREDICTABLE. See comments in pmxevtyper_write(). - */ - if (env->cp15.c9_pmselr =3D=3D 0x1f) { - return env->cp15.pmccfiltr_el0; + return pmevtyper_read(env, ri, env->cp15.c9_pmselr & 31); +} + +static void pmevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value, uint8_t counter) +{ + if (counter < PMU_NUM_COUNTERS(env)) { + env->cp15.c14_pmevcntr[counter] =3D value; + pmu_sync_counter(env, counter); + } + /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR + * are CONSTRAINED UNPREDICTABLE. */ +} + +static uint64_t pmevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri, + uint8_t counter) +{ + if (counter < PMU_NUM_COUNTERS(env)) { + uint64_t ret; + pmu_sync_counter(env, counter); + ret =3D env->cp15.c14_pmevcntr[counter]; + pmu_sync_counter(env, counter); + return ret; } else { + /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR + * are CONSTRAINED UNPREDICTABLE. */ return 0; } } =20 +static void pmevcntr_writefn(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); + pmevcntr_write(env, ri, value, counter); +} + +static uint64_t pmevcntr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); + return pmevcntr_read(env, ri, counter); +} + +static void pmxevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + pmevcntr_write(env, ri, value, env->cp15.c9_pmselr & 31); +} + +static uint64_t pmxevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return pmevcntr_read(env, ri, env->cp15.c9_pmselr & 31); +} + static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1435,10 +1558,13 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 1, .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW, .accessfn =3D pmreg_acc= ess, .writefn =3D pmxevtyper_write, .readfn =3D pmxevtyper_read }, - /* Unimplemented, RAZ/WI. */ { .name =3D "PMXEVCNTR", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 = =3D 0, .opc2 =3D 2, - .access =3D PL0_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, - .accessfn =3D pmreg_access_xevcntr }, + .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW, .accessfn =3D pmreg_acc= ess_xevcntr, + .writefn =3D pmxevcntr_write, .readfn =3D pmxevcntr_read }, + { .name =3D "PMXEVCNTR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 2, + .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW, .accessfn =3D pmreg_acc= ess_xevcntr, + .writefn =3D pmxevcntr_write, .readfn =3D pmxevcntr_read }, { .name =3D "PMUSERENR", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 0, .access =3D PL0_R | PL1_RW, .accessfn =3D access_tpm, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmuserenr), @@ -4072,7 +4198,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { #endif /* The only field of MDCR_EL2 that has a defined architectural reset v= alue * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but= we - * don't impelment any PMU event counters, so using zero as a reset + * don't implement any PMU event counters, so using zero as a reset * value for MDCR_EL2 is okay */ { .name =3D "MDCR_EL2", .state =3D ARM_CP_STATE_BOTH, @@ -4745,6 +4871,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, v7mp_cp_reginfo); } if (arm_feature(env, ARM_FEATURE_V7)) { + unsigned int i; /* v7 performance monitor control register: same implementor * field as main ID register, and we implement only the cycle * count register. @@ -4769,6 +4896,40 @@ void register_cp_regs_for_features(ARMCPU *cpu) }; define_one_arm_cp_reg(cpu, &pmcr); define_one_arm_cp_reg(cpu, &pmcr64); + for (i =3D 0; i < 31; i++) { + char *pmevcntr_name =3D g_strdup_printf("PMEVCNTR%d", i); + char *pmevcntr_el0_name =3D g_strdup_printf("PMEVCNTR%d_EL0", = i); + char *pmevtyper_name =3D g_strdup_printf("PMEVTYPER%d", i); + char *pmevtyper_el0_name =3D g_strdup_printf("PMEVTYPER%d_EL0"= , i); + ARMCPRegInfo pmev_regs[] =3D { + { .name =3D pmevcntr_name, .cp =3D 15, .crn =3D 15, + .crm =3D 8 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i & = 7, + .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW, + .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_write= fn, + .accessfn =3D pmreg_access }, + { .name =3D pmevcntr_el0_name, .state =3D ARM_CP_STATE_AA6= 4, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 15, .crm =3D 8 | (3 &= (i >> 3)), + .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg= _access, + .type =3D ARM_CP_NO_RAW, + .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_write= fn }, + { .name =3D pmevtyper_name, .cp =3D 15, .crn =3D 15, + .crm =3D 12 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i &= 7, + .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW, + .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_wri= tefn, + .accessfn =3D pmreg_access }, + { .name =3D pmevtyper_el0_name, .state =3D ARM_CP_STATE_AA= 64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 15, .crm =3D 12 | (3 = & (i >> 3)), + .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg= _access, + .type =3D ARM_CP_NO_RAW, + .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_wri= tefn }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, pmev_regs); + g_free(pmevcntr_name); + g_free(pmevcntr_el0_name); + g_free(pmevtyper_name); + g_free(pmevtyper_el0_name); + } #endif ARMCPRegInfo clidr =3D { .name =3D "CLIDR", .state =3D ARM_CP_STATE_BOTH, --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From nobody Sun Apr 28 02:37:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1492624404214851.5615380552848; Wed, 19 Apr 2017 10:53:24 -0700 (PDT) Received: from localhost ([::1]:49682 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d0tn8-00015m-PQ for importer@patchew.org; Wed, 19 Apr 2017 13:53:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44174) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d0tcC-0008NP-Hu for qemu-devel@nongnu.org; Wed, 19 Apr 2017 13:42:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d0tcB-0004Te-FT for qemu-devel@nongnu.org; Wed, 19 Apr 2017 13:42:04 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:37964) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1d0tc6-0004Q9-NL; Wed, 19 Apr 2017 13:41:58 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id D86A6610DB; Wed, 19 Apr 2017 17:41:57 +0000 (UTC) Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 8DE1F6110B; Wed, 19 Apr 2017 17:41:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1492623717; bh=qzlOI4KsqbIoOUzvLEVRckt/vWdX5oUMMBZks/dg04o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Bos8ZdxU/7uw6+nP6LpXysDnLInvoaf7pAbOlOFw1bRCQKphd8v8MpXRxjcjPwqe+ x9Y/rUDmuPlHrhocQWxHCHpAK3rAMhbTpakG2DQ22Qti7/hppmsz2JUz7+xwAgOcJZ 8yKnpzJ2yXaj+FhklG5ToYwd2aPc+UJWKvnHJ2Cs= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1492623717; bh=qzlOI4KsqbIoOUzvLEVRckt/vWdX5oUMMBZks/dg04o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Bos8ZdxU/7uw6+nP6LpXysDnLInvoaf7pAbOlOFw1bRCQKphd8v8MpXRxjcjPwqe+ x9Y/rUDmuPlHrhocQWxHCHpAK3rAMhbTpakG2DQ22Qti7/hppmsz2JUz7+xwAgOcJZ 8yKnpzJ2yXaj+FhklG5ToYwd2aPc+UJWKvnHJ2Cs= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 8DE1F6110B Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: Peter Maydell , qemu-arm@nongnu.org Date: Wed, 19 Apr 2017 13:41:22 -0400 Message-Id: <1492623684-25799-12-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1492623684-25799-1-git-send-email-alindsay@codeaurora.org> References: <1492623684-25799-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH 11/13] target/arm: PMU: Add instruction and cycle events X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mspradli@codeaurora.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The instruction event is only enabled when icount is used, cycles are always supported. Note: Setting can_do_io=3D1 should not be done here. It is ugly and wrong, but I am not sure of the proper way to handle this (See 'target/arm: Filter cycle counter based on PMCCFILTR_EL0') Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 47 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 66e576a..5972984 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -14,6 +14,7 @@ #include "arm_ldst.h" #include /* For crc32 */ #include "exec/semihost.h" +#include "sysemu/cpus.h" #include "sysemu/kvm.h" =20 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ @@ -901,8 +902,53 @@ typedef struct pm_event { uint64_t (*get_count)(CPUARMState *); } pm_event; =20 +static bool event_always_supported(CPUARMState *env) +{ + return true; +} + +static uint64_t cycles_get_count(CPUARMState *env) +{ + uint64_t ret; + CPUState *cpu =3D ENV_GET_CPU(env); + uint32_t saved_can_do_io =3D cpu->can_do_io; + cpu->can_do_io =3D 1; + + ret =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); + + cpu->can_do_io =3D saved_can_do_io; + return ret; +} + +static bool instructions_supported(CPUARMState *env) +{ + return use_icount =3D=3D 1 /* Precise instruction counting */; +} + +static uint64_t instructions_get_count(CPUARMState *env) +{ + uint64_t ret; + CPUState *cpu =3D ENV_GET_CPU(env); + uint32_t saved_can_do_io =3D cpu->can_do_io; + cpu->can_do_io =3D 1; + + ret =3D (uint64_t)cpu_get_icount_raw(); + + cpu->can_do_io =3D saved_can_do_io; + return ret; +} + #define SUPPORTED_EVENT_SENTINEL UINT16_MAX static const pm_event pm_events[] =3D { + { .number =3D 0x008, /* INST_RETIRED */ + .supported =3D instructions_supported, + .get_count =3D instructions_get_count + }, + { .number =3D 0x011, /* CPU_CYCLES */ + .supported =3D event_always_supported, + .get_count =3D cycles_get_count + }, { .number =3D SUPPORTED_EVENT_SENTINEL } }; static uint16_t supported_event_map[0x3f]; @@ -1087,8 +1133,7 @@ void pmccntr_sync(CPUARMState *env) !pmu_counter_filtered(env, env->cp15.pmccfiltr_el0)) { uint64_t temp_ticks; =20 - temp_ticks =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); + temp_ticks =3D cycles_get_count(env); =20 if (env->cp15.c9_pmcr & PMCRD) { /* Increment once every 64 processor clock cycles */ --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From nobody Sun Apr 28 02:37:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 149262443483866.1556996664732; Wed, 19 Apr 2017 10:53:54 -0700 (PDT) Received: from localhost ([::1]:49685 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d0tnd-0001Um-Ck for importer@patchew.org; Wed, 19 Apr 2017 13:53:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44162) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d0tcC-0008Mh-1C for qemu-devel@nongnu.org; Wed, 19 Apr 2017 13:42:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d0tcB-0004TQ-6x for qemu-devel@nongnu.org; Wed, 19 Apr 2017 13:42:04 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:38004) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1d0tc7-0004QR-6h; Wed, 19 Apr 2017 13:41:59 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 5CFCB61110; Wed, 19 Apr 2017 17:41:58 +0000 (UTC) Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 6A4A96110D; Wed, 19 Apr 2017 17:41:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1492623718; bh=DOEQgCYbmRI4K8pa91Bo4IMqRSp5D9GTpc5ABPezHuE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WEAZJFZxb7KoRav55OfYeuyksFSn8e0w4qlhOOFfHUuZ3I4mR6o1w0pC3gqWHhJYH ihxg3h6Y4mklypJOlwjgLyHIaUNPFKw6RXY4xSlP5XdoqnPuWNSJ5IDj+CF0tqSmUH HdpqD4fgbXccrcVizKaF9vqEgBLidJRl1onU1xA4= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1492623718; bh=DOEQgCYbmRI4K8pa91Bo4IMqRSp5D9GTpc5ABPezHuE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WEAZJFZxb7KoRav55OfYeuyksFSn8e0w4qlhOOFfHUuZ3I4mR6o1w0pC3gqWHhJYH ihxg3h6Y4mklypJOlwjgLyHIaUNPFKw6RXY4xSlP5XdoqnPuWNSJ5IDj+CF0tqSmUH HdpqD4fgbXccrcVizKaF9vqEgBLidJRl1onU1xA4= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 6A4A96110D Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: Peter Maydell , qemu-arm@nongnu.org Date: Wed, 19 Apr 2017 13:41:23 -0400 Message-Id: <1492623684-25799-13-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1492623684-25799-1-git-send-email-alindsay@codeaurora.org> References: <1492623684-25799-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH 12/13] target/arm: PMU: Set PMCR.N to 4 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mspradli@codeaurora.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This both advertises that we support four counters and adds them to the implementation because the PMU_NUM_COUNTERS macro reads this value from the PMCR. Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 5972984..a15b932 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4936,7 +4936,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL0_RW, .accessfn =3D pmreg_access, .type =3D ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcr), - .resetvalue =3D cpu->midr & 0xff000000, + /* 4 counters enabled */ + .resetvalue =3D (cpu->midr & 0xff000000) | (0x4 << PMCRN_SHIFT= ), .writefn =3D pmcr_write, .raw_writefn =3D raw_write, }; define_one_arm_cp_reg(cpu, &pmcr); --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. 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charset="utf-8" Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 40 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index a15b932..2c51f92 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -907,6 +907,15 @@ static bool event_always_supported(CPUARMState *env) return true; } =20 +static uint64_t swinc_get_count(CPUARMState *env) +{ + /* + * SW_INCR events are written directly to the pmevcntr's by writes to + * PMSWINC, so don't do anything here... + */ + return 0; +} + static uint64_t cycles_get_count(CPUARMState *env) { uint64_t ret; @@ -941,6 +950,10 @@ static uint64_t instructions_get_count(CPUARMState *en= v) =20 #define SUPPORTED_EVENT_SENTINEL UINT16_MAX static const pm_event pm_events[] =3D { + { .number =3D 0x000, /* SW_INCR */ + .supported =3D event_always_supported, + .get_count =3D swinc_get_count + }, { .number =3D 0x008, /* INST_RETIRED */ .supported =3D instructions_supported, .get_count =3D instructions_get_count @@ -1191,6 +1204,25 @@ static void pmcr_write(CPUARMState *env, const ARMCP= RegInfo *ri, pmu_sync(env); } =20 +static void pmswinc_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + unsigned int i; + for (i =3D 0; i < PMU_NUM_COUNTERS(env); i++) { + /* Increment a counter's count iff: */ + if ((value & (1 << i)) && /* counter's bit is set */ + /* counter is enabled and not filtered */ + pmu_counter_enabled(env, i) && + !pmu_counter_filtered(env, env->cp15.c14_pmevtyper[i]) && + /* counter is SW_INCR */ + (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) =3D=3D = 0x0) { + pmu_sync_counter(env, i); + env->cp15.c14_pmevcntr[i]++; + pmu_sync_counter(env, i); + } + } +} + static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) { uint64_t ret; @@ -1559,9 +1591,13 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmovsr), .writefn =3D pmovsset_write, .raw_writefn =3D raw_write }, - /* Unimplemented so WI. */ { .name =3D "PMSWINC", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D = 0, .opc2 =3D 4, - .access =3D PL0_W, .accessfn =3D pmreg_access_swinc, .type =3D ARM_C= P_NOP }, + .access =3D PL0_W, .accessfn =3D pmreg_access_swinc, .type =3D ARM_C= P_NO_RAW, + .writefn =3D pmswinc_write }, + { .name =3D "PMSWINC_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 4, + .access =3D PL0_W, .accessfn =3D pmreg_access_swinc, .type =3D ARM_C= P_NO_RAW, + .writefn =3D pmswinc_write }, #ifndef CONFIG_USER_ONLY { .name =3D "PMSELR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 5, .access =3D PL0_RW, .type =3D ARM_CP_ALIAS, --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, = Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.