From nobody Mon Feb 9 09:29:38 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1492159053981215.73185847255888; Fri, 14 Apr 2017 01:37:33 -0700 (PDT) Received: from localhost ([::1]:52305 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cywjU-0006Tr-Ky for importer@patchew.org; Fri, 14 Apr 2017 04:37:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56465) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cywhk-0005FV-Gy for qemu-devel@nongnu.org; Fri, 14 Apr 2017 04:35:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cywhf-0007K5-Ge for qemu-devel@nongnu.org; Fri, 14 Apr 2017 04:35:44 -0400 Received: from 8.mo178.mail-out.ovh.net ([46.105.74.227]:36723) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cywhf-0007IF-90 for qemu-devel@nongnu.org; Fri, 14 Apr 2017 04:35:39 -0400 Received: from player715.ha.ovh.net (b9.ovh.net [213.186.33.59]) by mo178.mail-out.ovh.net (Postfix) with ESMTP id 1E65E315F3 for ; Fri, 14 Apr 2017 10:35:38 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10647-27.w90-89.abo.wanadoo.fr [90.89.233.27]) (Authenticated sender: clg@kaod.org) by player715.ha.ovh.net (Postfix) with ESMTPSA id DF52A1C0093; Fri, 14 Apr 2017 10:35:29 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: Peter Maydell Date: Fri, 14 Apr 2017 10:35:01 +0200 Message-Id: <1492158903-8016-4-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1492158903-8016-1-git-send-email-clg@kaod.org> References: <1492158903-8016-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 9933251929868634897 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeeliedrvddtgddtgecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.74.227 Subject: [Qemu-devel] [PATCH v3 3/5] net/ftgmac100: add a 'aspeed' property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jan Kiszka , Jason Wang , qemu-devel@nongnu.org, qemu-arm@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Dmitry Fleytman , Samuel Thibault Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The Aspeed SoCs have a different definition of the end of the ring buffer bit. Add a property to specify which set of bits should be used by the NIC. Signed-off-by: C=C3=A9dric Le Goater --- hw/net/ftgmac100.c | 17 +++++++++++++++-- include/hw/net/ftgmac100.h | 4 ++++ 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c index fc309b3629fd..4c218bd79c64 100644 --- a/hw/net/ftgmac100.c +++ b/hw/net/ftgmac100.c @@ -126,6 +126,7 @@ #define FTGMAC100_TXDES0_CRC_ERR (1 << 19) #define FTGMAC100_TXDES0_LTS (1 << 28) #define FTGMAC100_TXDES0_FTS (1 << 29) +#define FTGMAC100_TXDES0_EDOTR_ASPEED (1 << 30) #define FTGMAC100_TXDES0_TXDMA_OWN (1 << 31) =20 #define FTGMAC100_TXDES1_VLANTAG_CI(x) ((x) & 0xffff) @@ -154,6 +155,7 @@ #define FTGMAC100_RXDES0_PAUSE_FRAME (1 << 25) #define FTGMAC100_RXDES0_LRS (1 << 28) #define FTGMAC100_RXDES0_FRS (1 << 29) +#define FTGMAC100_RXDES0_EDORR_ASPEED (1 << 30) #define FTGMAC100_RXDES0_RXPKT_RDY (1 << 31) =20 #define FTGMAC100_RXDES1_VLANTAG_CI 0xffff @@ -462,7 +464,7 @@ static void ftgmac100_do_tx(FTGMAC100State *s, uint32_t= tx_ring, /* Write back the modified descriptor. */ ftgmac100_write_bd(&bd, addr); /* Advance to the next descriptor. */ - if (bd.des0 & FTGMAC100_TXDES0_EDOTR) { + if (bd.des0 & s->txdes0_edotr) { addr =3D tx_ring; } else { addr +=3D sizeof(FTGMAC100Desc); @@ -880,7 +882,7 @@ static ssize_t ftgmac100_receive(NetClientState *nc, co= nst uint8_t *buf, s->isr |=3D FTGMAC100_INT_RPKT_FIFO; } ftgmac100_write_bd(&bd, addr); - if (bd.des0 & FTGMAC100_RXDES0_EDORR) { + if (bd.des0 & s->rxdes0_edorr) { addr =3D s->rx_ring; } else { addr +=3D sizeof(FTGMAC100Desc); @@ -921,6 +923,14 @@ static void ftgmac100_realize(DeviceState *dev, Error = **errp) FTGMAC100State *s =3D FTGMAC100(dev); SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); =20 + if (s->aspeed) { + s->txdes0_edotr =3D FTGMAC100_TXDES0_EDOTR_ASPEED; + s->rxdes0_edorr =3D FTGMAC100_RXDES0_EDORR_ASPEED; + } else { + s->txdes0_edotr =3D FTGMAC100_TXDES0_EDOTR; + s->rxdes0_edorr =3D FTGMAC100_RXDES0_EDORR; + } + memory_region_init_io(&s->iomem, OBJECT(dev), &ftgmac100_ops, s, TYPE_FTGMAC100, 0x2000); sysbus_init_mmio(sbd, &s->iomem); @@ -967,11 +977,14 @@ static const VMStateDescription vmstate_ftgmac100 =3D= { VMSTATE_UINT32(phy_advertise, FTGMAC100State), VMSTATE_UINT32(phy_int, FTGMAC100State), VMSTATE_UINT32(phy_int_mask, FTGMAC100State), + VMSTATE_UINT32(txdes0_edotr, FTGMAC100State), + VMSTATE_UINT32(rxdes0_edorr, FTGMAC100State), VMSTATE_END_OF_LIST() } }; =20 static Property ftgmac100_properties[] =3D { + DEFINE_PROP_BOOL("aspeed", FTGMAC100State, aspeed, false), DEFINE_NIC_PROPERTIES(FTGMAC100State, conf), DEFINE_PROP_END_OF_LIST(), }; diff --git a/include/hw/net/ftgmac100.h b/include/hw/net/ftgmac100.h index 962a718f43b8..d9bc589fbf72 100644 --- a/include/hw/net/ftgmac100.h +++ b/include/hw/net/ftgmac100.h @@ -55,6 +55,10 @@ typedef struct FTGMAC100State { uint32_t phy_advertise; uint32_t phy_int; uint32_t phy_int_mask; + + bool aspeed; + uint32_t txdes0_edotr; + uint32_t rxdes0_edorr; } FTGMAC100State; =20 #endif --=20 2.7.4