From nobody Tue Feb 10 03:45:16 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 149846801035191.41634702625015; Mon, 26 Jun 2017 02:06:50 -0700 (PDT) Received: from localhost ([::1]:45405 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dPPyq-0007rz-Lz for importer@patchew.org; Mon, 26 Jun 2017 05:06:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46311) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dPPrT-0001vR-Ln for qemu-devel@nongnu.org; Mon, 26 Jun 2017 04:59:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dPPrR-0004QM-Aw for qemu-devel@nongnu.org; Mon, 26 Jun 2017 04:59:11 -0400 Received: from mga11.intel.com ([192.55.52.93]:44436) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dPPrR-0004PL-2a for qemu-devel@nongnu.org; Mon, 26 Jun 2017 04:59:09 -0400 Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Jun 2017 01:59:07 -0700 Received: from yzhang13-kvm.sh.intel.com ([10.239.36.121]) by fmsmga006.fm.intel.com with ESMTP; 26 Jun 2017 01:58:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.39,394,1493708400"; d="scan'208";a="119263362" From: Yulei Zhang To: qemu-devel@nongnu.org Date: Tue, 4 Apr 2017 18:32:53 +0800 Message-Id: <1491301977-24481-6-git-send-email-yulei.zhang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491301977-24481-1-git-send-email-yulei.zhang@intel.com> References: <1491301977-24481-1-git-send-email-yulei.zhang@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.93 Subject: [Qemu-devel] [Intel-gfx][RFC 5/9] drm/i915/gvt: Align the guest gm aperture start offset for live migration X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kevin.tian@intel.com, joonas.lahtinen@linux.intel.com, zhenyuw@linux.intel.com, Yulei Zhang , xiao.zheng@intel.com, zhi.a.wang@intel.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" As guest gm aperture region start offset is initialized when vGPU created, in order to make sure that start offset is remain the same after migration, align the aperture start offset to 0 for guest. Signed-off-by: Yulei Zhang --- drivers/gpu/drm/i915/gvt/kvmgt.c | 3 +-- drivers/gpu/drm/i915/gvt/vgpu.c | 7 +++++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kv= mgt.c index 1ae0b40..d2b13ae 100644 --- a/drivers/gpu/drm/i915/gvt/kvmgt.c +++ b/drivers/gpu/drm/i915/gvt/kvmgt.c @@ -1002,8 +1002,7 @@ static long intel_vgpu_ioctl(struct mdev_device *mdev= , unsigned int cmd, =20 sparse->nr_areas =3D nr_areas; cap_type_id =3D VFIO_REGION_INFO_CAP_SPARSE_MMAP; - sparse->areas[0].offset =3D - PAGE_ALIGN(vgpu_aperture_offset(vgpu)); + sparse->areas[0].offset =3D 0; sparse->areas[0].size =3D vgpu_aperture_sz(vgpu); break; =20 diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgp= u.c index 90c14e6..989f353 100644 --- a/drivers/gpu/drm/i915/gvt/vgpu.c +++ b/drivers/gpu/drm/i915/gvt/vgpu.c @@ -43,8 +43,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu) vgpu_vreg(vgpu, vgtif_reg(version_minor)) =3D 0; vgpu_vreg(vgpu, vgtif_reg(display_ready)) =3D 0; vgpu_vreg(vgpu, vgtif_reg(vgt_id)) =3D vgpu->id; - vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =3D - vgpu_aperture_gmadr_base(vgpu); + vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =3D 0; vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) =3D vgpu_aperture_sz(vgpu); vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) =3D @@ -480,6 +479,8 @@ void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgp= u, bool dmlr, { struct intel_gvt *gvt =3D vgpu->gvt; struct intel_gvt_workload_scheduler *scheduler =3D &gvt->scheduler; + u64 maddr =3D vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)); + u64 unmaddr =3D vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base= )); =20 gvt_dbg_core("------------------------------------------\n"); gvt_dbg_core("resseting vgpu%d, dmlr %d, engine_mask %08x\n", @@ -510,6 +511,8 @@ void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgp= u, bool dmlr, =20 intel_vgpu_reset_mmio(vgpu, dmlr); populate_pvinfo_page(vgpu); + vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =3D maddr; + vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) =3D unmaddr; intel_vgpu_reset_display(vgpu); =20 if (dmlr) { --=20 2.7.4