From nobody Tue Feb 10 05:10:38 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498467893488944.9944599192096; Mon, 26 Jun 2017 02:04:53 -0700 (PDT) Received: from localhost ([::1]:45394 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dPPwx-0006aV-QC for importer@patchew.org; Mon, 26 Jun 2017 05:04:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46315) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dPPrT-0001vT-MY for qemu-devel@nongnu.org; Mon, 26 Jun 2017 04:59:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dPPrR-0004QD-5n for qemu-devel@nongnu.org; Mon, 26 Jun 2017 04:59:11 -0400 Received: from mga11.intel.com ([192.55.52.93]:49171) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dPPrQ-0004Oi-SZ for qemu-devel@nongnu.org; Mon, 26 Jun 2017 04:59:09 -0400 Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Jun 2017 01:59:07 -0700 Received: from yzhang13-kvm.sh.intel.com ([10.239.36.121]) by fmsmga006.fm.intel.com with ESMTP; 26 Jun 2017 01:58:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.39,394,1493708400"; d="scan'208";a="119263360" From: Yulei Zhang To: qemu-devel@nongnu.org Date: Tue, 4 Apr 2017 18:32:52 +0800 Message-Id: <1491301977-24481-5-git-send-email-yulei.zhang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491301977-24481-1-git-send-email-yulei.zhang@intel.com> References: <1491301977-24481-1-git-send-email-yulei.zhang@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.93 Subject: [Qemu-devel] [Intel-gfx][RFC 4/9] drm/i915/gvt: Retrieve the guest gm base address from PVINFO X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kevin.tian@intel.com, joonas.lahtinen@linux.intel.com, zhenyuw@linux.intel.com, Yulei Zhang , xiao.zheng@intel.com, zhi.a.wang@intel.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" As after migration the host gm base address will be changed due to resource re-allocation, in order to make sure the guest gm address doesn't change with that to retrieve the guest gm base address from PVINFO. Signed-off-by: Yulei Zhang --- drivers/gpu/drm/i915/gvt/cfg_space.c | 3 ++- drivers/gpu/drm/i915/gvt/gtt.c | 8 ++++---- drivers/gpu/drm/i915/gvt/gvt.h | 22 ++++++++++++++++++---- 3 files changed, 24 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/cfg_space.c b/drivers/gpu/drm/i915/gv= t/cfg_space.c index 40af17e..b57ae44 100644 --- a/drivers/gpu/drm/i915/gvt/cfg_space.c +++ b/drivers/gpu/drm/i915/gvt/cfg_space.c @@ -33,6 +33,7 @@ =20 #include "i915_drv.h" #include "gvt.h" +#include "i915_pvinfo.h" =20 enum { INTEL_GVT_PCI_BAR_GTTMMIO =3D 0, @@ -123,7 +124,7 @@ static int map_aperture(struct intel_vgpu *vgpu, bool m= ap) else val =3D *(u32 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_2); =20 - first_gfn =3D (val + vgpu_aperture_offset(vgpu)) >> PAGE_SHIFT; + first_gfn =3D (val + vgpu_guest_aperture_offset(vgpu)) >> PAGE_SHIFT; first_mfn =3D vgpu_aperture_pa_base(vgpu) >> PAGE_SHIFT; =20 ret =3D intel_gvt_hypervisor_map_gfn_to_mfn(vgpu, first_gfn, diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c index df596a6..e9a127c 100644 --- a/drivers/gpu/drm/i915/gvt/gtt.c +++ b/drivers/gpu/drm/i915/gvt/gtt.c @@ -64,10 +64,10 @@ int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u= 64 g_addr, u64 *h_addr) =20 if (vgpu_gmadr_is_aperture(vgpu, g_addr)) *h_addr =3D vgpu_aperture_gmadr_base(vgpu) - + (g_addr - vgpu_aperture_offset(vgpu)); + + (g_addr - vgpu_guest_aperture_gmadr_base(vgpu)); else *h_addr =3D vgpu_hidden_gmadr_base(vgpu) - + (g_addr - vgpu_hidden_offset(vgpu)); + + (g_addr - vgpu_guest_hidden_gmadr_base(vgpu)); return 0; } =20 @@ -79,10 +79,10 @@ int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u= 64 h_addr, u64 *g_addr) return -EACCES; =20 if (gvt_gmadr_is_aperture(vgpu->gvt, h_addr)) - *g_addr =3D vgpu_aperture_gmadr_base(vgpu) + *g_addr =3D vgpu_guest_aperture_gmadr_base(vgpu) + (h_addr - gvt_aperture_gmadr_base(vgpu->gvt)); else - *g_addr =3D vgpu_hidden_gmadr_base(vgpu) + *g_addr =3D vgpu_guest_hidden_gmadr_base(vgpu) + (h_addr - gvt_hidden_gmadr_base(vgpu->gvt)); return 0; } diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h index 71c00b2..23eeb7c 100644 --- a/drivers/gpu/drm/i915/gvt/gvt.h +++ b/drivers/gpu/drm/i915/gvt/gvt.h @@ -343,6 +343,20 @@ int intel_gvt_load_firmware(struct intel_gvt *gvt); #define vgpu_fence_base(vgpu) (vgpu->fence.base) #define vgpu_fence_sz(vgpu) (vgpu->fence.size) =20 +/* Aperture/GM space definitions for vGPU Guest view point */ +#define vgpu_guest_aperture_offset(vgpu) \ + vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) +#define vgpu_guest_hidden_offset(vgpu) \ + vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) + +#define vgpu_guest_aperture_gmadr_base(vgpu) (vgpu_guest_aperture_offset(v= gpu)) +#define vgpu_guest_aperture_gmadr_end(vgpu) \ + (vgpu_guest_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1) + +#define vgpu_guest_hidden_gmadr_base(vgpu) (vgpu_guest_hidden_offset(vgpu)) +#define vgpu_guest_hidden_gmadr_end(vgpu) \ + (vgpu_guest_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1) + struct intel_vgpu_creation_params { __u64 handle; __u64 low_gm_sz; /* in MB */ @@ -420,12 +434,12 @@ void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgp= u); =20 /* validating GM functions */ #define vgpu_gmadr_is_aperture(vgpu, gmadr) \ - ((gmadr >=3D vgpu_aperture_gmadr_base(vgpu)) && \ - (gmadr <=3D vgpu_aperture_gmadr_end(vgpu))) + ((gmadr >=3D vgpu_guest_aperture_gmadr_base(vgpu)) && \ + (gmadr <=3D vgpu_guest_aperture_gmadr_end(vgpu))) =20 #define vgpu_gmadr_is_hidden(vgpu, gmadr) \ - ((gmadr >=3D vgpu_hidden_gmadr_base(vgpu)) && \ - (gmadr <=3D vgpu_hidden_gmadr_end(vgpu))) + ((gmadr >=3D vgpu_guest_hidden_gmadr_base(vgpu)) && \ + (gmadr <=3D vgpu_guest_hidden_gmadr_end(vgpu))) =20 #define vgpu_gmadr_is_valid(vgpu, gmadr) \ ((vgpu_gmadr_is_aperture(vgpu, gmadr) || \ --=20 2.7.4