From nobody Tue Feb 10 05:10:38 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1498467661488604.1161617615696; Mon, 26 Jun 2017 02:01:01 -0700 (PDT) Received: from localhost ([::1]:45375 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dPPtB-00037g-Tn for importer@patchew.org; Mon, 26 Jun 2017 05:00:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46309) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dPPrT-0001vQ-L7 for qemu-devel@nongnu.org; Mon, 26 Jun 2017 04:59:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dPPrQ-0004Pq-Mh for qemu-devel@nongnu.org; Mon, 26 Jun 2017 04:59:11 -0400 Received: from mga11.intel.com ([192.55.52.93]:49171) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dPPrQ-0004Oi-D3 for qemu-devel@nongnu.org; Mon, 26 Jun 2017 04:59:08 -0400 Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Jun 2017 01:59:06 -0700 Received: from yzhang13-kvm.sh.intel.com ([10.239.36.121]) by fmsmga006.fm.intel.com with ESMTP; 26 Jun 2017 01:58:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.39,394,1493708400"; d="scan'208";a="119263351" From: Yulei Zhang To: qemu-devel@nongnu.org Date: Tue, 4 Apr 2017 18:32:50 +0800 Message-Id: <1491301977-24481-3-git-send-email-yulei.zhang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491301977-24481-1-git-send-email-yulei.zhang@intel.com> References: <1491301977-24481-1-git-send-email-yulei.zhang@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.93 Subject: [Qemu-devel] [Intel-gfx][RFC 2/9] drm/i915/gvt: Apply g2h adjustment during fence mmio access X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kevin.tian@intel.com, joonas.lahtinen@linux.intel.com, zhenyuw@linux.intel.com, Yulei Zhang , xiao.zheng@intel.com, zhi.a.wang@intel.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Apply the guest to host gma conversion while guest config the fence mmio registers due to the host gma change after the migration. Signed-off-by: Yulei Zhang --- drivers/gpu/drm/i915/gvt/aperture_gm.c | 6 ++++-- drivers/gpu/drm/i915/gvt/gvt.h | 14 ++++++++++++++ 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/aperture_gm.c b/drivers/gpu/drm/i915/= gvt/aperture_gm.c index ca3d192..cd68ec6 100644 --- a/drivers/gpu/drm/i915/gvt/aperture_gm.c +++ b/drivers/gpu/drm/i915/gvt/aperture_gm.c @@ -144,8 +144,10 @@ void intel_vgpu_write_fence(struct intel_vgpu *vgpu, I915_WRITE(fence_reg_lo, 0); POSTING_READ(fence_reg_lo); =20 - I915_WRITE(fence_reg_hi, upper_32_bits(value)); - I915_WRITE(fence_reg_lo, lower_32_bits(value)); + I915_WRITE(fence_reg_hi, + intel_gvt_reg_g2h(vgpu, upper_32_bits(value), 0xFFFFF000)); + I915_WRITE(fence_reg_lo, + intel_gvt_reg_g2h(vgpu, lower_32_bits(value), 0xFFFFF000)); POSTING_READ(fence_reg_lo); } =20 diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h index 3a74e79..71c00b2 100644 --- a/drivers/gpu/drm/i915/gvt/gvt.h +++ b/drivers/gpu/drm/i915/gvt/gvt.h @@ -451,6 +451,20 @@ int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, = unsigned long g_index, int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_inde= x, unsigned long *g_index); =20 +/* apply guest to host gma convertion in GM registers setting */ +static inline u64 intel_gvt_reg_g2h(struct intel_vgpu *vgpu, + u32 addr, u32 mask) +{ + u64 gma; + + if (addr) { + intel_gvt_ggtt_gmadr_g2h(vgpu, + addr & mask, &gma); + addr =3D gma | (addr & (~mask)); + } + return addr; +} + void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu, bool primary); void intel_vgpu_reset_cfg_space(struct intel_vgpu *vgpu); --=20 2.7.4