From nobody Thu May 2 23:33:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1489675158246441.68610709624943; Thu, 16 Mar 2017 07:39:18 -0700 (PDT) Received: from localhost ([::1]:43913 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1coWYd-0003IY-UO for importer@patchew.org; Thu, 16 Mar 2017 10:39:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33216) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1coWXA-0002rU-BG for qemu-devel@nongnu.org; Thu, 16 Mar 2017 10:37:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1coWX5-0006op-ST for qemu-devel@nongnu.org; Thu, 16 Mar 2017 10:37:44 -0400 Received: from 9.mo1.mail-out.ovh.net ([178.32.108.172]:48937) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1coWX5-0006oZ-IW for qemu-devel@nongnu.org; Thu, 16 Mar 2017 10:37:39 -0400 Received: from player756.ha.ovh.net (b7.ovh.net [213.186.33.57]) by mo1.mail-out.ovh.net (Postfix) with ESMTP id BD29F6255C for ; Thu, 16 Mar 2017 15:37:37 +0100 (CET) Received: from zorba.kaod.org.com (LFbn-1-10647-27.w90-89.abo.wanadoo.fr [90.89.233.27]) (Authenticated sender: clg@kaod.org) by player756.ha.ovh.net (Postfix) with ESMTPSA id 97D0A42007B; Thu, 16 Mar 2017 15:37:33 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 16 Mar 2017 15:35:05 +0100 Message-Id: <1489674912-21942-2-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1489674912-21942-1-git-send-email-clg@kaod.org> References: <1489674912-21942-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 11759180105125694438 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelhedriedtgdegfecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 178.32.108.172 Subject: [Qemu-devel] [PATCH v2 1/8] ppc/xics: introduce an ICPState backlink under PowerPCCPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Today, the ICPState array of the sPAPR machine is indexed with 'cpu_index' of the CPUState. This numbering of CPUs is internal to QEMU and the guest only knows about what is exposed in the device tree, that is the 'cpu_dt_id'. This is why sPAPR uses the helper xics_get_cpu_index_by_dt_id() to do the mapping in a couple of places. To provide a more generic XICS layer, we need to abstract the IRQ 'server' number and remove any assumption made on its nature. It should not be used as a 'cpu_index' for lookups like xics_cpu_setup() and xics_cpu_destroy() do. To reach that goal, we choose to introduce an ICPState backlink under PowerPCCPU, and let the machine core init routine do the ICPState lookup. The resulting object is stored under PowerPCCPU which is passed on to xics_cpu_setup(). The IRQ 'server' number in XICS is now generic. sPAPR uses 'cpu_dt_id' and PowerNV will use 'PIR' number. This also has the benefit of simplifying the sPAPR hcall routines which do not need to do any ICPState lookups anymore. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xics.c | 4 ++-- hw/intc/xics_spapr.c | 20 +++++--------------- hw/ppc/spapr_cpu_core.c | 4 +++- target/ppc/cpu.h | 2 ++ 4 files changed, 12 insertions(+), 18 deletions(-) diff --git a/hw/intc/xics.c b/hw/intc/xics.c index e740989a1162..5cde86ceb3bc 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -52,7 +52,7 @@ int xics_get_cpu_index_by_dt_id(int cpu_dt_id) void xics_cpu_destroy(XICSFabric *xi, PowerPCCPU *cpu) { CPUState *cs =3D CPU(cpu); - ICPState *icp =3D xics_icp_get(xi, cs->cpu_index); + ICPState *icp =3D cpu->icp; =20 assert(icp); assert(cs =3D=3D icp->cs); @@ -65,7 +65,7 @@ void xics_cpu_setup(XICSFabric *xi, PowerPCCPU *cpu) { CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; - ICPState *icp =3D xics_icp_get(xi, cs->cpu_index); + ICPState *icp =3D cpu->icp; ICPStateClass *icpc; =20 assert(icp); diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c index 84d24b2837a7..178b3adc8af7 100644 --- a/hw/intc/xics_spapr.c +++ b/hw/intc/xics_spapr.c @@ -43,11 +43,9 @@ static target_ulong h_cppr(PowerPCCPU *cpu, sPAPRMachineState *spapr, target_ulong opcode, target_ulong *args) { - CPUState *cs =3D CPU(cpu); - ICPState *icp =3D xics_icp_get(XICS_FABRIC(spapr), cs->cpu_index); target_ulong cppr =3D args[0]; =20 - icp_set_cppr(icp, cppr); + icp_set_cppr(cpu->icp, cppr); return H_SUCCESS; } =20 @@ -69,9 +67,7 @@ static target_ulong h_ipi(PowerPCCPU *cpu, sPAPRMachineSt= ate *spapr, static target_ulong h_xirr(PowerPCCPU *cpu, sPAPRMachineState *spapr, target_ulong opcode, target_ulong *args) { - CPUState *cs =3D CPU(cpu); - ICPState *icp =3D xics_icp_get(XICS_FABRIC(spapr), cs->cpu_index); - uint32_t xirr =3D icp_accept(icp); + uint32_t xirr =3D icp_accept(cpu->icp); =20 args[0] =3D xirr; return H_SUCCESS; @@ -80,9 +76,7 @@ static target_ulong h_xirr(PowerPCCPU *cpu, sPAPRMachineS= tate *spapr, static target_ulong h_xirr_x(PowerPCCPU *cpu, sPAPRMachineState *spapr, target_ulong opcode, target_ulong *args) { - CPUState *cs =3D CPU(cpu); - ICPState *icp =3D xics_icp_get(XICS_FABRIC(spapr), cs->cpu_index); - uint32_t xirr =3D icp_accept(icp); + uint32_t xirr =3D icp_accept(cpu->icp); =20 args[0] =3D xirr; args[1] =3D cpu_get_host_ticks(); @@ -92,21 +86,17 @@ static target_ulong h_xirr_x(PowerPCCPU *cpu, sPAPRMach= ineState *spapr, static target_ulong h_eoi(PowerPCCPU *cpu, sPAPRMachineState *spapr, target_ulong opcode, target_ulong *args) { - CPUState *cs =3D CPU(cpu); - ICPState *icp =3D xics_icp_get(XICS_FABRIC(spapr), cs->cpu_index); target_ulong xirr =3D args[0]; =20 - icp_eoi(icp, xirr); + icp_eoi(cpu->icp, xirr); return H_SUCCESS; } =20 static target_ulong h_ipoll(PowerPCCPU *cpu, sPAPRMachineState *spapr, target_ulong opcode, target_ulong *args) { - CPUState *cs =3D CPU(cpu); - ICPState *icp =3D xics_icp_get(XICS_FABRIC(spapr), cs->cpu_index); uint32_t mfrr; - uint32_t xirr =3D icp_ipoll(icp, &mfrr); + uint32_t xirr =3D icp_ipoll(cpu->icp, &mfrr); =20 args[0] =3D xirr; args[1] =3D mfrr; diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 6883f0991ae9..59f1cba6fba5 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -63,6 +63,7 @@ static void spapr_cpu_init(sPAPRMachineState *spapr, Powe= rPCCPU *cpu, Error **errp) { CPUPPCState *env =3D &cpu->env; + XICSFabric *xi =3D XICS_FABRIC(spapr); =20 /* Set time-base frequency to 512 MHz */ cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ); @@ -80,7 +81,8 @@ static void spapr_cpu_init(sPAPRMachineState *spapr, Powe= rPCCPU *cpu, } } =20 - xics_cpu_setup(XICS_FABRIC(spapr), cpu); + cpu->icp =3D xics_icp_get(xi, CPU(cpu)->cpu_index); + xics_cpu_setup(xi, cpu); =20 qemu_register_reset(spapr_cpu_reset, cpu); spapr_cpu_reset(cpu); diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 5ee33b3fd315..b1626d0a6607 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1176,6 +1176,7 @@ do { \ =20 typedef struct PPCVirtualHypervisor PPCVirtualHypervisor; typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass; +typedef struct ICPState ICPState; =20 /** * PowerPCCPU: @@ -1196,6 +1197,7 @@ struct PowerPCCPU { uint32_t max_compat; uint32_t compat_pvr; PPCVirtualHypervisor *vhyp; + ICPState *icp; =20 /* Fields related to migration compatibility hacks */ bool pre_2_8_migration; --=20 2.7.4 From nobody Thu May 2 23:33:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1489675166108593.2012182230876; Thu, 16 Mar 2017 07:39:26 -0700 (PDT) Received: from localhost ([::1]:43914 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1coWYk-0003UF-LS for importer@patchew.org; Thu, 16 Mar 2017 10:39:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33255) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1coWXE-0002v1-Ko for qemu-devel@nongnu.org; Thu, 16 Mar 2017 10:37:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1coWXA-0006pZ-7C for qemu-devel@nongnu.org; Thu, 16 Mar 2017 10:37:48 -0400 Received: from 19.mo1.mail-out.ovh.net ([178.32.97.206]:47814) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1coWXA-0006pM-0k for qemu-devel@nongnu.org; Thu, 16 Mar 2017 10:37:44 -0400 Received: from player756.ha.ovh.net (b7.ovh.net [213.186.33.57]) by mo1.mail-out.ovh.net (Postfix) with ESMTP id E2BBC625C9 for ; Thu, 16 Mar 2017 15:37:41 +0100 (CET) Received: from zorba.kaod.org.com (LFbn-1-10647-27.w90-89.abo.wanadoo.fr [90.89.233.27]) (Authenticated sender: clg@kaod.org) by player756.ha.ovh.net (Postfix) with ESMTPSA id BC66642007B; Thu, 16 Mar 2017 15:37:37 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 16 Mar 2017 15:35:06 +0100 Message-Id: <1489674912-21942-3-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1489674912-21942-1-git-send-email-clg@kaod.org> References: <1489674912-21942-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 11760306006045985766 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelhedriedtgdegfecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 178.32.97.206 Subject: [Qemu-devel] [PATCH v2 2/8] spapr: move the IRQ server number mapping under the machine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This is the second step to abstract the IRQ 'server' number of the XICS layer. Now that the prereq cleanups have been done in the previous patch, we can move down the 'cpu_dt_id' to 'cpu_index' mapping in the sPAPR machine handler. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: David Gibson --- hw/intc/xics_spapr.c | 5 ++--- hw/ppc/spapr.c | 3 ++- hw/ppc/spapr_cpu_core.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c index 178b3adc8af7..9574cae14944 100644 --- a/hw/intc/xics_spapr.c +++ b/hw/intc/xics_spapr.c @@ -52,9 +52,8 @@ static target_ulong h_cppr(PowerPCCPU *cpu, sPAPRMachineS= tate *spapr, static target_ulong h_ipi(PowerPCCPU *cpu, sPAPRMachineState *spapr, target_ulong opcode, target_ulong *args) { - target_ulong server =3D xics_get_cpu_index_by_dt_id(args[0]); target_ulong mfrr =3D args[1]; - ICPState *icp =3D xics_icp_get(XICS_FABRIC(spapr), server); + ICPState *icp =3D xics_icp_get(XICS_FABRIC(spapr), args[0]); =20 if (!icp) { return H_PARAMETER; @@ -122,7 +121,7 @@ static void rtas_set_xive(PowerPCCPU *cpu, sPAPRMachine= State *spapr, } =20 nr =3D rtas_ld(args, 0); - server =3D xics_get_cpu_index_by_dt_id(rtas_ld(args, 1)); + server =3D rtas_ld(args, 1); priority =3D rtas_ld(args, 2); =20 if (!ics_valid_irq(ics, nr) || !xics_icp_get(XICS_FABRIC(spapr), serve= r) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 6ee566d658f8..396490bc5dfc 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -3024,9 +3024,10 @@ static void spapr_ics_resend(XICSFabric *dev) ics_resend(spapr->ics); } =20 -static ICPState *spapr_icp_get(XICSFabric *xi, int server) +static ICPState *spapr_icp_get(XICSFabric *xi, int cpu_dt_id) { sPAPRMachineState *spapr =3D SPAPR_MACHINE(xi); + int server =3D xics_get_cpu_index_by_dt_id(cpu_dt_id); =20 return (server < spapr->nr_servers) ? &spapr->icps[server] : NULL; } diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 59f1cba6fba5..1d5e7fbeeb1f 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -81,7 +81,7 @@ static void spapr_cpu_init(sPAPRMachineState *spapr, Powe= rPCCPU *cpu, } } =20 - cpu->icp =3D xics_icp_get(xi, CPU(cpu)->cpu_index); + cpu->icp =3D xics_icp_get(xi, cpu->cpu_dt_id); xics_cpu_setup(xi, cpu); =20 qemu_register_reset(spapr_cpu_reset, cpu); --=20 2.7.4 From nobody Thu May 2 23:33:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1489675284195493.33310386186895; Thu, 16 Mar 2017 07:41:24 -0700 (PDT) Received: from localhost ([::1]:43932 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1coWah-0005Gm-5W for importer@patchew.org; Thu, 16 Mar 2017 10:41:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33270) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1coWXI-0002y0-5u for qemu-devel@nongnu.org; Thu, 16 Mar 2017 10:37:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1coWXD-0006qo-OQ for qemu-devel@nongnu.org; Thu, 16 Mar 2017 10:37:52 -0400 Received: from 8.mo1.mail-out.ovh.net ([178.33.110.239]:32817) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1coWXD-0006q8-IV for qemu-devel@nongnu.org; Thu, 16 Mar 2017 10:37:47 -0400 Received: from player756.ha.ovh.net (b7.ovh.net [213.186.33.57]) by mo1.mail-out.ovh.net (Postfix) with ESMTP id 14AF4625B1 for ; Thu, 16 Mar 2017 15:37:46 +0100 (CET) Received: from zorba.kaod.org.com (LFbn-1-10647-27.w90-89.abo.wanadoo.fr [90.89.233.27]) (Authenticated sender: clg@kaod.org) by player756.ha.ovh.net (Postfix) with ESMTPSA id E0382420091; Thu, 16 Mar 2017 15:37:41 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 16 Mar 2017 15:35:07 +0100 Message-Id: <1489674912-21942-4-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1489674912-21942-1-git-send-email-clg@kaod.org> References: <1489674912-21942-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 11761713381018471398 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelhedriedtgdegfecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 178.33.110.239 Subject: [Qemu-devel] [PATCH v2 3/8] ppc/xics: add a realize() handler to ICPStateClass X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" It will be used by derived classes in PowerNV for customization. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: David Gibson --- hw/intc/xics.c | 5 +++++ include/hw/ppc/xics.h | 1 + 2 files changed, 6 insertions(+) diff --git a/hw/intc/xics.c b/hw/intc/xics.c index 5cde86ceb3bc..7cd842102265 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -348,6 +348,7 @@ static void icp_reset(void *dev) static void icp_realize(DeviceState *dev, Error **errp) { ICPState *icp =3D ICP(dev); + ICPStateClass *icpc =3D ICP_GET_CLASS(dev); Object *obj; Error *err =3D NULL; =20 @@ -360,6 +361,10 @@ static void icp_realize(DeviceState *dev, Error **errp) =20 icp->xics =3D XICS_FABRIC(obj); =20 + if (icpc->realize) { + icpc->realize(dev, errp); + } + qemu_register_reset(icp_reset, dev); } =20 diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h index 9a5e715fe553..0863e3a079f5 100644 --- a/include/hw/ppc/xics.h +++ b/include/hw/ppc/xics.h @@ -60,6 +60,7 @@ typedef struct XICSFabric XICSFabric; struct ICPStateClass { DeviceClass parent_class; =20 + void (*realize)(DeviceState *dev, Error **errp); void (*pre_save)(ICPState *s); int (*post_load)(ICPState *s, int version_id); void (*cpu_setup)(ICPState *icp, PowerPCCPU *cpu); --=20 2.7.4 From nobody Thu May 2 23:33:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1489675277074897.9437816787306; Thu, 16 Mar 2017 07:41:17 -0700 (PDT) Received: from localhost ([::1]:43930 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1coWaa-0005Am-0D for importer@patchew.org; Thu, 16 Mar 2017 10:41:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33341) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1coWXR-00036j-AW for qemu-devel@nongnu.org; Thu, 16 Mar 2017 10:38:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1coWXL-0006t3-0d for qemu-devel@nongnu.org; Thu, 16 Mar 2017 10:38:01 -0400 Received: from 16.mo1.mail-out.ovh.net ([178.33.104.224]:58220) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1coWXK-0006se-Ne for qemu-devel@nongnu.org; Thu, 16 Mar 2017 10:37:54 -0400 Received: from player756.ha.ovh.net (b7.ovh.net [213.186.33.57]) by mo1.mail-out.ovh.net (Postfix) with ESMTP id 361746256D for ; Thu, 16 Mar 2017 15:37:50 +0100 (CET) Received: from zorba.kaod.org.com (LFbn-1-10647-27.w90-89.abo.wanadoo.fr [90.89.233.27]) (Authenticated sender: clg@kaod.org) by player756.ha.ovh.net (Postfix) with ESMTPSA id 10F024200A1; Thu, 16 Mar 2017 15:37:46 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 16 Mar 2017 15:35:08 +0100 Message-Id: <1489674912-21942-5-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1489674912-21942-1-git-send-email-clg@kaod.org> References: <1489674912-21942-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 11762839277574917094 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelhedriedtgdegfecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 178.33.104.224 Subject: [Qemu-devel] [PATCH v2 4/8] ppc/pnv: add a PnvICPState object X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This provides a new ICPState object for the PowerNV machine (POWER8). Access to the Interrupt Management area is done though a memory region. It contains the registers of the Interrupt Control Presenters of each thread which are used to accept, return, forward interrupts in the system. Signed-off-by: C=C3=A9dric Le Goater --- Changes since v1: - moved the memory region from PnvCore to a specific PnvICPState object hw/intc/Makefile.objs | 1 + hw/intc/xics_pnv.c | 180 ++++++++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/ppc/xics.h | 12 ++++ 3 files changed, 193 insertions(+) create mode 100644 hw/intc/xics_pnv.c diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs index adedd0da5fd8..78426a7dafcd 100644 --- a/hw/intc/Makefile.objs +++ b/hw/intc/Makefile.objs @@ -35,6 +35,7 @@ obj-$(CONFIG_SH4) +=3D sh_intc.o obj-$(CONFIG_XICS) +=3D xics.o obj-$(CONFIG_XICS_SPAPR) +=3D xics_spapr.o obj-$(CONFIG_XICS_KVM) +=3D xics_kvm.o +obj-$(CONFIG_POWERNV) +=3D xics_pnv.o obj-$(CONFIG_ALLWINNER_A10_PIC) +=3D allwinner-a10-pic.o obj-$(CONFIG_S390_FLIC) +=3D s390_flic.o obj-$(CONFIG_S390_FLIC_KVM) +=3D s390_flic_kvm.o diff --git a/hw/intc/xics_pnv.c b/hw/intc/xics_pnv.c new file mode 100644 index 000000000000..68a3ef6097a6 --- /dev/null +++ b/hw/intc/xics_pnv.c @@ -0,0 +1,180 @@ +/* + * QEMU PowerPC PowerNV ICP model + * + * Copyright (c) 2016, IBM Corporation. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public License + * as published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "sysemu/sysemu.h" +#include "qapi/error.h" +#include "qemu/log.h" +#include "hw/ppc/xics.h" + +static uint64_t pnv_icp_read(void *opaque, hwaddr addr, unsigned width) +{ + ICPState *icp =3D ICP(opaque); + PnvICPState *picp =3D PNV_ICP(opaque); + bool byte0 =3D (width =3D=3D 1 && (addr & 0x3) =3D=3D 0); + uint64_t val =3D 0xffffffff; + + switch (addr & 0xffc) { + case 0: /* poll */ + val =3D icp_ipoll(icp, NULL); + if (byte0) { + val >>=3D 24; + } else if (width !=3D 4) { + goto bad_access; + } + break; + case 4: /* xirr */ + if (byte0) { + val =3D icp_ipoll(icp, NULL) >> 24; + } else if (width =3D=3D 4) { + val =3D icp_accept(icp); + } else { + goto bad_access; + } + break; + case 12: + if (byte0) { + val =3D icp->mfrr; + } else { + goto bad_access; + } + break; + case 16: + if (width =3D=3D 4) { + val =3D picp->links[0]; + } else { + goto bad_access; + } + break; + case 20: + if (width =3D=3D 4) { + val =3D picp->links[1]; + } else { + goto bad_access; + } + break; + case 24: + if (width =3D=3D 4) { + val =3D picp->links[2]; + } else { + goto bad_access; + } + break; + default: +bad_access: + qemu_log_mask(LOG_GUEST_ERROR, "XICS: Bad ICP access 0x%" + HWADDR_PRIx"/%d\n", addr, width); + } + + return val; +} + +static void pnv_icp_write(void *opaque, hwaddr addr, uint64_t val, + unsigned width) +{ + ICPState *icp =3D ICP(opaque); + PnvICPState *picp =3D PNV_ICP(opaque); + bool byte0 =3D (width =3D=3D 1 && (addr & 0x3) =3D=3D 0); + + switch (addr & 0xffc) { + case 4: /* xirr */ + if (byte0) { + icp_set_cppr(icp, val); + } else if (width =3D=3D 4) { + icp_eoi(icp, val); + } else { + goto bad_access; + } + break; + case 12: + if (byte0) { + icp_set_mfrr(icp, val); + } else { + goto bad_access; + } + break; + case 16: + if (width =3D=3D 4) { + picp->links[0] =3D val; + } else { + goto bad_access; + } + break; + case 20: + if (width =3D=3D 4) { + picp->links[1] =3D val; + } else { + goto bad_access; + } + break; + case 24: + if (width =3D=3D 4) { + picp->links[2] =3D val; + } else { + goto bad_access; + } + break; + default: +bad_access: + qemu_log_mask(LOG_GUEST_ERROR, "XICS: Bad ICP access 0x%" + HWADDR_PRIx"/%d\n", addr, width); + } +} + +static const MemoryRegionOps pnv_icp_ops =3D { + .read =3D pnv_icp_read, + .write =3D pnv_icp_write, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 4, + .impl.min_access_size =3D 1, + .impl.max_access_size =3D 4, + .endianness =3D DEVICE_BIG_ENDIAN, +}; + +static void pnv_icp_realize(DeviceState *dev, Error **errp) +{ + PnvICPState *icp =3D PNV_ICP(dev); + + memory_region_init_io(&icp->mmio, OBJECT(dev), &pnv_icp_ops, + icp, "icp-thread", 0x1000); +} + +static void pnv_icp_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ICPStateClass *icpc =3D ICP_CLASS(klass); + + icpc->realize =3D pnv_icp_realize; + dc->desc =3D "PowerNV ICP"; +} + +static const TypeInfo pnv_icp_info =3D { + .name =3D TYPE_PNV_ICP, + .parent =3D TYPE_ICP, + .instance_size =3D sizeof(PnvICPState), + .class_init =3D pnv_icp_class_init, + .class_size =3D sizeof(ICPStateClass), +}; + +static void pnv_icp_register_types(void) +{ + type_register_static(&pnv_icp_info); +} + +type_init(pnv_icp_register_types) diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h index 0863e3a079f5..cfcf7ecece69 100644 --- a/include/hw/ppc/xics.h +++ b/include/hw/ppc/xics.h @@ -41,10 +41,12 @@ */ typedef struct ICPStateClass ICPStateClass; typedef struct ICPState ICPState; +typedef struct PnvICPState PnvICPState; typedef struct ICSStateClass ICSStateClass; typedef struct ICSState ICSState; typedef struct ICSIRQState ICSIRQState; typedef struct XICSFabric XICSFabric; +typedef struct PowerPCCPU PowerPCCPU; =20 #define TYPE_ICP "icp" #define ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_ICP) @@ -52,6 +54,9 @@ typedef struct XICSFabric XICSFabric; #define TYPE_KVM_ICP "icp-kvm" #define KVM_ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_KVM_ICP) =20 +#define TYPE_PNV_ICP "pnv-icp" +#define PNV_ICP(obj) OBJECT_CHECK(PnvICPState, (obj), TYPE_PNV_ICP) + #define ICP_CLASS(klass) \ OBJECT_CLASS_CHECK(ICPStateClass, (klass), TYPE_ICP) #define ICP_GET_CLASS(obj) \ @@ -81,6 +86,13 @@ struct ICPState { XICSFabric *xics; }; =20 +struct PnvICPState { + ICPState parent_obj; + + MemoryRegion mmio; + uint32_t links[3]; +}; + #define TYPE_ICS_BASE "ics-base" #define ICS_BASE(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_BASE) =20 --=20 2.7.4 From nobody Thu May 2 23:33:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1489675409981970.4241775786207; Thu, 16 Mar 2017 07:43:29 -0700 (PDT) Received: from localhost ([::1]:43939 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1coWci-00075z-Oe for importer@patchew.org; Thu, 16 Mar 2017 10:43:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33340) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1coWXR-00036i-AZ for qemu-devel@nongnu.org; Thu, 16 Mar 2017 10:38:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1coWXM-0006tM-Q1 for qemu-devel@nongnu.org; Thu, 16 Mar 2017 10:38:01 -0400 Received: from 12.mo1.mail-out.ovh.net ([87.98.162.229]:47717) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1coWXM-0006t8-GT for qemu-devel@nongnu.org; Thu, 16 Mar 2017 10:37:56 -0400 Received: from player756.ha.ovh.net (b7.ovh.net [213.186.33.57]) by mo1.mail-out.ovh.net (Postfix) with ESMTP id CFDCC62597 for ; Thu, 16 Mar 2017 15:37:54 +0100 (CET) Received: from zorba.kaod.org.com (LFbn-1-10647-27.w90-89.abo.wanadoo.fr [90.89.233.27]) (Authenticated sender: clg@kaod.org) by player756.ha.ovh.net (Postfix) with ESMTPSA id 33C654200AD; Thu, 16 Mar 2017 15:37:50 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 16 Mar 2017 15:35:09 +0100 Message-Id: <1489674912-21942-6-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1489674912-21942-1-git-send-email-clg@kaod.org> References: <1489674912-21942-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 11763965178485115878 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelhedriedtgdegfecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 87.98.162.229 Subject: [Qemu-devel] [PATCH v2 5/8] ppc/pnv: create the ICP and ICS objects under the machine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Like this is done for the sPAPR machine, we use a simple array under the PowerNV machine to store the Interrupt Control Presenters (ICP) objects, one for each vCPU. This array is indexed by 'cpu_index' of the CPUState but the users will provide a core PIR number. The mapping is done in the icp_get() handler of the machine and is transparent to XICS. We use a list to hold the different Interrupt Control Sources (ICS) objects, as PowerNV needs to handle multiple sources: for PCI-E and for the Processor Service Interface (PSI). Finally, to interface with the XICS layer which manipulates the ICP and ICS objects, we extend the PowerNV machine with an XICSFabric interface and its associated handlers. Signed-off-by: C=C3=A9dric Le Goater --- Changes since v1: - handled pir-to-cpu_index mapping under icp_get=20 - removed ics_eio handler - changed ICP name indexing - removed sysbus parenting of the ICP object hw/ppc/pnv.c | 102 ++++++++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/ppc/pnv.h | 4 ++ include/hw/ppc/xics.h | 1 + 3 files changed, 107 insertions(+) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 3fa722af82e6..6ff01c3b84d5 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -33,7 +33,10 @@ #include "exec/address-spaces.h" #include "qemu/cutils.h" #include "qapi/visitor.h" +#include "monitor/monitor.h" +#include "hw/intc/intc.h" =20 +#include "hw/ppc/xics.h" #include "hw/ppc/pnv_xscom.h" =20 #include "hw/isa/isa.h" @@ -417,6 +420,26 @@ static void ppc_powernv_init(MachineState *machine) machine->cpu_model =3D "POWER8"; } =20 + /* Create the Interrupt Control Presenters before the vCPUs */ + pnv->nr_servers =3D pnv->num_chips * smp_cores * smp_threads; + pnv->icps =3D g_new0(PnvICPState, pnv->nr_servers); + for (i =3D 0; i < pnv->nr_servers; i++) { + PnvICPState *icp =3D &pnv->icps[i]; + char name[32]; + + /* TODO: fix ICP object name to be in sync with the core name */ + snprintf(name, sizeof(name), "icp[%d]", i); + object_initialize(icp, sizeof(*icp), TYPE_PNV_ICP); + object_property_add_child(OBJECT(pnv), name, OBJECT(icp), + &error_fatal); + object_property_add_const_link(OBJECT(icp), "xics", OBJECT(pnv), + &error_fatal); + object_property_set_bool(OBJECT(icp), true, "realized", &error_fat= al); + } + + /* and the list of Interrupt Control Sources */ + QLIST_INIT(&pnv->ics); + /* Create the processor chips */ chip_typename =3D g_strdup_printf(TYPE_PNV_CHIP "-%s", machine->cpu_mo= del); if (!object_class_by_name(chip_typename)) { @@ -743,6 +766,58 @@ static void pnv_get_num_chips(Object *obj, Visitor *v,= const char *name, visit_type_uint32(v, name, &POWERNV_MACHINE(obj)->num_chips, errp); } =20 +static ICSState *pnv_ics_get(XICSFabric *xi, int irq) +{ + PnvMachineState *pnv =3D POWERNV_MACHINE(xi); + ICSState *ics; + + QLIST_FOREACH(ics, &pnv->ics, list) { + if (ics_valid_irq(ics, irq)) { + return ics; + } + } + return NULL; +} + +static void pnv_ics_resend(XICSFabric *xi) +{ + PnvMachineState *pnv =3D POWERNV_MACHINE(xi); + ICSState *ics; + + QLIST_FOREACH(ics, &pnv->ics, list) { + ics_resend(ics); + } +} + +static PowerPCCPU *ppc_get_vcpu_by_pir(int pir) +{ + CPUState *cs; + + CPU_FOREACH(cs) { + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + CPUPPCState *env =3D &cpu->env; + + if (env->spr_cb[SPR_PIR].default_value =3D=3D pir) { + return cpu; + } + } + + return NULL; +} + +static ICPState *pnv_icp_get(XICSFabric *xi, int pir) +{ + PnvMachineState *pnv =3D POWERNV_MACHINE(xi); + PowerPCCPU *cpu =3D ppc_get_vcpu_by_pir(pir); + + if (!cpu) { + return NULL; + } + + assert(cpu->parent_obj.cpu_index < pnv->nr_servers); + return ICP(&pnv->icps[cpu->parent_obj.cpu_index]); +} + static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -784,9 +859,27 @@ static void powernv_machine_class_props_init(ObjectCla= ss *oc) NULL); } =20 +static void pnv_pic_print_info(InterruptStatsProvider *obj, + Monitor *mon) +{ + PnvMachineState *pnv =3D POWERNV_MACHINE(obj); + ICSState *ics; + int i; + + for (i =3D 0; i < pnv->nr_servers; i++) { + icp_pic_print_info(ICP(&pnv->icps[i]), mon); + } + + QLIST_FOREACH(ics, &pnv->ics, list) { + ics_pic_print_info(ics, mon); + } +} + static void powernv_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); + XICSFabricClass *xic =3D XICS_FABRIC_CLASS(oc); + InterruptStatsProviderClass *ispc =3D INTERRUPT_STATS_PROVIDER_CLASS(o= c); =20 mc->desc =3D "IBM PowerNV (Non-Virtualized)"; mc->init =3D ppc_powernv_init; @@ -797,6 +890,10 @@ static void powernv_machine_class_init(ObjectClass *oc= , void *data) mc->no_parallel =3D 1; mc->default_boot_order =3D NULL; mc->default_ram_size =3D 1 * G_BYTE; + xic->icp_get =3D pnv_icp_get; + xic->ics_get =3D pnv_ics_get; + xic->ics_resend =3D pnv_ics_resend; + ispc->print_info =3D pnv_pic_print_info; =20 powernv_machine_class_props_init(oc); } @@ -807,6 +904,11 @@ static const TypeInfo powernv_machine_info =3D { .instance_size =3D sizeof(PnvMachineState), .instance_init =3D powernv_machine_initfn, .class_init =3D powernv_machine_class_init, + .interfaces =3D (InterfaceInfo[]) { + { TYPE_XICS_FABRIC }, + { TYPE_INTERRUPT_STATS_PROVIDER }, + { }, + }, }; =20 static void powernv_machine_register_types(void) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index df98a72006e4..d6ef04771aff 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -22,6 +22,7 @@ #include "hw/boards.h" #include "hw/sysbus.h" #include "hw/ppc/pnv_lpc.h" +#include "hw/ppc/xics.h" =20 #define TYPE_PNV_CHIP "powernv-chip" #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP) @@ -114,6 +115,9 @@ typedef struct PnvMachineState { PnvChip **chips; =20 ISABus *isa_bus; + PnvICPState *icps; + uint32_t nr_servers; + QLIST_HEAD(, ICSState) ics; } PnvMachineState; =20 #define PNV_FDT_ADDR 0x01000000 diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h index cfcf7ecece69..4b100869003c 100644 --- a/include/hw/ppc/xics.h +++ b/include/hw/ppc/xics.h @@ -128,6 +128,7 @@ struct ICSState { qemu_irq *qirqs; ICSIRQState *irqs; XICSFabric *xics; + QLIST_ENTRY(ICSState) list; }; =20 static inline bool ics_valid_irq(ICSState *ics, uint32_t nr) --=20 2.7.4 From nobody Thu May 2 23:33:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1489675516315852.2335623175327; Thu, 16 Mar 2017 07:45:16 -0700 (PDT) Received: from localhost ([::1]:43953 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1coWeR-0000Z6-5l for importer@patchew.org; Thu, 16 Mar 2017 10:45:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33380) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1coWXV-0003A1-5G for qemu-devel@nongnu.org; Thu, 16 Mar 2017 10:38:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1coWXQ-0006uN-O0 for qemu-devel@nongnu.org; Thu, 16 Mar 2017 10:38:05 -0400 Received: from 7.mo1.mail-out.ovh.net ([87.98.158.110]:38536) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1coWXQ-0006u6-Hr for qemu-devel@nongnu.org; Thu, 16 Mar 2017 10:38:00 -0400 Received: from player756.ha.ovh.net (b7.ovh.net [213.186.33.57]) by mo1.mail-out.ovh.net (Postfix) with ESMTP id 02F64625A7 for ; Thu, 16 Mar 2017 15:37:59 +0100 (CET) Received: from zorba.kaod.org.com (LFbn-1-10647-27.w90-89.abo.wanadoo.fr [90.89.233.27]) (Authenticated sender: clg@kaod.org) by player756.ha.ovh.net (Postfix) with ESMTPSA id D1D324200AD; Thu, 16 Mar 2017 15:37:54 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 16 Mar 2017 15:35:10 +0100 Message-Id: <1489674912-21942-7-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1489674912-21942-1-git-send-email-clg@kaod.org> References: <1489674912-21942-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 11765091078492621798 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelhedriedtgdegfecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 87.98.158.110 Subject: [Qemu-devel] [PATCH v2 6/8] ppc/pnv: add a helper to calculate MMIO addresses registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Some controllers (ICP, PSI) have a base register address which is calculated using the chip id. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: David Gibson --- include/hw/ppc/pnv.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index d6ef04771aff..cfd059fc49db 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -92,14 +92,24 @@ typedef struct PnvChipClass { OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9) =20 /* - * This generates a HW chip id depending on an index: + * This generates a HW chip id depending on an index, as found on a + * two socket system with dual chip modules : * * 0x0, 0x1, 0x10, 0x11 * * 4 chips should be the maximum + * + * TODO: use a machine property to define the chip ids */ #define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1)) =20 +/* + * Converts back a HW chip id to an index. This is useful to calculate + * the MMIO addresses of some controllers which depend on the chip id. + */ +#define PNV_CHIP_INDEX(chip) \ + (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3)) + #define TYPE_POWERNV_MACHINE MACHINE_TYPE_NAME("powernv") #define POWERNV_MACHINE(obj) \ OBJECT_CHECK(PnvMachineState, (obj), TYPE_POWERNV_MACHINE) --=20 2.7.4 From nobody Thu May 2 23:33:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1489675284506872.1863596995457; Thu, 16 Mar 2017 07:41:24 -0700 (PDT) Received: from localhost ([::1]:43931 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1coWah-0005Gh-DH for importer@patchew.org; Thu, 16 Mar 2017 10:41:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33423) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1coWXZ-0003EV-Gd for qemu-devel@nongnu.org; Thu, 16 Mar 2017 10:38:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1coWXV-0006vp-24 for qemu-devel@nongnu.org; Thu, 16 Mar 2017 10:38:09 -0400 Received: from 3.mo1.mail-out.ovh.net ([46.105.60.232]:51569) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1coWXU-0006vK-Qp for qemu-devel@nongnu.org; Thu, 16 Mar 2017 10:38:04 -0400 Received: from player756.ha.ovh.net (b7.ovh.net [213.186.33.57]) by mo1.mail-out.ovh.net (Postfix) with ESMTP id 355D9625D8 for ; Thu, 16 Mar 2017 15:38:03 +0100 (CET) Received: from zorba.kaod.org.com (LFbn-1-10647-27.w90-89.abo.wanadoo.fr [90.89.233.27]) (Authenticated sender: clg@kaod.org) by player756.ha.ovh.net (Postfix) with ESMTPSA id 019804200AA; Thu, 16 Mar 2017 15:37:58 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 16 Mar 2017 15:35:11 +0100 Message-Id: <1489674912-21942-8-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1489674912-21942-1-git-send-email-clg@kaod.org> References: <1489674912-21942-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 11766498455173630950 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelhedriedtgdegfecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.60.232 Subject: [Qemu-devel] [PATCH v2 7/8] ppc/pnv: link the CPUs to the machine XICSFabric X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This assigns the ICPState object to the CPU using the PIR number for lookups before calling the XICS layer to finish the job. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: David Gibson --- hw/ppc/pnv.c | 2 ++ hw/ppc/pnv_core.c | 20 ++++++++++++++++---- 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 6ff01c3b84d5..9c239932fb3a 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -714,6 +714,8 @@ static void pnv_chip_realize(DeviceState *dev, Error **= errp) object_property_set_int(OBJECT(pnv_core), pcc->core_pir(chip, core_hwid), "pir", &error_fatal); + object_property_add_const_link(OBJECT(pnv_core), "xics", + qdev_get_machine(), &error_fatal); object_property_set_bool(OBJECT(pnv_core), true, "realized", &error_fatal); object_unref(OBJECT(pnv_core)); diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index d79d530b4881..6ec1c9c0a831 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -25,6 +25,7 @@ #include "hw/ppc/pnv.h" #include "hw/ppc/pnv_core.h" #include "hw/ppc/pnv_xscom.h" +#include "hw/ppc/xics.h" =20 static void powernv_cpu_reset(void *opaque) { @@ -43,7 +44,7 @@ static void powernv_cpu_reset(void *opaque) env->msr |=3D MSR_HVB; /* Hypervisor mode */ } =20 -static void powernv_cpu_init(PowerPCCPU *cpu, Error **errp) +static void powernv_cpu_init(PowerPCCPU *cpu, XICSFabric *xi, Error **errp) { CPUPPCState *env =3D &cpu->env; int core_pir; @@ -63,6 +64,9 @@ static void powernv_cpu_init(PowerPCCPU *cpu, Error **err= p) cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ); =20 qemu_register_reset(powernv_cpu_reset, cpu); + + cpu->icp =3D xics_icp_get(xi, pir->default_value); + xics_cpu_setup(xi, cpu); } =20 /* @@ -110,7 +114,7 @@ static const MemoryRegionOps pnv_core_xscom_ops =3D { .endianness =3D DEVICE_BIG_ENDIAN, }; =20 -static void pnv_core_realize_child(Object *child, Error **errp) +static void pnv_core_realize_child(Object *child, XICSFabric *xi, Error **= errp) { Error *local_err =3D NULL; CPUState *cs =3D CPU(child); @@ -122,7 +126,7 @@ static void pnv_core_realize_child(Object *child, Error= **errp) return; } =20 - powernv_cpu_init(cpu, &local_err); + powernv_cpu_init(cpu, xi, &local_err); if (local_err) { error_propagate(errp, local_err); return; @@ -140,6 +144,14 @@ static void pnv_core_realize(DeviceState *dev, Error *= *errp) void *obj; int i, j; char name[32]; + Object *xi; + + xi =3D object_property_get_link(OBJECT(dev), "xics", &local_err); + if (!xi) { + error_setg(errp, "%s: required link 'xics' not found: %s", + __func__, error_get_pretty(local_err)); + return; + } =20 pc->threads =3D g_malloc0(size * cc->nr_threads); for (i =3D 0; i < cc->nr_threads; i++) { @@ -160,7 +172,7 @@ static void pnv_core_realize(DeviceState *dev, Error **= errp) for (j =3D 0; j < cc->nr_threads; j++) { obj =3D pc->threads + j * size; =20 - pnv_core_realize_child(obj, &local_err); + pnv_core_realize_child(obj, XICS_FABRIC(xi), &local_err); if (local_err) { goto err; } --=20 2.7.4 From nobody Thu May 2 23:33:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1489675414613676.3841058797216; Thu, 16 Mar 2017 07:43:34 -0700 (PDT) Received: from localhost ([::1]:43941 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1coWcn-0007Aa-JC for importer@patchew.org; Thu, 16 Mar 2017 10:43:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33466) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1coWXd-0003Hm-LJ for qemu-devel@nongnu.org; Thu, 16 Mar 2017 10:38:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1coWXY-0006x1-Ml for qemu-devel@nongnu.org; Thu, 16 Mar 2017 10:38:13 -0400 Received: from 9.mo1.mail-out.ovh.net ([178.32.108.172]:38572) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1coWXY-0006wl-Da for qemu-devel@nongnu.org; Thu, 16 Mar 2017 10:38:08 -0400 Received: from player756.ha.ovh.net (b7.ovh.net [213.186.33.57]) by mo1.mail-out.ovh.net (Postfix) with ESMTP id 4BB28625B1 for ; Thu, 16 Mar 2017 15:38:07 +0100 (CET) Received: from zorba.kaod.org.com (LFbn-1-10647-27.w90-89.abo.wanadoo.fr [90.89.233.27]) (Authenticated sender: clg@kaod.org) by player756.ha.ovh.net (Postfix) with ESMTPSA id 253C942008C; Thu, 16 Mar 2017 15:38:03 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 16 Mar 2017 15:35:12 +0100 Message-Id: <1489674912-21942-9-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1489674912-21942-1-git-send-email-clg@kaod.org> References: <1489674912-21942-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 11767624353195133926 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelhedriedtgdegfecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 178.32.108.172 Subject: [Qemu-devel] [PATCH v2 8/8] ppc/pnv: add memory regions for the ICP registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This provides to a PowerNV chip (POWER8) access to the Interrupt Management area, which contains the registers of the Interrupt Control Presenters of each thread. These are used to accept, return, forward interrupts in the system. This area is modeled with a per-chip container memory region holding all the ICP registers. Each thread of a chip is then associated with its ICP registers using a memory subregion indexed by its PIR number in the overall region. The device tree is populated accordingly. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: David Gibson --- Changes since v1: - added multichip support - adapted to use PnvICPState object hw/ppc/pnv.c | 81 ++++++++++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/ppc/pnv.h | 19 ++++++++++++ 2 files changed, 100 insertions(+) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 9c239932fb3a..f91e16955fa8 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -218,6 +218,43 @@ static void powernv_create_core_node(PnvChip *chip, Pn= vCore *pc, void *fdt) servers_prop, sizeof(servers_prop)))); } =20 +static void powernv_populate_icp(PnvChip *chip, void *fdt, uint32_t pir, + uint32_t nr_threads) +{ + uint64_t addr =3D PNV_ICP_BASE(chip) | (pir << 12); + char *name; + const char compat[] =3D "IBM,power8-icp\0IBM,ppc-xicp"; + uint32_t irange[2], i, rsize; + uint64_t *reg; + int offset; + + irange[0] =3D cpu_to_be32(pir); + irange[1] =3D cpu_to_be32(nr_threads); + + rsize =3D sizeof(uint64_t) * 2 * nr_threads; + reg =3D g_malloc(rsize); + for (i =3D 0; i < nr_threads; i++) { + reg[i * 2] =3D cpu_to_be64(addr | ((pir + i) * 0x1000)); + reg[i * 2 + 1] =3D cpu_to_be64(0x1000); + } + + name =3D g_strdup_printf("interrupt-controller@%"PRIX64, addr); + offset =3D fdt_add_subnode(fdt, 0, name); + _FDT(offset); + g_free(name); + + _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); + _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); + _FDT((fdt_setprop_string(fdt, offset, "device_type", + "PowerPC-External-Interrupt-Presentation"))); + _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); + _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", + irange, sizeof(irange)))); + _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); + _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); + g_free(reg); +} + static void powernv_populate_chip(PnvChip *chip, void *fdt) { PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); @@ -231,6 +268,10 @@ static void powernv_populate_chip(PnvChip *chip, void = *fdt) PnvCore *pnv_core =3D PNV_CORE(chip->cores + i * typesize); =20 powernv_create_core_node(chip, pnv_core, fdt); + + /* Interrupt Control Presenters (ICP). One per core. */ + powernv_populate_icp(chip, fdt, pnv_core->pir, + CPU_CORE(pnv_core)->nr_threads); } =20 if (chip->ram_size) { @@ -663,6 +704,38 @@ static void pnv_chip_init(Object *obj) object_property_add_child(obj, "lpc", OBJECT(&chip->lpc), NULL); } =20 +static void pnv_chip_icp_realize(PnvChip *chip, Error **errp) +{ + PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); + char *typename =3D pnv_core_typename(pcc->cpu_model); + size_t typesize =3D object_type_get_instance_size(typename); + int i, j; + char *name; + XICSFabric *xi =3D XICS_FABRIC(qdev_get_machine()); + + name =3D g_strdup_printf("icp-%x", chip->chip_id); + memory_region_init(&chip->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip->icp_mmio); + g_free(name); + + sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); + + /* Map the ICP registers for each thread */ + for (i =3D 0; i < chip->nr_cores; i++) { + PnvCore *pnv_core =3D PNV_CORE(chip->cores + i * typesize); + int core_hwid =3D CPU_CORE(pnv_core)->core_id; + + for (j =3D 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { + uint32_t pir =3D pcc->core_pir(chip, core_hwid) + j; + PnvICPState *icp =3D PNV_ICP(xics_icp_get(xi, pir)); + + memory_region_add_subregion(&chip->icp_mmio, pir << 12, &icp->= mmio); + } + } + + g_free(typename); +} + static void pnv_chip_realize(DeviceState *dev, Error **errp) { PnvChip *chip =3D PNV_CHIP(dev); @@ -729,6 +802,14 @@ static void pnv_chip_realize(DeviceState *dev, Error *= *errp) } g_free(typename); =20 + /* Interrupt Management Area. This is the memory region holding + * all the Interrupt Control Presenter (ICP) registers */ + pnv_chip_icp_realize(chip, &error); + if (error) { + error_propagate(errp, error); + return; + } + /* Create LPC controller */ object_property_set_bool(OBJECT(&chip->lpc), true, "realized", &error_fatal); diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index cfd059fc49db..8e8ca548967d 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -55,6 +55,7 @@ typedef struct PnvChip { MemoryRegion xscom_mmio; MemoryRegion xscom; AddressSpace xscom_as; + MemoryRegion icp_mmio; =20 PnvLpcController lpc; } PnvChip; @@ -140,4 +141,22 @@ typedef struct PnvMachineState { #define PNV_XSCOM_BASE(chip) \ (chip->xscom_base + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE) =20 +/* + * XSCOM 0x20109CA defines the ICP BAR: + * + * 0:29 : bits 14 to 43 of address to define 1 MB region. + * 30 : 1 to enable ICP to receive loads/stores against its BAR region + * 31:63 : Constant 0 + * + * Usually defined as : + * + * 0xffffe00200000000 -> 0x0003ffff80000000 + * 0xffffe00600000000 -> 0x0003ffff80100000 + * 0xffffe02200000000 -> 0x0003ffff80800000 + * 0xffffe02600000000 -> 0x0003ffff80900000 + */ +#define PNV_ICP_SIZE 0x0000000000100000ull +#define PNV_ICP_BASE(chip) \ + (0x0003ffff80000000ull + (uint64_t) PNV_CHIP_INDEX(chip) * PNV_ICP_SIZ= E) + #endif /* _PPC_PNV_H */ --=20 2.7.4