From nobody Mon May 6 06:09:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1489491443427523.8868098894683; Tue, 14 Mar 2017 04:37:23 -0700 (PDT) Received: from localhost ([::1]:57883 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cnklU-0003md-7G for importer@patchew.org; Tue, 14 Mar 2017 07:37:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53041) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cnkgd-0000kU-12 for qemu-devel@nongnu.org; Tue, 14 Mar 2017 07:32:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cnkgb-00089o-Qb for qemu-devel@nongnu.org; Tue, 14 Mar 2017 07:32:18 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:48836) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cnkgb-0007v8-Ip for qemu-devel@nongnu.org; Tue, 14 Mar 2017 07:32:17 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1cnkgR-0002E7-Gc for qemu-devel@nongnu.org; Tue, 14 Mar 2017 11:32:07 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 14 Mar 2017 11:32:04 +0000 Message-Id: <1489491125-23648-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1489491125-23648-1-git-send-email-peter.maydell@linaro.org> References: <1489491125-23648-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 1/2] target/arm: implement armv8 PMUSERENR (user-mode enable bits) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Andrew Baumann In armv8, this register implements more than a single bit, with fine-grained enables for read access to event counters, cycles counters, and write access to the software increment. This change implements those checks using custom access functions for the relevant registers. Signed-off-by: Andrew Baumann Message-id: 20170228215801.10472-2-Andrew.Baumann@microsoft.com Reviewed-by: Peter Maydell [PMM: move a couple of access functions to be only compiled ifndef CONFIG_USER_ONLY to avoid compiler warnings] Signed-off-by: Peter Maydell --- target/arm/helper.c | 79 +++++++++++++++++++++++++++++++++++++++++++++++--= ---- 1 file changed, 71 insertions(+), 8 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 76b608f..8646a7a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -885,7 +885,7 @@ static CPAccessResult pmreg_access(CPUARMState *env, co= nst ARMCPRegInfo *ri, */ int el =3D arm_current_el(env); =20 - if (el =3D=3D 0 && !env->cp15.c9_pmuserenr) { + if (el =3D=3D 0 && !(env->cp15.c9_pmuserenr & 1)) { return CP_ACCESS_TRAP; } if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM) @@ -899,8 +899,67 @@ static CPAccessResult pmreg_access(CPUARMState *env, c= onst ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 +static CPAccessResult pmreg_access_xevcntr(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + /* ER: event counter read trap control */ + if (arm_feature(env, ARM_FEATURE_V8) + && arm_current_el(env) =3D=3D 0 + && (env->cp15.c9_pmuserenr & (1 << 3)) !=3D 0 + && isread) { + return CP_ACCESS_OK; + } + + return pmreg_access(env, ri, isread); +} + +static CPAccessResult pmreg_access_swinc(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + /* SW: software increment write trap control */ + if (arm_feature(env, ARM_FEATURE_V8) + && arm_current_el(env) =3D=3D 0 + && (env->cp15.c9_pmuserenr & (1 << 1)) !=3D 0 + && !isread) { + return CP_ACCESS_OK; + } + + return pmreg_access(env, ri, isread); +} + #ifndef CONFIG_USER_ONLY =20 +static CPAccessResult pmreg_access_selr(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + /* ER: event counter read trap control */ + if (arm_feature(env, ARM_FEATURE_V8) + && arm_current_el(env) =3D=3D 0 + && (env->cp15.c9_pmuserenr & (1 << 3)) !=3D 0) { + return CP_ACCESS_OK; + } + + return pmreg_access(env, ri, isread); +} + +static CPAccessResult pmreg_access_ccntr(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + /* CR: cycle counter read trap control */ + if (arm_feature(env, ARM_FEATURE_V8) + && arm_current_el(env) =3D=3D 0 + && (env->cp15.c9_pmuserenr & (1 << 2)) !=3D 0 + && isread) { + return CP_ACCESS_OK; + } + + return pmreg_access(env, ri, isread); +} + static inline bool arm_ccnt_enabled(CPUARMState *env) { /* This does not support checking PMCCFILTR_EL0 register */ @@ -1068,7 +1127,11 @@ static uint64_t pmxevtyper_read(CPUARMState *env, co= nst ARMCPRegInfo *ri) static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - env->cp15.c9_pmuserenr =3D value & 1; + if (arm_feature(env, ARM_FEATURE_V8)) { + env->cp15.c9_pmuserenr =3D value & 0xf; + } else { + env->cp15.c9_pmuserenr =3D value & 1; + } } =20 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1212,25 +1275,25 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .raw_writefn =3D raw_write }, /* Unimplemented so WI. */ { .name =3D "PMSWINC", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D = 0, .opc2 =3D 4, - .access =3D PL0_W, .accessfn =3D pmreg_access, .type =3D ARM_CP_NOP = }, + .access =3D PL0_W, .accessfn =3D pmreg_access_swinc, .type =3D ARM_C= P_NOP }, #ifndef CONFIG_USER_ONLY { .name =3D "PMSELR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 5, .access =3D PL0_RW, .type =3D ARM_CP_ALIAS, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmselr), - .accessfn =3D pmreg_access, .writefn =3D pmselr_write, + .accessfn =3D pmreg_access_selr, .writefn =3D pmselr_write, .raw_writefn =3D raw_write}, { .name =3D "PMSELR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 5, - .access =3D PL0_RW, .accessfn =3D pmreg_access, + .access =3D PL0_RW, .accessfn =3D pmreg_access_selr, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmselr), .writefn =3D pmselr_write, .raw_writefn =3D raw_write, }, { .name =3D "PMCCNTR", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 =3D = 0, .opc2 =3D 0, .access =3D PL0_RW, .resetvalue =3D 0, .type =3D ARM_CP_IO, .readfn =3D pmccntr_read, .writefn =3D pmccntr_write32, - .accessfn =3D pmreg_access }, + .accessfn =3D pmreg_access_ccntr }, { .name =3D "PMCCNTR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 0, - .access =3D PL0_RW, .accessfn =3D pmreg_access, + .access =3D PL0_RW, .accessfn =3D pmreg_access_ccntr, .type =3D ARM_CP_IO, .readfn =3D pmccntr_read, .writefn =3D pmccntr_write, }, #endif @@ -1251,7 +1314,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { /* Unimplemented, RAZ/WI. */ { .name =3D "PMXEVCNTR", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 = =3D 0, .opc2 =3D 2, .access =3D PL0_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, - .accessfn =3D pmreg_access }, + .accessfn =3D pmreg_access_xevcntr }, { .name =3D "PMUSERENR", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 0, .access =3D PL0_R | PL1_RW, .accessfn =3D access_tpm, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmuserenr), --=20 2.7.4 From nobody Mon May 6 06:09:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1489491324373956.7630158861872; Tue, 14 Mar 2017 04:35:24 -0700 (PDT) Received: from localhost ([::1]:57870 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cnkja-0002Ev-5B for importer@patchew.org; Tue, 14 Mar 2017 07:35:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53024) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cnkgb-0000im-TQ for qemu-devel@nongnu.org; Tue, 14 Mar 2017 07:32:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cnkgb-000897-06 for qemu-devel@nongnu.org; Tue, 14 Mar 2017 07:32:17 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:48836) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cnkga-0007v8-Pv for qemu-devel@nongnu.org; Tue, 14 Mar 2017 07:32:16 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1cnkgR-0002EU-VV for qemu-devel@nongnu.org; Tue, 14 Mar 2017 11:32:07 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 14 Mar 2017 11:32:05 +0000 Message-Id: <1489491125-23648-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1489491125-23648-1-git-send-email-peter.maydell@linaro.org> References: <1489491125-23648-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 2/2] target/arm/arm-powerctl: Fix psci info return values X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Andrew Jones The power state spec section 5.1.5 AFFINITY_INFO defines the affinity info return values as 0 ON 1 OFF 2 ON_PENDING I grepped QEMU for power_state to ensure that no assumptions of OFF=3D0 were being made. Signed-off-by: Andrew Jones Message-id: 20170303123232.4967-1-drjones@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 25ceaab..a8aabce 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -536,8 +536,8 @@ typedef void ARMELChangeHook(ARMCPU *cpu, void *opaque); /* These values map onto the return values for * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ typedef enum ARMPSCIState { - PSCI_OFF =3D 0, - PSCI_ON =3D 1, + PSCI_ON =3D 0, + PSCI_OFF =3D 1, PSCI_ON_PENDING =3D 2 } ARMPSCIState; =20 --=20 2.7.4