From nobody Thu Nov 6 14:08:45 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1489298374473496.12852636144225; Sat, 11 Mar 2017 21:59:34 -0800 (PST) Received: from localhost ([::1]:45703 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cmwXV-0005TN-4Y for importer@patchew.org; Sun, 12 Mar 2017 00:59:33 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54896) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cmwWj-0005S5-Lg for qemu-devel@nongnu.org; Sun, 12 Mar 2017 00:58:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cmwWh-0004PD-W7 for qemu-devel@nongnu.org; Sun, 12 Mar 2017 00:58:45 -0500 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:36447) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cmwWh-0004P7-OQ for qemu-devel@nongnu.org; Sun, 12 Mar 2017 00:58:43 -0500 Received: by mail-pf0-x242.google.com with SMTP id j5so15447030pfb.3 for ; Sat, 11 Mar 2017 21:58:43 -0800 (PST) Received: from localhost.localdomain (118-92-230-15.dsl.dyn.ihug.co.nz. [118.92.230.15]) by smtp.gmail.com with ESMTPSA id i15sm26874753pfj.0.2017.03.11.21.58.38 (version=TLS1 cipher=AES128-SHA bits=128/128); Sat, 11 Mar 2017 21:58:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=philjordan-eu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8IBBloCcdLlVsEuEh0YVmpcHyD5u8RI2ITaz4dq/dz8=; b=f6g1397H8FppN4E3xE14ZNwF2coI8umXy5+uvCn6bsXADQPqiKHa6yiXy/nu/s13Hp AmHZ9J1Uoe3aIG26C7/8HGq5NQHYXuVOTkXP+3gXY2gp/Wn5kBSNZ2mgxuO94d0wb7XJ vDVLkmqb3vtrIDRH0rLpnYxo054ruFtQpW+rPZI8slMovuUGXmWkh3sMb8awJduWOd68 9ThnYP9ssrXCpemH2RIPx4ojY/wvDguQFKPhMvGkUF78iFLUO2eqddAtxB6iUXyezn+B QlZhWKZkKPtj4cEmSyvc4GaEALxYJ+lyR9mjaRC8X5JMZ2NjieiO6UUTx0rRv19RK1j5 4hbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8IBBloCcdLlVsEuEh0YVmpcHyD5u8RI2ITaz4dq/dz8=; b=D2gIGw6QxuArXChlk/W4/16lWPIMqgfWWHbV5ESMctj8WNDI2soqNLZ/aUYH6o2WFu tJx/jqzFhe2RugBWe6Uubkl60noNyLnNGzi7RCS2okmoIznpIn5BHvFihPYNN3B4vUKz hZZSdja+Dc0vN349dVN2CTZNZXkUm2RFacO+ubDtR0cWSE6EpfrokDZUE6OiB3u7u1NR 0w2a4p029v0DEUfgqDzD5KZzOZrZU9Gv9O/wquPB4sw+vA6jY7OzXMV3UKMOBySlIiXE 97UHLxLADRPPHeE/kTrdlhBjoH4vLQoIC5sIlHjWhkK+Pt7NHb7d7Bth6cOv5nRTbic5 iytQ== X-Gm-Message-State: AMke39konGf7nWJKUkPDb9Mnbb2b5J+m6XzZIzUaq+NGB6HHrRmctBUv59bTJClijaVi5g== X-Received: by 10.84.241.130 with SMTP id b2mr38456042pll.32.1489298322681; Sat, 11 Mar 2017 21:58:42 -0800 (PST) From: Phil Dennis-Jordan To: "Michael S. Tsirkin" , Igor Mammedov , Paolo Bonzini , Richard Henderson , Eduardo Habkost , qemu-devel@nongnu.org, Laszlo Ersek Date: Sun, 12 Mar 2017 18:58:10 +1300 Message-Id: <1489298291-25154-2-git-send-email-phil@philjordan.eu> X-Mailer: git-send-email 2.3.2 (Apple Git-55) In-Reply-To: <1489298291-25154-1-git-send-email-phil@philjordan.eu> References: <1489298291-25154-1-git-send-email-phil@philjordan.eu> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH v2 1/2] hw/i386: Use Rev3 FADT (ACPI 2.0) instead of Rev1 to improve guest OS support. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Phil Dennis-Jordan Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This updates the FADT generated for x86/64 machine types from Revision 1 to= 3. (Based on ACPI standard 2.0 instead of 1.0) The intention is to expose = the reset register information to guest operating systems which require it,= specifically OS X/macOS. Revision 1 FADTs do not contain the fields relati= ng to the reset register. The new layout and contents remains backwards-compatible with operating sys= tems which only support ACPI 1.0, as the existing fields are not modified b= y this change, as the 64-bit and 32-bit variants are allowed to co-exist ac= cording to the ACPI 2.0 standard. No regressions became apparent in tests w= ith a range of Windows (XP-10) and Linux versions. Signed-off-by: Phil Dennis-Jordan --- hw/i386/acpi-build.c | 32 +++++++++++++++++-- include/hw/acpi/acpi-defs.h | 77 +++++++++++++++++++++--------------------= ---- tests/bios-tables-test.c | 4 +-- 3 files changed, 67 insertions(+), 46 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 2073108..7997f06 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -272,7 +272,7 @@ build_facs(GArray *table_data, BIOSLinker *linker) } =20 /* Load chipset information in FADT */ -static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm) +static void fadt_setup(AcpiFadtDescriptorRev3 *fadt, AcpiPmInfo *pm) { fadt->model =3D 1; fadt->reserved1 =3D 0; @@ -304,6 +304,28 @@ static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, A= cpiPmInfo *pm) fadt->flags |=3D cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_M= ODEL); } fadt->century =3D RTC_CENTURY; + + fadt->flags |=3D cpu_to_le32(1 << ACPI_FADT_F_RESET_REG_SUP); + fadt->reset_value =3D 0xf; + fadt->reset_register.space_id =3D AML_SYSTEM_IO; + fadt->reset_register.bit_width =3D 8; + fadt->reset_register.address =3D cpu_to_le64(ICH9_RST_CNT_IOPORT); + + fadt->xpm1a_event_block.space_id =3D AML_SYSTEM_IO; + fadt->xpm1a_event_block.bit_width =3D fadt->pm1_evt_len * 8; + fadt->xpm1a_event_block.address =3D cpu_to_le64(pm->io_base); + + fadt->xpm1a_control_block.space_id =3D AML_SYSTEM_IO; + fadt->xpm1a_control_block.bit_width =3D fadt->pm1_cnt_len * 8; + fadt->xpm1a_control_block.address =3D cpu_to_le64(pm->io_base + 0x4); + + fadt->xpm_timer_block.space_id =3D AML_SYSTEM_IO; + fadt->xpm_timer_block.bit_width =3D fadt->pm_tmr_len * 8; + fadt->xpm_timer_block.address =3D cpu_to_le64(pm->io_base + 0x8); + + fadt->xgpe0_block.space_id =3D AML_SYSTEM_IO; + fadt->xgpe0_block.bit_width =3D pm->gpe0_blk_len * 8; + fadt->xgpe0_block.address =3D cpu_to_le64(pm->gpe0_blk); } =20 =20 @@ -313,9 +335,10 @@ build_fadt(GArray *table_data, BIOSLinker *linker, Acp= iPmInfo *pm, unsigned facs_tbl_offset, unsigned dsdt_tbl_offset, const char *oem_id, const char *oem_table_id) { - AcpiFadtDescriptorRev1 *fadt =3D acpi_data_push(table_data, sizeof(*fa= dt)); + AcpiFadtDescriptorRev3 *fadt =3D acpi_data_push(table_data, sizeof(*fa= dt)); unsigned fw_ctrl_offset =3D (char *)&fadt->firmware_ctrl - table_data-= >data; unsigned dsdt_entry_offset =3D (char *)&fadt->dsdt - table_data->data; + unsigned xdsdt_entry_offset =3D (char *)&fadt->Xdsdt - table_data->dat= a; =20 /* FACS address to be filled by Guest linker */ bios_linker_loader_add_pointer(linker, @@ -327,9 +350,12 @@ build_fadt(GArray *table_data, BIOSLinker *linker, Acp= iPmInfo *pm, bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, dsdt_entry_offset, sizeof(fadt->dsdt), ACPI_BUILD_TABLE_FILE, dsdt_tbl_offset); + bios_linker_loader_add_pointer(linker, + ACPI_BUILD_TABLE_FILE, xdsdt_entry_offset, sizeof(fadt->Xdsdt), + ACPI_BUILD_TABLE_FILE, dsdt_tbl_offset); =20 build_header(linker, table_data, - (void *)fadt, "FACP", sizeof(*fadt), 1, oem_id, oem_table= _id); + (void *)fadt, "FACP", sizeof(*fadt), 3, oem_id, oem_table= _id); } =20 void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid, diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h index 4cc3630..293ee45 100644 --- a/include/hw/acpi/acpi-defs.h +++ b/include/hw/acpi/acpi-defs.h @@ -131,17 +131,37 @@ typedef struct AcpiTableHeader AcpiTableHeader; uint8_t duty_width; /* Bit width of duty cycle field in p_cnt reg *= / \ uint8_t day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM = */ \ uint8_t mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM= */ \ - uint8_t century; /* Index to century in RTC CMOS RAM */ - -struct AcpiFadtDescriptorRev1 -{ - ACPI_FADT_COMMON_DEF - uint8_t reserved4; /* Reserved */ - uint8_t reserved4a; /* Reserved */ - uint8_t reserved4b; /* Reserved */ - uint32_t flags; -} QEMU_PACKED; -typedef struct AcpiFadtDescriptorRev1 AcpiFadtDescriptorRev1; + uint8_t century; /* Index to century in RTC CMOS RAM */ \ + /* IA-PC Boot Architecture Flags (see below for individual flags) */ \ + uint16_t boot_flags; \ + uint8_t reserved; /* Reserved, must be zero */ \ + /* Miscellaneous flag bits (see below for individual flags) */ \ + uint32_t flags; \ + /* 64-bit address of the Reset register */ \ + struct AcpiGenericAddress reset_register; \ + /* Value to write to the reset_register port to reset the system */ \ + uint8_t reset_value; \ + /* ARM-Specific Boot Flags (see below for individual flags) (ACPI 5.1)= */ \ + uint16_t arm_boot_flags; \ + uint8_t minor_revision; /* FADT Minor Revision (ACPI 5.1) */ \ + uint64_t Xfacs; /* 64-bit physical address of FACS */ \ + uint64_t Xdsdt; /* 64-bit physical address of DSDT */ \ + /* 64-bit Extended Power Mgt 1a Event Reg Blk address */ \ + struct AcpiGenericAddress xpm1a_event_block; \ + /* 64-bit Extended Power Mgt 1b Event Reg Blk address */ \ + struct AcpiGenericAddress xpm1b_event_block; \ + /* 64-bit Extended Power Mgt 1a Control Reg Blk address */ \ + struct AcpiGenericAddress xpm1a_control_block; \ + /* 64-bit Extended Power Mgt 1b Control Reg Blk address */ \ + struct AcpiGenericAddress xpm1b_control_block; \ + /* 64-bit Extended Power Mgt 2 Control Reg Blk address */ \ + struct AcpiGenericAddress xpm2_control_block; \ + /* 64-bit Extended Power Mgt Timer Ctrl Reg Blk address */ \ + struct AcpiGenericAddress xpm_timer_block; \ + /* 64-bit Extended General Purpose Event 0 Reg Blk address */ \ + struct AcpiGenericAddress xgpe0_block; \ + /* 64-bit Extended General Purpose Event 1 Reg Blk address */ \ + struct AcpiGenericAddress xgpe1_block; \ =20 struct AcpiGenericAddress { uint8_t space_id; /* Address space where struct or register exi= sts */ @@ -151,38 +171,13 @@ struct AcpiGenericAddress { uint64_t address; /* 64-bit address of struct or register */ } QEMU_PACKED; =20 +struct AcpiFadtDescriptorRev3 { + ACPI_FADT_COMMON_DEF +} QEMU_PACKED; +typedef struct AcpiFadtDescriptorRev3 AcpiFadtDescriptorRev3; + struct AcpiFadtDescriptorRev5_1 { ACPI_FADT_COMMON_DEF - /* IA-PC Boot Architecture Flags (see below for individual flags) */ - uint16_t boot_flags; - uint8_t reserved; /* Reserved, must be zero */ - /* Miscellaneous flag bits (see below for individual flags) */ - uint32_t flags; - /* 64-bit address of the Reset register */ - struct AcpiGenericAddress reset_register; - /* Value to write to the reset_register port to reset the system */ - uint8_t reset_value; - /* ARM-Specific Boot Flags (see below for individual flags) (ACPI 5.1)= */ - uint16_t arm_boot_flags; - uint8_t minor_revision; /* FADT Minor Revision (ACPI 5.1) */ - uint64_t Xfacs; /* 64-bit physical address of FACS */ - uint64_t Xdsdt; /* 64-bit physical address of DSDT */ - /* 64-bit Extended Power Mgt 1a Event Reg Blk address */ - struct AcpiGenericAddress xpm1a_event_block; - /* 64-bit Extended Power Mgt 1b Event Reg Blk address */ - struct AcpiGenericAddress xpm1b_event_block; - /* 64-bit Extended Power Mgt 1a Control Reg Blk address */ - struct AcpiGenericAddress xpm1a_control_block; - /* 64-bit Extended Power Mgt 1b Control Reg Blk address */ - struct AcpiGenericAddress xpm1b_control_block; - /* 64-bit Extended Power Mgt 2 Control Reg Blk address */ - struct AcpiGenericAddress xpm2_control_block; - /* 64-bit Extended Power Mgt Timer Ctrl Reg Blk address */ - struct AcpiGenericAddress xpm_timer_block; - /* 64-bit Extended General Purpose Event 0 Reg Blk address */ - struct AcpiGenericAddress xgpe0_block; - /* 64-bit Extended General Purpose Event 1 Reg Blk address */ - struct AcpiGenericAddress xgpe1_block; /* 64-bit Sleep Control register (ACPI 5.0) */ struct AcpiGenericAddress sleep_control; /* 64-bit Sleep Status register (ACPI 5.0) */ diff --git a/tests/bios-tables-test.c b/tests/bios-tables-test.c index 88dbf97..73b9ae4 100644 --- a/tests/bios-tables-test.c +++ b/tests/bios-tables-test.c @@ -29,7 +29,7 @@ typedef struct { uint32_t rsdp_addr; AcpiRsdpDescriptor rsdp_table; AcpiRsdtDescriptorRev1 rsdt_table; - AcpiFadtDescriptorRev1 fadt_table; + AcpiFadtDescriptorRev3 fadt_table; AcpiFacsDescriptorRev1 facs_table; uint32_t *rsdt_tables_addr; int rsdt_tables_nr; @@ -126,7 +126,7 @@ static void test_acpi_rsdt_table(test_data *data) =20 static void test_acpi_fadt_table(test_data *data) { - AcpiFadtDescriptorRev1 *fadt_table =3D &data->fadt_table; + AcpiFadtDescriptorRev3 *fadt_table =3D &data->fadt_table; uint32_t addr; =20 /* FADT table comes first */ --=20 2.3.2 (Apple Git-55) From nobody Thu Nov 6 14:08:45 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1489298396720852.6871796492758; Sat, 11 Mar 2017 21:59:56 -0800 (PST) Received: from localhost ([::1]:45704 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cmwXr-0005fy-8U for importer@patchew.org; Sun, 12 Mar 2017 00:59:55 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54994) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cmwX1-0005dZ-8X for qemu-devel@nongnu.org; Sun, 12 Mar 2017 00:59:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cmwWw-0004S8-Kh for qemu-devel@nongnu.org; Sun, 12 Mar 2017 00:59:03 -0500 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:33123) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cmwWw-0004Rx-Ew for qemu-devel@nongnu.org; Sun, 12 Mar 2017 00:58:58 -0500 Received: by mail-pg0-x241.google.com with SMTP id 77so14697120pgc.0 for ; Sat, 11 Mar 2017 21:58:58 -0800 (PST) Received: from localhost.localdomain (118-92-230-15.dsl.dyn.ihug.co.nz. [118.92.230.15]) by smtp.gmail.com with ESMTPSA id i15sm26874753pfj.0.2017.03.11.21.58.53 (version=TLS1 cipher=AES128-SHA bits=128/128); Sat, 11 Mar 2017 21:58:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=philjordan-eu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NPwdh2AhlEJGZiVBXM9pedgkcelhkAOijYOxVB8bFFQ=; b=mxVmCWVEuAOAe/wMRtAlzce9fADeI7i6IRa2FCGSdsFAOVka0DxeV7h1toQ7JenDXd 1Emay3UEdPqP1YV9g4Ah8x77qx7L1aseaMiNVgxVZRlWE5eDD6T36/IB4RTjxDFk62l3 EuuTd2/rMbfnppVHpPfesp0LxCB9QF4xmb6IREHPk+U8ZQUVDwtcLsfij6KkYru3qaFF f7gW2wM56l1hK/OXTKFzr7iDoManEJkkA3PGXc1rWWK8+hQu0kY60x0YJyrJ12CVpn+d NCuqvapOwXNT6yVhTNUA1PCn5yPKG6BFSnp+D0zRpS3KXEbPYMAOkkdjmYJfOAFyl9gY i1vA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NPwdh2AhlEJGZiVBXM9pedgkcelhkAOijYOxVB8bFFQ=; b=C/X9lh0VYCliNxxU8PQxHwe9lX4mp+CBlLtQriLfber4m2J6MGiLGxdaeK2fVPUdmE pieSGnSRorTiJTePFBS1JfjN0ObvEMR59YGgjvQ6RdQpHIDPgnZV6wokv+ZHaZOAAZcV Ybf5CncNFbTQefUxc7ZyAd8QXjGPB3gPB6tPs+JKFV3IklbtF9KNjg42PvgjXRGrI+UW VXsOzbDYXAqfiMLNBZU4/y8GeHKxzxi3iK2SJ4NIWxGwYlp8XDNmsaqx+ZMN19oaUI6+ YkU+tmkyAICdisNic+InorX4SkTGhxMOlZr4xBTf+zs6gGd7zY/TsCJM9oa2lwp8i0Xk 5CFw== X-Gm-Message-State: AMke39lZvbKZzHwFwbJSFFmOgxLgQMpTcGBPvrD6ijU2Kf7E1KcEcR5xOcStXLsCnBUEhw== X-Received: by 10.84.133.193 with SMTP id f59mr37967719plf.64.1489298337437; Sat, 11 Mar 2017 21:58:57 -0800 (PST) From: Phil Dennis-Jordan To: "Michael S. Tsirkin" , Igor Mammedov , Paolo Bonzini , Richard Henderson , Eduardo Habkost , qemu-devel@nongnu.org, Laszlo Ersek Date: Sun, 12 Mar 2017 18:58:11 +1300 Message-Id: <1489298291-25154-3-git-send-email-phil@philjordan.eu> X-Mailer: git-send-email 2.3.2 (Apple Git-55) In-Reply-To: <1489298291-25154-1-git-send-email-phil@philjordan.eu> References: <1489298291-25154-1-git-send-email-phil@philjordan.eu> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v2 2/2] hw/i386: Build-time assertion on pc/q35 reset register being identical. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Phil Dennis-Jordan Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This adds a clarifying comment and build time assert to the FADT reset regi= ster field initialisation: the reset register is the same on both machine t= ypes. Signed-off-by: Phil Dennis-Jordan --- hw/i386/acpi-build.c | 3 +++ hw/pci-host/piix.c | 6 ------ include/hw/i386/pc.h | 6 ++++++ 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 7997f06..1d8c645 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -310,6 +310,9 @@ static void fadt_setup(AcpiFadtDescriptorRev3 *fadt, Ac= piPmInfo *pm) fadt->reset_register.space_id =3D AML_SYSTEM_IO; fadt->reset_register.bit_width =3D 8; fadt->reset_register.address =3D cpu_to_le64(ICH9_RST_CNT_IOPORT); + /* The above need not be conditional on machine type because the reset= port + * happens to be the same on PIIX (pc) and ICH9 (q35). */ + QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT !=3D RCR_IOPORT); =20 fadt->xpm1a_event_block.space_id =3D AML_SYSTEM_IO; fadt->xpm1a_event_block.bit_width =3D fadt->pm1_evt_len * 8; diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c index f9218aa..bf4221d 100644 --- a/hw/pci-host/piix.c +++ b/hw/pci-host/piix.c @@ -58,12 +58,6 @@ typedef struct I440FXState { #define XEN_PIIX_NUM_PIRQS 128ULL #define PIIX_PIRQC 0x60 =20 -/* - * Reset Control Register: PCI-accessible ISA-Compatible Register at addre= ss - * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000). - */ -#define RCR_IOPORT 0xcf9 - typedef struct PIIX3State { PCIDevice dev; =20 diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index ab303c7..10cb55f 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -303,6 +303,12 @@ typedef struct PCII440FXState PCII440FXState; =20 #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX" =20 +/* + * Reset Control Register: PCI-accessible ISA-Compatible Register at addre= ss + * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000). + */ +#define RCR_IOPORT 0xcf9 + PCIBus *i440fx_init(const char *host_type, const char *pci_type, PCII440FXState **pi440fx_state, int *piix_devfn, ISABus **isa_bus, qemu_irq *pic, --=20 2.3.2 (Apple Git-55)