From nobody Sun Apr 28 23:40:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1488970587022296.9809139749484; Wed, 8 Mar 2017 02:56:27 -0800 (PST) Received: from localhost ([::1]:55529 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1clZGb-00019E-Oj for importer@patchew.org; Wed, 08 Mar 2017 05:56:25 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36969) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1clZDW-0007ao-5I for qemu-devel@nongnu.org; Wed, 08 Mar 2017 05:53:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1clZDR-00036M-W9 for qemu-devel@nongnu.org; Wed, 08 Mar 2017 05:53:14 -0500 Received: from 6.mo177.mail-out.ovh.net ([46.105.51.249]:51672) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1clZDR-00034d-PY for qemu-devel@nongnu.org; Wed, 08 Mar 2017 05:53:09 -0500 Received: from player714.ha.ovh.net (b7.ovh.net [213.186.33.57]) by mo177.mail-out.ovh.net (Postfix) with ESMTP id 7C4F73BD6F for ; Wed, 8 Mar 2017 11:53:01 +0100 (CET) Received: from zorba.kaod.org.com (LFbn-1-10647-27.w90-89.abo.wanadoo.fr [90.89.233.27]) (Authenticated sender: clg@kaod.org) by player714.ha.ovh.net (Postfix) with ESMTPSA id 56AEA3C0093; Wed, 8 Mar 2017 11:52:57 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 8 Mar 2017 11:52:44 +0100 Message-Id: <1488970371-8865-2-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1488970371-8865-1-git-send-email-clg@kaod.org> References: <1488970371-8865-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 16324704224644336614 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelhedrgeeggddujecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.51.249 Subject: [Qemu-devel] [PATCH for-2.10 1/8] ppc/xics: add a xics_get_cpu_index_by_pir() helper X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This helper will be used to translate the server number of the XIVE (which is a PIR) into an ICPState index number (which is a cpu index). Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xics.c | 11 +++++++++++ hw/ppc/ppc.c | 16 ++++++++++++++++ include/hw/ppc/xics.h | 1 + target/ppc/cpu.h | 10 ++++++++++ 4 files changed, 38 insertions(+) diff --git a/hw/intc/xics.c b/hw/intc/xics.c index e740989a1162..209e1a75ecb9 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -49,6 +49,17 @@ int xics_get_cpu_index_by_dt_id(int cpu_dt_id) return -1; } =20 +int xics_get_cpu_index_by_pir(int pir) +{ + PowerPCCPU *cpu =3D ppc_get_vcpu_by_pir(pir); + + if (cpu) { + return cpu->parent_obj.cpu_index; + } + + return -1; +} + void xics_cpu_destroy(XICSFabric *xi, PowerPCCPU *cpu) { CPUState *cs =3D CPU(cpu); diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index 5f93083d4a16..94bbe382a73a 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -1379,6 +1379,22 @@ PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id) return NULL; } =20 +PowerPCCPU *ppc_get_vcpu_by_pir(int pir) +{ + CPUState *cs; + + CPU_FOREACH(cs) { + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + CPUPPCState *env =3D &cpu->env; + + if (env->spr_cb[SPR_PIR].default_value =3D=3D pir) { + return cpu; + } + } + + return NULL; +} + void ppc_cpu_parse_features(const char *cpu_model) { CPUClass *cc; diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h index 9a5e715fe553..42bd24e975cb 100644 --- a/include/hw/ppc/xics.h +++ b/include/hw/ppc/xics.h @@ -173,6 +173,7 @@ void xics_cpu_destroy(XICSFabric *xi, PowerPCCPU *cpu); =20 /* Internal XICS interfaces */ int xics_get_cpu_index_by_dt_id(int cpu_dt_id); +int xics_get_cpu_index_by_pir(int pir); =20 void icp_set_cppr(ICPState *icp, uint8_t cppr); void icp_set_mfrr(ICPState *icp, uint8_t mfrr); diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 7c4a1f50b38b..24a5af95cb45 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2518,5 +2518,15 @@ int ppc_get_vcpu_dt_id(PowerPCCPU *cpu); */ PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id); =20 +/** + * ppc_get_vcpu_by_pir_id: + * @pir: Processor Identifier Register (SPR_PIR) + * + * Searches for a CPU by @pir. + * + * Returns: a PowerPCCPU struct + */ +PowerPCCPU *ppc_get_vcpu_by_pir(int pir); + void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len); #endif /* PPC_CPU_H */ --=20 2.7.4 From nobody Sun Apr 28 23:40:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1488970458091685.3188719028655; Wed, 8 Mar 2017 02:54:18 -0800 (PST) Received: from localhost ([::1]:55513 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1clZEW-0007cl-Lv for importer@patchew.org; Wed, 08 Mar 2017 05:54:16 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36960) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1clZDW-0007ah-00 for qemu-devel@nongnu.org; Wed, 08 Mar 2017 05:53:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1clZDV-00037G-4M for qemu-devel@nongnu.org; Wed, 08 Mar 2017 05:53:14 -0500 Received: from 9.mo177.mail-out.ovh.net ([46.105.72.238]:57780) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1clZDU-00035G-UE for qemu-devel@nongnu.org; Wed, 08 Mar 2017 05:53:13 -0500 Received: from player714.ha.ovh.net (b7.ovh.net [213.186.33.57]) by mo177.mail-out.ovh.net (Postfix) with ESMTP id BF9023BD53 for ; Wed, 8 Mar 2017 11:53:05 +0100 (CET) Received: from zorba.kaod.org.com (LFbn-1-10647-27.w90-89.abo.wanadoo.fr [90.89.233.27]) (Authenticated sender: clg@kaod.org) by player714.ha.ovh.net (Postfix) with ESMTPSA id 7A9E73C0093; Wed, 8 Mar 2017 11:53:01 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 8 Mar 2017 11:52:45 +0100 Message-Id: <1488970371-8865-3-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1488970371-8865-1-git-send-email-clg@kaod.org> References: <1488970371-8865-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 16325830124675894246 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelhedrgeeggddujecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.72.238 Subject: [Qemu-devel] [PATCH for-2.10 2/8] ppc/xics: add an ics_eoi() handler to XICSFabric X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This handler will be required by PowerPC machines using multiple ICS objects, like this is the case for PowerNV. Also update the sPAPR machine to use the new handler. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xics.c | 9 +++------ hw/ppc/spapr.c | 11 +++++++++++ include/hw/ppc/xics.h | 2 ++ 3 files changed, 16 insertions(+), 6 deletions(-) diff --git a/hw/intc/xics.c b/hw/intc/xics.c index 209e1a75ecb9..e6fecd6e1a89 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -169,7 +169,7 @@ void ics_resend(ICSState *ics) } } =20 -static void ics_eoi(ICSState *ics, int nr) +void ics_eoi(ICSState *ics, int nr) { ICSStateClass *k =3D ICS_BASE_GET_CLASS(ics); =20 @@ -268,7 +268,6 @@ void icp_eoi(ICPState *icp, uint32_t xirr) { XICSFabric *xi =3D icp->xics; XICSFabricClass *xic =3D XICS_FABRIC_GET_CLASS(xi); - ICSState *ics; uint32_t irq; =20 /* Send EOI -> ICS */ @@ -276,10 +275,8 @@ void icp_eoi(ICPState *icp, uint32_t xirr) trace_xics_icp_eoi(icp->cs->cpu_index, xirr, icp->xirr); irq =3D xirr & XISR_MASK; =20 - ics =3D xic->ics_get(xi, irq); - if (ics) { - ics_eoi(ics, irq); - } + xic->ics_eoi(xi, irq); + if (!XISR(icp)) { icp_resend(icp); } diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index c3bb99160545..043629cc5c54 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -3024,6 +3024,16 @@ static void spapr_ics_resend(XICSFabric *dev) ics_resend(spapr->ics); } =20 +static void spapr_ics_eoi(XICSFabric *xi, int irq) +{ + ICSState *ics; + + ics =3D spapr_ics_get(xi, irq); + if (ics) { + ics_eoi(ics, irq); + } +} + static ICPState *spapr_icp_get(XICSFabric *xi, int server) { sPAPRMachineState *spapr =3D SPAPR_MACHINE(xi); @@ -3094,6 +3104,7 @@ static void spapr_machine_class_init(ObjectClass *oc,= void *data) vhc->get_patbe =3D spapr_get_patbe; xic->ics_get =3D spapr_ics_get; xic->ics_resend =3D spapr_ics_resend; + xic->ics_eoi =3D spapr_ics_eoi; xic->icp_get =3D spapr_icp_get; ispc->print_info =3D spapr_pic_print_info; } diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h index 42bd24e975cb..00b003b2392d 100644 --- a/include/hw/ppc/xics.h +++ b/include/hw/ppc/xics.h @@ -155,6 +155,7 @@ typedef struct XICSFabricClass { InterfaceClass parent; ICSState *(*ics_get)(XICSFabric *xi, int irq); void (*ics_resend)(XICSFabric *xi); + void (*ics_eoi)(XICSFabric *xi, int irq); ICPState *(*icp_get)(XICSFabric *xi, int server); } XICSFabricClass; =20 @@ -189,6 +190,7 @@ void icp_pic_print_info(ICPState *icp, Monitor *mon); void ics_pic_print_info(ICSState *ics, Monitor *mon); =20 void ics_resend(ICSState *ics); +void ics_eoi(ICSState *ics, int irq); void icp_resend(ICPState *ss); =20 typedef struct sPAPRMachineState sPAPRMachineState; --=20 2.7.4 From nobody Sun Apr 28 23:40:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1488970697988116.46774397204399; Wed, 8 Mar 2017 02:58:17 -0800 (PST) Received: from localhost ([::1]:55536 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1clZIO-0002ok-Lx for importer@patchew.org; Wed, 08 Mar 2017 05:58:16 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37006) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1clZDZ-0007eR-UY for qemu-devel@nongnu.org; Wed, 08 Mar 2017 05:53:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1clZDV-00037V-GZ for qemu-devel@nongnu.org; Wed, 08 Mar 2017 05:53:18 -0500 Received: from mo177.mail-out.ovh.net ([178.32.228.177]:49274) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1clZDV-00036t-6Z for qemu-devel@nongnu.org; Wed, 08 Mar 2017 05:53:13 -0500 Received: from player714.ha.ovh.net (b7.ovh.net [213.186.33.57]) by mo177.mail-out.ovh.net (Postfix) with ESMTP id C43B732945 for ; Wed, 8 Mar 2017 11:53:09 +0100 (CET) Received: from zorba.kaod.org.com (LFbn-1-10647-27.w90-89.abo.wanadoo.fr [90.89.233.27]) (Authenticated sender: clg@kaod.org) by player714.ha.ovh.net (Postfix) with ESMTPSA id 9E9AF3C006B; Wed, 8 Mar 2017 11:53:05 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 8 Mar 2017 11:52:46 +0100 Message-Id: <1488970371-8865-4-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1488970371-8865-1-git-send-email-clg@kaod.org> References: <1488970371-8865-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 16326956027808943078 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelhedrgeeggddujecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 178.32.228.177 Subject: [Qemu-devel] [PATCH for-2.10 3/8] ppc/pnv: create the ICP and ICS objects under the machine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Like this is done for the sPAPR machine, we use a simple array under the PowerNV machine to store the Interrupt Control Presenters (ICP) objects, one for each vCPU. This array is indexed by 'cpu_index' of the CPUState. We use a list to hold the different Interrupt Control Sources (ICS) objects, as PowerNV needs to handle multiple sources: for PCI-E and for the Processor Service Interface (PSI). Finally, to interface with the XICS layer which manipulates the ICP and ICS objects, we extend the PowerNV machine with an XICSFabric interface and its associated handlers. Signed-off-by: C=C3=A9dric Le Goater --- hw/ppc/pnv.c | 89 +++++++++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/ppc/pnv.h | 4 +++ include/hw/ppc/xics.h | 1 + 3 files changed, 94 insertions(+) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 09f0d22defb8..461d3535e99c 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -32,6 +32,8 @@ #include "exec/address-spaces.h" #include "qemu/cutils.h" #include "qapi/visitor.h" +#include "monitor/monitor.h" +#include "hw/intc/intc.h" =20 #include "hw/ppc/pnv_xscom.h" =20 @@ -416,6 +418,23 @@ static void ppc_powernv_init(MachineState *machine) machine->cpu_model =3D "POWER8"; } =20 + /* Create the Interrupt Control Presenters before the vCPUs */ + pnv->nr_servers =3D pnv->num_chips * smp_cores * smp_threads; + pnv->icps =3D g_new0(ICPState, pnv->nr_servers); + for (i =3D 0; i < pnv->nr_servers; i++) { + ICPState *icp =3D &pnv->icps[i]; + object_initialize(icp, sizeof(*icp), TYPE_ICP); + qdev_set_parent_bus(DEVICE(icp), sysbus_get_default()); + object_property_add_child(OBJECT(pnv), "icp[*]", OBJECT(icp), + &error_fatal); + object_property_add_const_link(OBJECT(icp), "xics", OBJECT(pnv), + &error_fatal); + object_property_set_bool(OBJECT(icp), true, "realized", &error_fat= al); + } + + /* and the list of Interrupt Control Sources */ + QLIST_INIT(&pnv->ics); + /* Create the processor chips */ chip_typename =3D g_strdup_printf(TYPE_PNV_CHIP "-%s", machine->cpu_mo= del); if (!object_class_by_name(chip_typename)) { @@ -742,6 +761,48 @@ static void pnv_get_num_chips(Object *obj, Visitor *v,= const char *name, visit_type_uint32(v, name, &POWERNV_MACHINE(obj)->num_chips, errp); } =20 +static ICSState *pnv_ics_get(XICSFabric *xi, int irq) +{ + PnvMachineState *pnv =3D POWERNV_MACHINE(xi); + ICSState *ics; + + QLIST_FOREACH(ics, &pnv->ics, list) { + if (ics_valid_irq(ics, irq)) { + return ics; + } + } + return NULL; +} + +static void pnv_ics_resend(XICSFabric *xi) +{ + PnvMachineState *pnv =3D POWERNV_MACHINE(xi); + ICSState *ics; + + QLIST_FOREACH(ics, &pnv->ics, list) { + ics_resend(ics); + } +} + +static void pnv_ics_eoi(XICSFabric *xi, int irq) +{ + PnvMachineState *pnv =3D POWERNV_MACHINE(xi); + ICSState *ics; + + QLIST_FOREACH(ics, &pnv->ics, list) { + if (ics_valid_irq(ics, irq)) { + ics_eoi(ics, irq); + } + } +} + +static ICPState *pnv_icp_get(XICSFabric *xi, int server) +{ + PnvMachineState *pnv =3D POWERNV_MACHINE(xi); + + return (server < pnv->nr_servers) ? &pnv->icps[server] : NULL; +} + static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -783,9 +844,27 @@ static void powernv_machine_class_props_init(ObjectCla= ss *oc) NULL); } =20 +static void pnv_pic_print_info(InterruptStatsProvider *obj, + Monitor *mon) +{ + PnvMachineState *pnv =3D POWERNV_MACHINE(obj); + ICSState *ics; + int i; + + for (i =3D 0; i < pnv->nr_servers; i++) { + icp_pic_print_info(&pnv->icps[i], mon); + } + + QLIST_FOREACH(ics, &pnv->ics, list) { + ics_pic_print_info(ics, mon); + } +} + static void powernv_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); + XICSFabricClass *xic =3D XICS_FABRIC_CLASS(oc); + InterruptStatsProviderClass *ispc =3D INTERRUPT_STATS_PROVIDER_CLASS(o= c); =20 mc->desc =3D "IBM PowerNV (Non-Virtualized)"; mc->init =3D ppc_powernv_init; @@ -796,6 +875,11 @@ static void powernv_machine_class_init(ObjectClass *oc= , void *data) mc->no_parallel =3D 1; mc->default_boot_order =3D NULL; mc->default_ram_size =3D 1 * G_BYTE; + xic->icp_get =3D pnv_icp_get; + xic->ics_get =3D pnv_ics_get; + xic->ics_eoi =3D pnv_ics_eoi; + xic->ics_resend =3D pnv_ics_resend; + ispc->print_info =3D pnv_pic_print_info; =20 powernv_machine_class_props_init(oc); } @@ -806,6 +890,11 @@ static const TypeInfo powernv_machine_info =3D { .instance_size =3D sizeof(PnvMachineState), .instance_init =3D powernv_machine_initfn, .class_init =3D powernv_machine_class_init, + .interfaces =3D (InterfaceInfo[]) { + { TYPE_XICS_FABRIC }, + { TYPE_INTERRUPT_STATS_PROVIDER }, + { }, + }, }; =20 static void powernv_machine_register_types(void) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index df98a72006e4..6a0b004cea93 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -22,6 +22,7 @@ #include "hw/boards.h" #include "hw/sysbus.h" #include "hw/ppc/pnv_lpc.h" +#include "hw/ppc/xics.h" =20 #define TYPE_PNV_CHIP "powernv-chip" #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP) @@ -114,6 +115,9 @@ typedef struct PnvMachineState { PnvChip **chips; =20 ISABus *isa_bus; + ICPState *icps; + uint32_t nr_servers; + QLIST_HEAD(, ICSState) ics; } PnvMachineState; =20 #define PNV_FDT_ADDR 0x01000000 diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h index 00b003b2392d..c2032cac55f6 100644 --- a/include/hw/ppc/xics.h +++ b/include/hw/ppc/xics.h @@ -115,6 +115,7 @@ struct ICSState { qemu_irq *qirqs; ICSIRQState *irqs; XICSFabric *xics; + QLIST_ENTRY(ICSState) list; }; =20 static inline bool ics_valid_irq(ICSState *ics, uint32_t nr) --=20 2.7.4 From nobody Sun Apr 28 23:40:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1488970589020433.1562207274943; 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Wed, 8 Mar 2017 11:53:09 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 8 Mar 2017 11:52:47 +0100 Message-Id: <1488970371-8865-5-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1488970371-8865-1-git-send-email-clg@kaod.org> References: <1488970371-8865-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 16328081924295199718 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelhedrgeeggddujecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.72.238 Subject: [Qemu-devel] [PATCH for-2.10 4/8] ppc/pnv: add memory regions for the ICP registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This provides to a PowerNV chip (POWER8) access to the Interrupt Management area, which contains the registers of the Interrupt Control Presenters of each thread. These are used to accept, return, forward interrupts in the system. This area is modeled with a per-chip container memory region holding all the ICP registers. Each thread of a chip is then associated with its ICP registers using a memory subregion indexed by its PIR number in the overall region. Signed-off-by: C=C3=A9dric Le Goater --- hw/ppc/pnv.c | 20 +++++++ hw/ppc/pnv_core.c | 146 ++++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/ppc/pnv.h | 20 +++++++ include/hw/ppc/pnv_core.h | 1 + include/hw/ppc/xics.h | 3 + 5 files changed, 190 insertions(+) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 461d3535e99c..7b13b08deadf 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -658,6 +658,16 @@ static void pnv_chip_init(Object *obj) object_property_add_child(obj, "lpc", OBJECT(&chip->lpc), NULL); } =20 +static void pnv_chip_icp_realize(PnvChip *chip, Error **errp) +{ + char *name; + + name =3D g_strdup_printf("icp-%x", chip->chip_id); + memory_region_init(&chip->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip->icp_mmio); + g_free(name); +} + static void pnv_chip_realize(DeviceState *dev, Error **errp) { PnvChip *chip =3D PNV_CHIP(dev); @@ -680,6 +690,14 @@ static void pnv_chip_realize(DeviceState *dev, Error *= *errp) } sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); =20 + /* Interrupt Management Area. This is the memory region holding + * all the Interrupt Control Presenter (ICP) registers */ + pnv_chip_icp_realize(chip, &error); + if (error) { + error_propagate(errp, error); + return; + } + /* Cores */ pnv_chip_core_sanitize(chip, &error); if (error) { @@ -709,6 +727,8 @@ static void pnv_chip_realize(DeviceState *dev, Error **= errp) object_property_set_int(OBJECT(pnv_core), pcc->core_pir(chip, core_hwid), "pir", &error_fatal); + object_property_add_const_link(OBJECT(pnv_core), "xics", + qdev_get_machine(), &error_fatal); object_property_set_bool(OBJECT(pnv_core), true, "realized", &error_fatal); object_unref(OBJECT(pnv_core)); diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index d79d530b4881..8633afbff795 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -26,6 +26,128 @@ #include "hw/ppc/pnv_core.h" #include "hw/ppc/pnv_xscom.h" =20 +static uint64_t pnv_core_icp_read(void *opaque, hwaddr addr, unsigned widt= h) +{ + ICPState *icp =3D opaque; + bool byte0 =3D (width =3D=3D 1 && (addr & 0x3) =3D=3D 0); + uint64_t val =3D 0xffffffff; + + switch (addr & 0xffc) { + case 0: /* poll */ + val =3D icp_ipoll(icp, NULL); + if (byte0) { + val >>=3D 24; + } else if (width !=3D 4) { + goto bad_access; + } + break; + case 4: /* xirr */ + if (byte0) { + val =3D icp_ipoll(icp, NULL) >> 24; + } else if (width =3D=3D 4) { + val =3D icp_accept(icp); + } else { + goto bad_access; + } + break; + case 12: + if (byte0) { + val =3D icp->mfrr; + } else { + goto bad_access; + } + break; + case 16: + if (width =3D=3D 4) { + val =3D icp->links[0]; + } else { + goto bad_access; + } + break; + case 20: + if (width =3D=3D 4) { + val =3D icp->links[1]; + } else { + goto bad_access; + } + break; + case 24: + if (width =3D=3D 4) { + val =3D icp->links[2]; + } else { + goto bad_access; + } + break; + default: +bad_access: + qemu_log_mask(LOG_GUEST_ERROR, "XICS: Bad ICP access 0x%" + HWADDR_PRIx"/%d\n", addr, width); + } + + return val; +} + +static void pnv_core_icp_write(void *opaque, hwaddr addr, uint64_t val, + unsigned width) +{ + ICPState *icp =3D opaque; + bool byte0 =3D (width =3D=3D 1 && (addr & 0x3) =3D=3D 0); + + switch (addr & 0xffc) { + case 4: /* xirr */ + if (byte0) { + icp_set_cppr(icp, val); + } else if (width =3D=3D 4) { + icp_eoi(icp, val); + } else { + goto bad_access; + } + break; + case 12: + if (byte0) { + icp_set_mfrr(icp, val); + } else { + goto bad_access; + } + break; + case 16: + if (width =3D=3D 4) { + icp->links[0] =3D val; + } else { + goto bad_access; + } + break; + case 20: + if (width =3D=3D 4) { + icp->links[1] =3D val; + } else { + goto bad_access; + } + break; + case 24: + if (width =3D=3D 4) { + icp->links[2] =3D val; + } else { + goto bad_access; + } + break; + default: +bad_access: + qemu_log_mask(LOG_GUEST_ERROR, "XICS: Bad ICP access 0x%" + HWADDR_PRIx"/%d\n", addr, width); + } +} + +static const MemoryRegionOps pnv_core_icp_ops =3D { + .read =3D pnv_core_icp_read, + .write =3D pnv_core_icp_write, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 4, + .impl.min_access_size =3D 1, + .impl.max_access_size =3D 4, + .endianness =3D DEVICE_BIG_ENDIAN, +}; + static void powernv_cpu_reset(void *opaque) { PowerPCCPU *cpu =3D opaque; @@ -129,6 +251,14 @@ static void pnv_core_realize_child(Object *child, Erro= r **errp) } } =20 +static ICPState *xics_get_icp_per_pir(XICSFabric *xi, int pir) +{ + int index =3D xics_get_cpu_index_by_pir(pir); + assert(index !=3D -1); + + return xics_icp_get(xi, index); +} + static void pnv_core_realize(DeviceState *dev, Error **errp) { PnvCore *pc =3D PNV_CORE(OBJECT(dev)); @@ -140,6 +270,14 @@ static void pnv_core_realize(DeviceState *dev, Error *= *errp) void *obj; int i, j; char name[32]; + Object *xi; + + xi =3D object_property_get_link(OBJECT(dev), "xics", &local_err); + if (!xi) { + error_setg(errp, "%s: required link 'xics' not found: %s", + __func__, error_get_pretty(local_err)); + return; + } =20 pc->threads =3D g_malloc0(size * cc->nr_threads); for (i =3D 0; i < cc->nr_threads; i++) { @@ -169,6 +307,14 @@ static void pnv_core_realize(DeviceState *dev, Error *= *errp) snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id); pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), &pnv_core_xscom_op= s, pc, name, PNV_XSCOM_EX_CORE_SIZE); + + pc->icp_mmios =3D g_new0(MemoryRegion, cc->nr_threads); + for (i =3D 0; i < cc->nr_threads; i++) { + ICPState *icp =3D xics_get_icp_per_pir(XICS_FABRIC(xi), pc->pir + = i); + snprintf(name, sizeof(name), "icp-core.%d", cc->core_id); + memory_region_init_io(&pc->icp_mmios[i], OBJECT(dev), + &pnv_core_icp_ops, icp, name, 0x1000); + } return; =20 err: diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 6a0b004cea93..f11215ea31f2 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -55,6 +55,7 @@ typedef struct PnvChip { MemoryRegion xscom_mmio; MemoryRegion xscom; AddressSpace xscom_as; + MemoryRegion icp_mmio; =20 PnvLpcController lpc; } PnvChip; @@ -130,4 +131,23 @@ typedef struct PnvMachineState { #define PNV_XSCOM_BASE(chip) \ (chip->xscom_base + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE) =20 +/* + * XSCOM 0x20109CA defines the ICP BAR: + * + * 0:29 : bits 14 to 43 of address to define 1 MB region. + * 30 : 1 to enable ICP to receive loads/stores against its BAR region + * 31:63 : Constant 0 + * + * Usually defined as : + * + * 0xffffe00200000000 -> 0x0003ffff80000000 + * 0xffffe00600000000 -> 0x0003ffff80100000 + * 0xffffe02200000000 -> 0x0003ffff80800000 + * 0xffffe02600000000 -> 0x0003ffff80900000 + * + * TODO: make a macro using the chip hw id + */ +#define PNV_ICP_BASE(chip) 0x0003ffff80000000ull +#define PNV_ICP_SIZE 0x0000000000100000ull + #endif /* _PPC_PNV_H */ diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h index 2955a41c901f..f2fad8f6361b 100644 --- a/include/hw/ppc/pnv_core.h +++ b/include/hw/ppc/pnv_core.h @@ -38,6 +38,7 @@ typedef struct PnvCore { uint32_t pir; =20 MemoryRegion xscom_regs; + MemoryRegion *icp_mmios; } PnvCore; =20 typedef struct PnvCoreClass { diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h index c2032cac55f6..a3dcdf93bbe3 100644 --- a/include/hw/ppc/xics.h +++ b/include/hw/ppc/xics.h @@ -78,6 +78,9 @@ struct ICPState { bool cap_irq_xics_enabled; =20 XICSFabric *xics; + + /* for the PowerNV ICP registers (not used by Linux). */ + uint32_t links[3]; }; =20 #define TYPE_ICS_BASE "ics-base" --=20 2.7.4 From nobody Sun Apr 28 23:40:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1488970678540842.2714914222566; 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Wed, 8 Mar 2017 11:53:13 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 8 Mar 2017 11:52:48 +0100 Message-Id: <1488970371-8865-6-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1488970371-8865-1-git-send-email-clg@kaod.org> References: <1488970371-8865-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 16329489300891339750 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelhedrgeeggddujecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.61.98 Subject: [Qemu-devel] [PATCH for-2.10 5/8] ppc/pnv: map the ICP memory regions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" and populate the device tree accordingly for the guest to start using interrupts. This also links the ICP object to its associated CPUState (only used by KVM to control the kernel vCPU). Signed-off-by: C=C3=A9dric Le Goater --- hw/ppc/pnv.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++= ++++ hw/ppc/pnv_core.c | 12 ++++++++---- 2 files changed, 63 insertions(+), 4 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 7b13b08deadf..0ae11cc3a2ca 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -35,6 +35,7 @@ #include "monitor/monitor.h" #include "hw/intc/intc.h" =20 +#include "hw/ppc/xics.h" #include "hw/ppc/pnv_xscom.h" =20 #include "hw/isa/isa.h" @@ -216,6 +217,47 @@ static void powernv_create_core_node(PnvChip *chip, Pn= vCore *pc, void *fdt) servers_prop, sizeof(servers_prop)))); } =20 +static void powernv_populate_icp(PnvChip *chip, void *fdt, int offset, + uint32_t pir, uint32_t count) +{ + uint64_t addr; + char *name; + const char compat[] =3D "IBM,power8-icp\0IBM,ppc-xicp"; + uint32_t irange[2], i, rsize; + uint64_t *reg; + + /* + * TODO: add multichip ICP BAR + */ + addr =3D PNV_ICP_BASE(chip) | (pir << 12); + + irange[0] =3D cpu_to_be32(pir); + irange[1] =3D cpu_to_be32(count); + + rsize =3D sizeof(uint64_t) * 2 * count; + reg =3D g_malloc(rsize); + for (i =3D 0; i < count; i++) { + reg[i * 2] =3D cpu_to_be64(addr | ((pir + i) * 0x1000)); + reg[i * 2 + 1] =3D cpu_to_be64(0x1000); + } + + name =3D g_strdup_printf("interrupt-controller@%"PRIX64, addr); + offset =3D fdt_add_subnode(fdt, offset, name); + _FDT(offset); + g_free(name); + + _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); + _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); + _FDT((fdt_setprop_string(fdt, offset, "device_type", + "PowerPC-External-Interrupt-Presentation"))); + _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); + _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", + irange, sizeof(irange)))); + _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); + _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); + g_free(reg); +} + static void powernv_populate_chip(PnvChip *chip, void *fdt) { PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); @@ -229,6 +271,10 @@ static void powernv_populate_chip(PnvChip *chip, void = *fdt) PnvCore *pnv_core =3D PNV_CORE(chip->cores + i * typesize); =20 powernv_create_core_node(chip, pnv_core, fdt); + + /* Interrupt Control Presenters (ICP). One per thread. */ + powernv_populate_icp(chip, fdt, 0, pnv_core->pir, + CPU_CORE(pnv_core)->nr_threads); } =20 if (chip->ram_size) { @@ -697,6 +743,7 @@ static void pnv_chip_realize(DeviceState *dev, Error **= errp) error_propagate(errp, error); return; } + sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); =20 /* Cores */ pnv_chip_core_sanitize(chip, &error); @@ -711,6 +758,7 @@ static void pnv_chip_realize(DeviceState *dev, Error **= errp) && (i < chip->nr_cores); core_hwid++) { char core_name[32]; void *pnv_core =3D chip->cores + i * typesize; + int j; =20 if (!(chip->cores_mask & (1ull << core_hwid))) { continue; @@ -738,6 +786,13 @@ static void pnv_chip_realize(DeviceState *dev, Error *= *errp) PNV_XSCOM_EX_CORE_BASE(pcc->xscom_core_bas= e, core_hwid), &PNV_CORE(pnv_core)->xscom_regs); + + /* Map the ICP registers for each thread */ + for (j =3D 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { + memory_region_add_subregion(&chip->icp_mmio, + (pcc->core_pir(chip, core_hwid) + j) << 1= 2, + &PNV_CORE(pnv_core)->icp_mmios[j]); + } i++; } g_free(typename); diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 8633afbff795..d28fa445b11b 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -25,6 +25,7 @@ #include "hw/ppc/pnv.h" #include "hw/ppc/pnv_core.h" #include "hw/ppc/pnv_xscom.h" +#include "hw/ppc/xics.h" =20 static uint64_t pnv_core_icp_read(void *opaque, hwaddr addr, unsigned widt= h) { @@ -165,7 +166,7 @@ static void powernv_cpu_reset(void *opaque) env->msr |=3D MSR_HVB; /* Hypervisor mode */ } =20 -static void powernv_cpu_init(PowerPCCPU *cpu, Error **errp) +static void powernv_cpu_init(PowerPCCPU *cpu, XICSFabric *xi, Error **errp) { CPUPPCState *env =3D &cpu->env; int core_pir; @@ -185,6 +186,9 @@ static void powernv_cpu_init(PowerPCCPU *cpu, Error **e= rrp) cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ); =20 qemu_register_reset(powernv_cpu_reset, cpu); + + /* xics_cpu_setup() assigns the CPU to the ICPState */ + xics_cpu_setup(xi, cpu); } =20 /* @@ -232,7 +236,7 @@ static const MemoryRegionOps pnv_core_xscom_ops =3D { .endianness =3D DEVICE_BIG_ENDIAN, }; =20 -static void pnv_core_realize_child(Object *child, Error **errp) +static void pnv_core_realize_child(Object *child, XICSFabric *xi, Error **= errp) { Error *local_err =3D NULL; CPUState *cs =3D CPU(child); @@ -244,7 +248,7 @@ static void pnv_core_realize_child(Object *child, Error= **errp) return; } =20 - powernv_cpu_init(cpu, &local_err); + powernv_cpu_init(cpu, xi, &local_err); if (local_err) { error_propagate(errp, local_err); return; @@ -298,7 +302,7 @@ static void pnv_core_realize(DeviceState *dev, Error **= errp) for (j =3D 0; j < cc->nr_threads; j++) { obj =3D pc->threads + j * size; =20 - pnv_core_realize_child(obj, &local_err); + pnv_core_realize_child(obj, XICS_FABRIC(xi), &local_err); if (local_err) { goto err; } --=20 2.7.4 From nobody Sun Apr 28 23:40:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Wed, 08 Mar 2017 05:53:25 -0500 Received: from player714.ha.ovh.net (b7.ovh.net [213.186.33.57]) by mo177.mail-out.ovh.net (Postfix) with ESMTP id 89E0C33BF2 for ; Wed, 8 Mar 2017 11:53:23 +0100 (CET) Received: from zorba.kaod.org.com (LFbn-1-10647-27.w90-89.abo.wanadoo.fr [90.89.233.27]) (Authenticated sender: clg@kaod.org) by player714.ha.ovh.net (Postfix) with ESMTPSA id 149EF3C007E; Wed, 8 Mar 2017 11:53:18 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 8 Mar 2017 11:52:49 +0100 Message-Id: <1488970371-8865-7-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1488970371-8865-1-git-send-email-clg@kaod.org> References: <1488970371-8865-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 16330896674694138854 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelhedrgeeggddujecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.36.172 Subject: [Qemu-devel] [PATCH for-2.10 6/8] ppc/pnv: Add cut down PSI bridge model and hookup external interrupt X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Benjamin Herrenschmidt The PSI (Processor Service Interface) Controller is one of the engines of the "Bridge" unit which connects the different interfaces to the Power Processor. This adds just enough of the PSI bridge to handle various on-chip and the one external interrupt. The rest of PSI has to do with the link to the IBM FSP service processor which we don't plan to emulate (not used on OpenPower machines). Signed-off-by: Benjamin Herrenschmidt [clg: - updated for qemu-2.9 - changed the XSCOM interface to fit new model - QOMified the model - reworked set_xive and worked around a skiboot bug - removed the 'psi_mmio_to_xscom' mapping array ] Signed-off-by: C=C3=A9dric Le Goater --- hw/ppc/Makefile.objs | 2 +- hw/ppc/pnv.c | 35 ++- hw/ppc/pnv_psi.c | 583 +++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/ppc/pnv.h | 8 + include/hw/ppc/pnv_psi.h | 61 +++++ include/hw/ppc/pnv_xscom.h | 3 + 6 files changed, 685 insertions(+), 7 deletions(-) create mode 100644 hw/ppc/pnv_psi.c create mode 100644 include/hw/ppc/pnv_psi.h diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs index 001293423c8d..dc19ee17fa57 100644 --- a/hw/ppc/Makefile.objs +++ b/hw/ppc/Makefile.objs @@ -6,7 +6,7 @@ obj-$(CONFIG_PSERIES) +=3D spapr_hcall.o spapr_iommu.o spap= r_rtas.o obj-$(CONFIG_PSERIES) +=3D spapr_pci.o spapr_rtc.o spapr_drc.o spapr_rng.o obj-$(CONFIG_PSERIES) +=3D spapr_cpu_core.o spapr_ovec.o # IBM PowerNV -obj-$(CONFIG_POWERNV) +=3D pnv.o pnv_xscom.o pnv_core.o pnv_lpc.o +obj-$(CONFIG_POWERNV) +=3D pnv.o pnv_xscom.o pnv_core.o pnv_lpc.o pnv_psi.o ifeq ($(CONFIG_PCI)$(CONFIG_PSERIES)$(CONFIG_LINUX), yyy) obj-y +=3D spapr_pci_vfio.o endif diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 0ae11cc3a2ca..85b00bf235c6 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -356,15 +356,22 @@ static void ppc_powernv_reset(void) * have a CPLD that will collect the SerIRQ and shoot them as a * single level interrupt to the P8 chip. So let's setup a hook * for doing just that. - * - * Note: The actual interrupt input isn't emulated yet, this will - * come with the PSI bridge model. */ static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level) { - /* We don't yet emulate the PSI bridge which provides the external - * interrupt, so just drop interrupts on the floor - */ + PnvMachineState *pnv =3D POWERNV_MACHINE(qdev_get_machine()); + uint32_t old_state =3D pnv->cpld_irqstate; + PnvChip *chip =3D opaque; + + if (level) { + pnv->cpld_irqstate |=3D 1u << n; + } else { + pnv->cpld_irqstate &=3D ~(1u << n); + } + if (pnv->cpld_irqstate !=3D old_state) { + pnv_psi_irq_set(&chip->psi, PSIHB_IRQ_EXTERNAL, + pnv->cpld_irqstate !=3D 0); + } } =20 static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level) @@ -702,6 +709,11 @@ static void pnv_chip_init(Object *obj) =20 object_initialize(&chip->lpc, sizeof(chip->lpc), TYPE_PNV_LPC); object_property_add_child(obj, "lpc", OBJECT(&chip->lpc), NULL); + + object_initialize(&chip->psi, sizeof(chip->psi), TYPE_PNV_PSI); + object_property_add_child(obj, "psi", OBJECT(&chip->psi), NULL); + object_property_add_const_link(OBJECT(&chip->psi), "xics", + OBJECT(qdev_get_machine()), &error_abor= t); } =20 static void pnv_chip_icp_realize(PnvChip *chip, Error **errp) @@ -722,6 +734,8 @@ static void pnv_chip_realize(DeviceState *dev, Error **= errp) char *typename =3D pnv_core_typename(pcc->cpu_model); size_t typesize =3D object_type_get_instance_size(typename); int i, core_hwid; + MachineState *machine =3D MACHINE(qdev_get_machine()); + PnvMachineState *pnv =3D POWERNV_MACHINE(machine); =20 if (!object_class_by_name(typename)) { error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); @@ -797,6 +811,15 @@ static void pnv_chip_realize(DeviceState *dev, Error *= *errp) } g_free(typename); =20 + + /* Processor Service Interface (PSI) Host Bridge */ + object_property_set_bool(OBJECT(&chip->psi), true, "realized", + &error_fatal); + pnv_xscom_add_subregion(chip, PNV_XSCOM_PSI_BASE, &chip->psi.xscom_reg= s); + + /* link in the PSI ICS */ + QLIST_INSERT_HEAD(&pnv->ics, &chip->psi.ics, list); + /* Create LPC controller */ object_property_set_bool(OBJECT(&chip->lpc), true, "realized", &error_fatal); diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c new file mode 100644 index 000000000000..6ba688aac075 --- /dev/null +++ b/hw/ppc/pnv_psi.c @@ -0,0 +1,583 @@ +/* + * QEMU PowerNV PowerPC PSI interface + * + * Copyright (c) 2016, IBM Corporation + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "hw/hw.h" +#include "target/ppc/cpu.h" +#include "qemu/log.h" +#include "qapi/error.h" + +#include "exec/address-spaces.h" + +#include "hw/ppc/fdt.h" +#include "hw/ppc/pnv.h" +#include "hw/ppc/pnv_xscom.h" +#include "hw/ppc/pnv_psi.h" + +#include + +#define PSIHB_XSCOM_FIR_RW 0x00 +#define PSIHB_XSCOM_FIR_AND 0x01 +#define PSIHB_XSCOM_FIR_OR 0x02 +#define PSIHB_XSCOM_FIRMASK_RW 0x03 +#define PSIHB_XSCOM_FIRMASK_AND 0x04 +#define PSIHB_XSCOM_FIRMASK_OR 0x05 +#define PSIHB_XSCOM_FIRACT0 0x06 +#define PSIHB_XSCOM_FIRACT1 0x07 +#define PSIHB_XSCOM_BAR 0x0a +#define PSIHB_BAR_EN 0x0000000000000001ull +#define PSIHB_XSCOM_FSPBAR 0x0b +#define PSIHB_XSCOM_CR 0x0e +#define PSIHB_CR_FSP_CMD_ENABLE 0x8000000000000000ull +#define PSIHB_CR_FSP_MMIO_ENABLE 0x4000000000000000ull +#define PSIHB_CR_FSP_IRQ_ENABLE 0x1000000000000000ull +#define PSIHB_CR_FSP_ERR_RSP_ENABLE 0x0800000000000000ull +#define PSIHB_CR_PSI_LINK_ENABLE 0x0400000000000000ull +#define PSIHB_CR_FSP_RESET 0x0200000000000000ull +#define PSIHB_CR_PSIHB_RESET 0x0100000000000000ull +#define PSIHB_CR_PSI_IRQ 0x0000800000000000ull +#define PSIHB_CR_FSP_IRQ 0x0000400000000000ull +#define PSIHB_CR_FSP_LINK_ACTIVE 0x0000200000000000ull + /* and more ... */ +#define PSIHB_XSCOM_SEMR 0x0f +#define PSIHB_XSCOM_XIVR_PSI 0x10 +#define PSIHB_XIVR_SERVER_SH 40 +#define PSIHB_XIVR_SERVER_MSK (0xffffull << PSIHB_XIVR_SERVER_SH) +#define PSIHB_XIVR_PRIO_SH 32 +#define PSIHB_XIVR_PRIO_MSK (0xffull << PSIHB_XIVR_PRIO_SH) +#define PSIHB_XIVR_SRC_SH 29 +#define PSIHB_XIVR_SRC_MSK (0x7ull << PSIHB_XIVR_SRC_SH) +#define PSIHB_XIVR_PENDING 0x01000000ull +#define PSIHB_XSCOM_SCR 0x12 +#define PSIHB_XSCOM_CCR 0x13 +#define PSIHB_XSCOM_DMA_UPADD 0x14 +#define PSIHB_XSCOM_IRQ_STAT 0x15 +#define PSIHB_IRQ_STAT_OCC 0x0000001000000000ull +#define PSIHB_IRQ_STAT_FSI 0x0000000800000000ull +#define PSIHB_IRQ_STAT_LPCI2C 0x0000000400000000ull +#define PSIHB_IRQ_STAT_LOCERR 0x0000000200000000ull +#define PSIHB_IRQ_STAT_EXT 0x0000000100000000ull +#define PSIHB_XSCOM_XIVR_OCC 0x16 +#define PSIHB_XSCOM_XIVR_FSI 0x17 +#define PSIHB_XSCOM_XIVR_LPCI2C 0x18 +#define PSIHB_XSCOM_XIVR_LOCERR 0x19 +#define PSIHB_XSCOM_XIVR_EXT 0x1a +#define PSIHB_XSCOM_IRSN 0x1b +#define PSIHB_IRSN_COMP_SH 45 +#define PSIHB_IRSN_COMP_MSK (0x7ffffull << PSIHB_IRSN_COMP_SH) +#define PSIHB_IRSN_IRQ_MUX 0x0000000800000000ull +#define PSIHB_IRSN_IRQ_RESET 0x0000000400000000ull +#define PSIHB_IRSN_DOWNSTREAM_EN 0x0000000200000000ull +#define PSIHB_IRSN_UPSTREAM_EN 0x0000000100000000ull +#define PSIHB_IRSN_COMPMASK_SH 13 +#define PSIHB_IRSN_COMPMASK_MSK (0x7ffffull << PSIHB_IRSN_COMPMASK= _SH) + +/* + * These are the values of the registers when accessed through the + * MMIO region. The relation is xscom =3D (mmio + 0x50) >> 3 + */ +#define PSIHB_MMIO_BAR 0x00 +#define PSIHB_MMIO_FSPBAR 0x08 +#define PSIHB_MMIO_CR 0x20 +#define PSIHB_MMIO_SEMR 0x28 +#define PSIHB_MMIO_XIVR_PSI 0x30 +#define PSIHB_MMIO_SCR 0x40 +#define PSIHB_MMIO_CCR 0x48 +#define PSIHB_MMIO_DMA_UPADD 0x50 +#define PSIHB_MMIO_IRQ_STAT 0x58 +#define PSIHB_MMIO_XIVR_OCC 0x60 +#define PSIHB_MMIO_XIVR_FSI 0x68 +#define PSIHB_MMIO_XIVR_LPCI2C 0x70 +#define PSIHB_MMIO_XIVR_LOCERR 0x78 +#define PSIHB_MMIO_XIVR_EXT 0x80 +#define PSIHB_MMIO_IRSN 0x88 +#define PSIHB_MMIO_MAX 0x100 + +static void pnv_psi_set_bar(PnvPsi *psi, uint64_t bar) +{ + MemoryRegion *sysmem =3D get_system_memory(); + uint64_t old =3D psi->regs[PSIHB_XSCOM_BAR]; + + psi->regs[PSIHB_XSCOM_BAR] =3D bar & 0x0003fffffff00001; + + /* Update MR, always remove it first */ + if (old & PSIHB_BAR_EN) { + memory_region_del_subregion(sysmem, &psi->regs_mr); + } + /* Then add it back if needed */ + if (bar & PSIHB_BAR_EN) { + uint64_t addr =3D bar & 0x0003fffffff00000; + memory_region_add_subregion(sysmem, addr, &psi->regs_mr); + } +} + +static void pnv_psi_update_fsp_mr(PnvPsi *psi) +{ + /* XXX Update FSP MR if/when we support FSP BAR */ +} + +static void pnv_psi_set_cr(PnvPsi *psi, uint64_t cr) +{ + uint64_t old =3D psi->regs[PSIHB_XSCOM_CR]; + + psi->regs[PSIHB_XSCOM_CR] =3D cr & 0x0003ffff00000000; + + /* Check some bit changes */ + if ((old ^ psi->regs[PSIHB_XSCOM_CR]) & PSIHB_CR_FSP_MMIO_ENABLE) { + pnv_psi_update_fsp_mr(psi); + } +} + +static void pnv_psi_set_irsn(PnvPsi *psi, uint64_t val) +{ + uint32_t offset; + ICSState *ics =3D &psi->ics; + + /* In this model we ignore the up/down enable bits for now + * as SW doesn't use them (other than setting them at boot). + * We ignore IRQ_MUX, its meaning isn't clear and we don't use + * it and finally we ignore reset (XXX fix that ?) + */ + psi->regs[PSIHB_XSCOM_IRSN] =3D val & (PSIHB_IRSN_COMP_MSK | + PSIHB_IRSN_IRQ_MUX | + PSIHB_IRSN_DOWNSTREAM_EN | + PSIHB_IRSN_DOWNSTREAM_EN | + PSIHB_IRSN_DOWNSTREAM_EN); + + /* We ignore the compare mask as well, our ICS emulation is too + * simplistic to make any use if it, and we extract the offset + * from the compare value + */ + offset =3D (val & PSIHB_IRSN_COMP_MSK) >> PSIHB_IRSN_COMP_SH; + ics->offset =3D offset; +} + +static bool pnv_psi_irq_bits(PnvPsi *psi, PnvPsiIrq irq, + uint32_t *out_xivr_reg, + uint32_t *out_stat_reg, + uint64_t *out_stat_bit) +{ + switch (irq) { + case PSIHB_IRQ_PSI: + *out_xivr_reg =3D PSIHB_XSCOM_XIVR_PSI; + *out_stat_reg =3D PSIHB_XSCOM_CR; + *out_stat_bit =3D PSIHB_CR_PSI_IRQ; + break; + case PSIHB_IRQ_FSP: + *out_xivr_reg =3D PSIHB_XSCOM_XIVR_PSI; + *out_stat_reg =3D PSIHB_XSCOM_CR; + *out_stat_bit =3D PSIHB_CR_FSP_IRQ; + break; + case PSIHB_IRQ_OCC: + *out_xivr_reg =3D PSIHB_XSCOM_XIVR_OCC; + *out_stat_reg =3D PSIHB_XSCOM_IRQ_STAT; + *out_stat_bit =3D PSIHB_IRQ_STAT_OCC; + break; + case PSIHB_IRQ_FSI: + *out_xivr_reg =3D PSIHB_XSCOM_XIVR_FSI; + *out_stat_reg =3D PSIHB_XSCOM_IRQ_STAT; + *out_stat_bit =3D PSIHB_IRQ_STAT_FSI; + break; + case PSIHB_IRQ_LPC_I2C: + *out_xivr_reg =3D PSIHB_XSCOM_XIVR_LPCI2C; + *out_stat_reg =3D PSIHB_XSCOM_IRQ_STAT; + *out_stat_bit =3D PSIHB_IRQ_STAT_LPCI2C; + break; + case PSIHB_IRQ_LOCAL_ERR: + *out_xivr_reg =3D PSIHB_XSCOM_XIVR_LOCERR; + *out_stat_reg =3D PSIHB_XSCOM_IRQ_STAT; + *out_stat_bit =3D PSIHB_IRQ_STAT_LOCERR; + break; + case PSIHB_IRQ_EXTERNAL: + *out_xivr_reg =3D PSIHB_XSCOM_XIVR_EXT; + *out_stat_reg =3D PSIHB_XSCOM_IRQ_STAT; + *out_stat_bit =3D PSIHB_IRQ_STAT_EXT; + break; + default: + return false; + } + return true; +} + +void pnv_psi_irq_set(PnvPsi *psi, PnvPsiIrq irq, bool state) +{ + ICSState *ics =3D &psi->ics; + uint32_t xivr_reg; + uint32_t stat_reg; + uint64_t stat_bit; + uint32_t src; + bool masked; + + if (!pnv_psi_irq_bits(psi, irq, &xivr_reg, &stat_reg, &stat_bit)) { + qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", irq); + return; + } + + src =3D (psi->regs[xivr_reg] & PSIHB_XIVR_SRC_MSK) >> PSIHB_XIVR_SRC_S= H; + masked =3D (psi->regs[xivr_reg] & PSIHB_XIVR_PRIO_MSK) =3D=3D PSIHB_XI= VR_PRIO_MSK; + if (state) { + psi->regs[stat_reg] |=3D stat_bit; + /* XXX optimization: check mask here. That means re-evaluating + * when unmasking, thus TODO + */ + qemu_irq_raise(ics->qirqs[src]); + } else { + psi->regs[stat_reg] &=3D ~stat_bit; + + /* FSP and PSI are muxed so don't lower if either still set */ + if (stat_reg !=3D PSIHB_XSCOM_CR || + !(psi->regs[stat_reg] & (PSIHB_CR_PSI_IRQ | PSIHB_CR_FSP_IRQ))= ) { + qemu_irq_lower(ics->qirqs[src]); + } else { + state =3D true; + } + } + + /* XXX Note about the emulation of the pending bit: This isn't + * entirely correct. The pending bit should be cleared when the + * EOI has been received. However, we don't have callbacks on + * EOI (especially not under KVM) so no way to emulate that + * properly, so instead we just set that bit as the logical + * "output" of the XIVR (ie pending & !masked) + * XXX TODO: Also update it on set_xivr + */ + if (state && !masked) { + psi->regs[xivr_reg] |=3D PSIHB_XIVR_PENDING; + } else { + psi->regs[xivr_reg] &=3D ~PSIHB_XIVR_PENDING; + } +} + +static void pnv_psi_set_xivr(PnvPsi *psi, uint32_t reg, uint64_t val) +{ + ICSState *ics =3D &psi->ics; + uint16_t server; + uint8_t prio; + uint8_t src; + int icp_index; + + psi->regs[reg] =3D (psi->regs[reg] & PSIHB_XIVR_PENDING) | + (val & (PSIHB_XIVR_SERVER_MSK | + PSIHB_XIVR_PRIO_MSK | + PSIHB_XIVR_SRC_MSK)); + val =3D psi->regs[reg]; + server =3D (val & PSIHB_XIVR_SERVER_MSK) >> PSIHB_XIVR_SERVER_SH; + prio =3D (val & PSIHB_XIVR_PRIO_MSK) >> PSIHB_XIVR_PRIO_SH; + src =3D (val & PSIHB_XIVR_SRC_MSK) >> PSIHB_XIVR_SRC_SH; + if (src > PSIHB_IRQ_EXTERNAL) { + /* XXX Generate error ? */ + return; + } + + /* + * Linux fills the irq xivr with the hw processor id plus the + * link bits. shift back to get something valid. + */ + server >>=3D 2; + + /* + * When skiboot initializes PSIHB, it fills the xives with + * server=3D0, prio=3D0xff, but we don't have a CPU with a pir=3D0. So + * skip that case. + */ + if (prio !=3D 0xff) { + icp_index =3D xics_get_cpu_index_by_pir(server); + assert(icp_index !=3D -1); + } else { + if (server) { + qemu_log_mask(LOG_GUEST_ERROR, "PSI: bogus server %d for IRQ %= d\n", + server, src); + } + icp_index =3D server; + } + + /* Now because of source remapping, weird things can happen + * if you change the source number dynamically, our simple ICS + * doesn't deal with remapping. So we just poke a different + * ICS entry based on what source number was written. This will + * do for now but a more accurate implementation would instead + * use a fixed server/prio and a remapper of the generated irq. + */ + ics_simple_write_xive(ics, src, icp_index, prio, prio); +} + +static uint64_t pnv_psi_reg_read(PnvPsi *psi, uint32_t offset, bool mmio) +{ + uint64_t val =3D 0xffffffffffffffffull; + + switch (offset) { + case PSIHB_XSCOM_FIR_RW: + case PSIHB_XSCOM_FIRACT0: + case PSIHB_XSCOM_FIRACT1: + case PSIHB_XSCOM_BAR: + case PSIHB_XSCOM_FSPBAR: + case PSIHB_XSCOM_CR: + case PSIHB_XSCOM_XIVR_PSI: + case PSIHB_XSCOM_XIVR_OCC: + case PSIHB_XSCOM_XIVR_FSI: + case PSIHB_XSCOM_XIVR_LPCI2C: + case PSIHB_XSCOM_XIVR_LOCERR: + case PSIHB_XSCOM_XIVR_EXT: + case PSIHB_XSCOM_IRQ_STAT: + case PSIHB_XSCOM_SEMR: + case PSIHB_XSCOM_DMA_UPADD: + case PSIHB_XSCOM_IRSN: + val =3D psi->regs[offset]; + break; + default: + qemu_log_mask(LOG_UNIMP, "PSI Unimplemented register: Ox%" PRIx32 = "\n", + offset); + } + return val; +} + +static void pnv_psi_reg_write(PnvPsi *psi, uint32_t offset, uint64_t val, + bool mmio) +{ + switch (offset) { + case PSIHB_XSCOM_FIR_RW: + case PSIHB_XSCOM_FIRACT0: + case PSIHB_XSCOM_FIRACT1: + case PSIHB_XSCOM_SEMR: + case PSIHB_XSCOM_DMA_UPADD: + psi->regs[offset] =3D val; + break; + case PSIHB_XSCOM_FIR_OR: + psi->regs[PSIHB_XSCOM_FIR_RW] |=3D val; + break; + case PSIHB_XSCOM_FIR_AND: + psi->regs[PSIHB_XSCOM_FIR_RW] &=3D val; + break; + case PSIHB_XSCOM_BAR: + /* Only XSCOM can write this one */ + if (!mmio) { + pnv_psi_set_bar(psi, val); + } + break; + case PSIHB_XSCOM_FSPBAR: + psi->regs[PSIHB_XSCOM_BAR] =3D val & 0x0003ffff00000000; + pnv_psi_update_fsp_mr(psi); + break; + case PSIHB_XSCOM_CR: + pnv_psi_set_cr(psi, val); + break; + case PSIHB_XSCOM_SCR: + pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] | val); + break; + case PSIHB_XSCOM_CCR: + pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] & ~val); + break; + case PSIHB_XSCOM_XIVR_PSI: + case PSIHB_XSCOM_XIVR_OCC: + case PSIHB_XSCOM_XIVR_FSI: + case PSIHB_XSCOM_XIVR_LPCI2C: + case PSIHB_XSCOM_XIVR_LOCERR: + case PSIHB_XSCOM_XIVR_EXT: + pnv_psi_set_xivr(psi, offset, val); + break; + case PSIHB_XSCOM_IRQ_STAT: + /* Read only, should we generate an error ? */ + break; + case PSIHB_XSCOM_IRSN: + pnv_psi_set_irsn(psi, val); + break; + default: + qemu_log_mask(LOG_UNIMP, "PSI Unimplemented register: Ox%" PRIx32 = "\n", + offset); + } +} + +static inline uint32_t psi_mmio_to_xscom(hwaddr addr) +{ + return (addr >> 3) + PSIHB_XSCOM_BAR; +} + +static uint64_t pnv_psi_mmio_read(void *opaque, hwaddr addr, unsigned size) +{ + return pnv_psi_reg_read(opaque, psi_mmio_to_xscom(addr), true); +} + +static void pnv_psi_mmio_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + pnv_psi_reg_write(opaque, psi_mmio_to_xscom(addr), val, true); +} + +static const MemoryRegionOps psi_mmio_ops =3D { + .read =3D pnv_psi_mmio_read, + .write =3D pnv_psi_mmio_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .valid =3D { + .min_access_size =3D 8, + .max_access_size =3D 8, + }, + .impl =3D { + .min_access_size =3D 8, + .max_access_size =3D 8, + }, +}; + +static uint64_t pnv_psi_xscom_read(void *opaque, hwaddr addr, unsigned siz= e) +{ + PnvPsi *psi =3D PNV_PSI(opaque); + uint32_t offset =3D addr >> 3; + + return pnv_psi_reg_read(psi, offset, false); +} + +static void pnv_psi_xscom_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + PnvPsi *psi =3D PNV_PSI(opaque); + uint32_t offset =3D addr >> 3; + + pnv_psi_reg_write(psi, offset, val, false); +} + +static const MemoryRegionOps pnv_psi_xscom_ops =3D { + .read =3D pnv_psi_xscom_read, + .write =3D pnv_psi_xscom_write, + .valid.min_access_size =3D 8, + .valid.max_access_size =3D 8, + .impl.min_access_size =3D 8, + .impl.max_access_size =3D 8, + .endianness =3D DEVICE_BIG_ENDIAN, +}; + +static void pnv_psi_init(Object *obj) +{ + PnvPsi *psi =3D PNV_PSI(obj); + + object_initialize(&psi->ics, sizeof(psi->ics), TYPE_ICS_SIMPLE); + qdev_set_parent_bus(DEVICE(&psi->ics), sysbus_get_default()); + object_property_add_child(obj, "ics-psi", OBJECT(&psi->ics), NULL); +} + +static void pnv_psi_realize(DeviceState *dev, Error **errp) +{ + PnvPsi *psi =3D PNV_PSI(dev); + ICSState *ics =3D &psi->ics; + Object *obj; + Error *err =3D NULL, *local_err =3D NULL; + unsigned int i; + + /* Initialize MMIO region */ + memory_region_init_io(&psi->regs_mr, OBJECT(dev), &psi_mmio_ops, psi, + "psihb", PNV_PSIHB_BAR_SIZE); + + /* Default BAR. Use object properties ? */ + pnv_psi_set_bar(psi, PNV_PSIHB_BAR | PSIHB_BAR_EN); + + /* Default sources in XIVR */ + psi->regs[PSIHB_XSCOM_XIVR_PSI] =3D PSIHB_XIVR_PRIO_MSK | + (0ull << PSIHB_XIVR_SRC_SH); + psi->regs[PSIHB_XSCOM_XIVR_OCC] =3D PSIHB_XIVR_PRIO_MSK | + (1ull << PSIHB_XIVR_SRC_SH); + psi->regs[PSIHB_XSCOM_XIVR_FSI] =3D PSIHB_XIVR_PRIO_MSK | + (2ull << PSIHB_XIVR_SRC_SH); + psi->regs[PSIHB_XSCOM_XIVR_LPCI2C] =3D PSIHB_XIVR_PRIO_MSK | + (3ull << PSIHB_XIVR_SRC_SH); + psi->regs[PSIHB_XSCOM_XIVR_LOCERR] =3D PSIHB_XIVR_PRIO_MSK | + (4ull << PSIHB_XIVR_SRC_SH); + psi->regs[PSIHB_XSCOM_XIVR_EXT] =3D PSIHB_XIVR_PRIO_MSK | + (5ull << PSIHB_XIVR_SRC_SH); + + /* get XICSFabric from chip */ + obj =3D object_property_get_link(OBJECT(dev), "xics", &err); + if (!obj) { + error_setg(errp, "%s: required link 'xics' not found: %s", + __func__, error_get_pretty(err)); + return; + } + + /* + * PSI interrupt control source + */ + object_property_set_int(OBJECT(ics), PSI_NUM_INTERRUPTS, "nr-irqs", &e= rr); + object_property_add_const_link(OBJECT(ics), "xics", obj, &err); + object_property_set_bool(OBJECT(ics), true, "realized", &local_err); + error_propagate(&err, local_err); + if (err) { + error_propagate(errp, err); + return; + } + + for (i =3D 0; i < ics->nr_irqs; i++) { + ics_set_irq_type(ics, i, true); + } + + /* XScom region for PSI registers */ + pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_xscom_op= s, + psi, "xscom-psi", PNV_XSCOM_PSI_SIZE); +} + +static int pnv_psi_populate(PnvXScomInterface *dev, void *fdt, int xscom_o= ffset) +{ + const char compat[] =3D "ibm,power8-psihb-x\0ibm,psihb-x"; + char *name; + int offset; + uint32_t lpc_pcba =3D PNV_XSCOM_PSI_BASE; + uint32_t reg[] =3D { + cpu_to_be32(lpc_pcba), + cpu_to_be32(PNV_XSCOM_PSI_SIZE) + }; + + name =3D g_strdup_printf("psihb@%x", lpc_pcba); + offset =3D fdt_add_subnode(fdt, xscom_offset, name); + _FDT(offset); + g_free(name); + + _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)))); + + _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2))); + _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1))); + _FDT((fdt_setprop(fdt, offset, "compatible", compat, + sizeof(compat)))); + return 0; +} + + +static void pnv_psi_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + PnvXScomInterfaceClass *xdc =3D PNV_XSCOM_INTERFACE_CLASS(klass); + + xdc->populate =3D pnv_psi_populate; + + dc->realize =3D pnv_psi_realize; +} + +static const TypeInfo pnv_psi_info =3D { + .name =3D TYPE_PNV_PSI, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(PnvPsi), + .instance_init =3D pnv_psi_init, + .class_init =3D pnv_psi_class_init, + .interfaces =3D (InterfaceInfo[]) { + { TYPE_PNV_XSCOM_INTERFACE }, + { } + } +}; + +static void pnv_psi_register_types(void) +{ + type_register_static(&pnv_psi_info); +} + +type_init(pnv_psi_register_types) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index f11215ea31f2..f93ec32603b7 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -23,6 +23,7 @@ #include "hw/sysbus.h" #include "hw/ppc/pnv_lpc.h" #include "hw/ppc/xics.h" +#include "hw/ppc/pnv_psi.h" =20 #define TYPE_PNV_CHIP "powernv-chip" #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP) @@ -58,6 +59,7 @@ typedef struct PnvChip { MemoryRegion icp_mmio; =20 PnvLpcController lpc; + PnvPsi psi; } PnvChip; =20 typedef struct PnvChipClass { @@ -119,6 +121,8 @@ typedef struct PnvMachineState { ICPState *icps; uint32_t nr_servers; QLIST_HEAD(, ICSState) ics; + + uint32_t cpld_irqstate; } PnvMachineState; =20 #define PNV_FDT_ADDR 0x01000000 @@ -150,4 +154,8 @@ typedef struct PnvMachineState { #define PNV_ICP_BASE(chip) 0x0003ffff80000000ull #define PNV_ICP_SIZE 0x0000000000100000ull =20 +#define PNV_PSIHB_BAR 0x0003fffe80000000ull +#define PNV_PSIHB_BAR_SIZE 0x0000000000100000ull + + #endif /* _PPC_PNV_H */ diff --git a/include/hw/ppc/pnv_psi.h b/include/hw/ppc/pnv_psi.h new file mode 100644 index 000000000000..ac3c5f8362e3 --- /dev/null +++ b/include/hw/ppc/pnv_psi.h @@ -0,0 +1,61 @@ +/* + * QEMU PowerPC PowerNV PSI controller + * + * Copyright (c) 2016, IBM Corporation. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ +#ifndef _PPC_PNV_PSI_H +#define _PPC_PNV_PSI_H + +#define TYPE_PNV_PSI "pnv-psi" +#define PNV_PSI(obj) \ + OBJECT_CHECK(PnvPsi, (obj), TYPE_PNV_PSI) + +#define PSIHB_XSCOM_MAX 0x20 + +typedef struct XICSState XICSState; + +typedef struct PnvPsi { + DeviceState parent; + + MemoryRegion regs_mr; + + /* FSP region not supported */ + /* MemoryRegion fsp_mr; */ + + /* Interrupt generation */ + ICSState ics; + + /* Registers */ + uint64_t regs[PSIHB_XSCOM_MAX]; + + MemoryRegion xscom_regs; +} PnvPsi; + +typedef enum PnvPsiIrq { + PSIHB_IRQ_PSI, /* internal use only */ + PSIHB_IRQ_FSP, /* internal use only */ + PSIHB_IRQ_OCC, + PSIHB_IRQ_FSI, + PSIHB_IRQ_LPC_I2C, + PSIHB_IRQ_LOCAL_ERR, + PSIHB_IRQ_EXTERNAL, +} PnvPsiIrq; + +#define PSI_NUM_INTERRUPTS 6 + +extern void pnv_psi_irq_set(PnvPsi *psi, PnvPsiIrq irq, bool state); + +#endif /* _PPC_PNV_PSI_H */ diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index 0faa1847bf13..2938abd74955 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -60,6 +60,9 @@ typedef struct PnvXScomInterfaceClass { #define PNV_XSCOM_LPC_BASE 0xb0020 #define PNV_XSCOM_LPC_SIZE 0x4 =20 +#define PNV_XSCOM_PSI_BASE 0x2010900 +#define PNV_XSCOM_PSI_SIZE 0x20 + extern void pnv_xscom_realize(PnvChip *chip, Error **errp); extern int pnv_xscom_populate(PnvChip *chip, void *fdt, int offset); =20 --=20 2.7.4 From nobody Sun Apr 28 23:40:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1488970483549671.3529759088957; Wed, 8 Mar 2017 02:54:43 -0800 (PST) Received: from localhost ([::1]:55517 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1clZEw-0007xm-9d for importer@patchew.org; Wed, 08 Mar 2017 05:54:42 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37142) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1clZDp-0007t5-CR for qemu-devel@nongnu.org; Wed, 08 Mar 2017 05:53:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1clZDm-0003Bg-57 for qemu-devel@nongnu.org; Wed, 08 Mar 2017 05:53:33 -0500 Received: from 8.mo177.mail-out.ovh.net ([46.105.61.98]:58745) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1clZDl-0003BK-Rw for qemu-devel@nongnu.org; Wed, 08 Mar 2017 05:53:30 -0500 Received: from player714.ha.ovh.net (b7.ovh.net [213.186.33.57]) by mo177.mail-out.ovh.net (Postfix) with ESMTP id B6D7C33BF9 for ; Wed, 8 Mar 2017 11:53:28 +0100 (CET) Received: from zorba.kaod.org.com (LFbn-1-10647-27.w90-89.abo.wanadoo.fr [90.89.233.27]) (Authenticated sender: clg@kaod.org) by player714.ha.ovh.net (Postfix) with ESMTPSA id 8C1553C007E; Wed, 8 Mar 2017 11:53:23 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 8 Mar 2017 11:52:50 +0100 Message-Id: <1488970371-8865-8-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1488970371-8865-1-git-send-email-clg@kaod.org> References: <1488970371-8865-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 16332304052349864934 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelhedrgeeggddujecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.61.98 Subject: [Qemu-devel] [PATCH for-2.10 7/8] ppc/pnv: Add OCC model stub with interrupt support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Benjamin Herrenschmidt The OCC is an on-chip microcontroller based on a ppc405 core used for various power management tasks. It comes with a pile of additional hardware sitting on the PIB (aka XSCOM bus). At this point we don't emulate it (nor plan to do so). However there is one facility which is provided by the surrounding hardware that we do need, which is the interrupt generation facility. OPAL uses it to send itself interrupts under some circumstances and there are other uses around the corner. So this implement just enough to support this. Signed-off-by: Benjamin Herrenschmidt [clg: - updated for qemu-2.9 - changed the XSCOM interface to fit new model - QOMified the model ] Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: David Gibson --- hw/ppc/Makefile.objs | 2 +- hw/ppc/pnv.c | 10 ++++ hw/ppc/pnv_occ.c | 136 +++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/ppc/pnv.h | 2 + include/hw/ppc/pnv_occ.h | 38 +++++++++++++ include/hw/ppc/pnv_xscom.h | 3 + 6 files changed, 190 insertions(+), 1 deletion(-) create mode 100644 hw/ppc/pnv_occ.c create mode 100644 include/hw/ppc/pnv_occ.h diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs index dc19ee17fa57..ef67ea820158 100644 --- a/hw/ppc/Makefile.objs +++ b/hw/ppc/Makefile.objs @@ -6,7 +6,7 @@ obj-$(CONFIG_PSERIES) +=3D spapr_hcall.o spapr_iommu.o spap= r_rtas.o obj-$(CONFIG_PSERIES) +=3D spapr_pci.o spapr_rtc.o spapr_drc.o spapr_rng.o obj-$(CONFIG_PSERIES) +=3D spapr_cpu_core.o spapr_ovec.o # IBM PowerNV -obj-$(CONFIG_POWERNV) +=3D pnv.o pnv_xscom.o pnv_core.o pnv_lpc.o pnv_psi.o +obj-$(CONFIG_POWERNV) +=3D pnv.o pnv_xscom.o pnv_core.o pnv_lpc.o pnv_psi.= o pnv_occ.o ifeq ($(CONFIG_PCI)$(CONFIG_PSERIES)$(CONFIG_LINUX), yyy) obj-y +=3D spapr_pci_vfio.o endif diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 85b00bf235c6..ca5a078bc6c6 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -714,6 +714,11 @@ static void pnv_chip_init(Object *obj) object_property_add_child(obj, "psi", OBJECT(&chip->psi), NULL); object_property_add_const_link(OBJECT(&chip->psi), "xics", OBJECT(qdev_get_machine()), &error_abor= t); + + object_initialize(&chip->occ, sizeof(chip->occ), TYPE_PNV_OCC); + object_property_add_child(obj, "occ", OBJECT(&chip->occ), NULL); + object_property_add_const_link(OBJECT(&chip->occ), "psi", + OBJECT(&chip->psi), &error_abort); } =20 static void pnv_chip_icp_realize(PnvChip *chip, Error **errp) @@ -824,6 +829,11 @@ static void pnv_chip_realize(DeviceState *dev, Error *= *errp) object_property_set_bool(OBJECT(&chip->lpc), true, "realized", &error_fatal); pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip->lpc.xscom_reg= s); + + /* Create the simplified OCC model */ + object_property_set_bool(OBJECT(&chip->occ), true, "realized", + &error_fatal); + pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip->occ.xscom_reg= s); } =20 static Property pnv_chip_properties[] =3D { diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c new file mode 100644 index 000000000000..32f167b77ea3 --- /dev/null +++ b/hw/ppc/pnv_occ.c @@ -0,0 +1,136 @@ +/* + * QEMU PowerNV Emulation of a few OCC related registers + * + * Copyright (c) 2016, IBM Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "hw/hw.h" +#include "sysemu/sysemu.h" +#include "target/ppc/cpu.h" +#include "qapi/error.h" +#include "qemu/log.h" + +#include "hw/ppc/pnv.h" +#include "hw/ppc/pnv_xscom.h" +#include "hw/ppc/pnv_occ.h" + +#define OCB_OCI_OCCMISC 0x4020 +#define OCB_OCI_OCCMISC_AND 0x4021 +#define OCB_OCI_OCCMISC_OR 0x4022 + +static void pnv_occ_set_misc(PnvOCC *occ, uint64_t val) +{ + bool irq_state; + + val &=3D 0xffff000000000000ull; + + occ->occmisc =3D val; + irq_state =3D !!(val >> 63); + pnv_psi_irq_set(occ->psi, PSIHB_IRQ_OCC, irq_state); +} + +static uint64_t pnv_occ_xscom_read(void *opaque, hwaddr addr, unsigned siz= e) +{ + PnvOCC *occ =3D PNV_OCC(opaque); + uint32_t offset =3D addr >> 3; + uint64_t val =3D 0; + + switch (offset) { + case OCB_OCI_OCCMISC: + val =3D occ->occmisc; + break; + default: + qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%" + HWADDR_PRIx "\n", addr); + } + return val; +} + +static void pnv_occ_xscom_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + PnvOCC *occ =3D PNV_OCC(opaque); + uint32_t offset =3D addr >> 3; + + switch (offset) { + case OCB_OCI_OCCMISC_AND: + pnv_occ_set_misc(occ, occ->occmisc & val); + break; + case OCB_OCI_OCCMISC_OR: + pnv_occ_set_misc(occ, occ->occmisc | val); + break; + case OCB_OCI_OCCMISC: + pnv_occ_set_misc(occ, val); + break; + default: + qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%" + HWADDR_PRIx "\n", addr); + } +} + +static const MemoryRegionOps pnv_occ_xscom_ops =3D { + .read =3D pnv_occ_xscom_read, + .write =3D pnv_occ_xscom_write, + .valid.min_access_size =3D 8, + .valid.max_access_size =3D 8, + .impl.min_access_size =3D 8, + .impl.max_access_size =3D 8, + .endianness =3D DEVICE_BIG_ENDIAN, +}; + + +static void pnv_occ_realize(DeviceState *dev, Error **errp) +{ + PnvOCC *occ =3D PNV_OCC(dev); + Object *obj; + Error *error =3D NULL; + + occ->occmisc =3D 0; + + /* get PSI object from chip */ + obj =3D object_property_get_link(OBJECT(dev), "psi", &error); + if (!obj) { + error_setg(errp, "%s: required link 'psi' not found: %s", + __func__, error_get_pretty(error)); + return; + } + occ->psi =3D PNV_PSI(obj); + + /* XScom region for OCC registers */ + pnv_xscom_region_init(&occ->xscom_regs, OBJECT(dev), &pnv_occ_xscom_op= s, + occ, "xscom-occ", PNV_XSCOM_OCC_SIZE); +} + +static void pnv_occ_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D pnv_occ_realize; +} + +static const TypeInfo pnv_occ_type_info =3D { + .name =3D TYPE_PNV_OCC, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(PnvOCC), + .class_init =3D pnv_occ_class_init, +}; + +static void pnv_occ_register_types(void) +{ + type_register_static(&pnv_occ_type_info); +} + +type_init(pnv_occ_register_types) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index f93ec32603b7..481f276699fa 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -24,6 +24,7 @@ #include "hw/ppc/pnv_lpc.h" #include "hw/ppc/xics.h" #include "hw/ppc/pnv_psi.h" +#include "hw/ppc/pnv_occ.h" =20 #define TYPE_PNV_CHIP "powernv-chip" #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP) @@ -60,6 +61,7 @@ typedef struct PnvChip { =20 PnvLpcController lpc; PnvPsi psi; + PnvOCC occ; } PnvChip; =20 typedef struct PnvChipClass { diff --git a/include/hw/ppc/pnv_occ.h b/include/hw/ppc/pnv_occ.h new file mode 100644 index 000000000000..94c9b6fe1384 --- /dev/null +++ b/include/hw/ppc/pnv_occ.h @@ -0,0 +1,38 @@ +/* + * QEMU PowerNV Emulation of a few OCC related registers + * + * Copyright (c) 2016, IBM Corporation. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ +#ifndef _PPC_PNV_OCC_H +#define _PPC_PNV_OCC_H + +#define TYPE_PNV_OCC "pnv-occ" +#define PNV_OCC(obj) OBJECT_CHECK(PnvOCC, (obj), TYPE_PNV_OCC) + +typedef struct PnvPsi PnvPsi; + +typedef struct PnvOCC { + DeviceState xd; + + /* OCC Misc interrupt */ + uint64_t occmisc; + + PnvPsi *psi; + + MemoryRegion xscom_regs; +} PnvOCC; + +#endif /* _PPC_PNV_OCC_H */ diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index 2938abd74955..226ff61900de 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -63,6 +63,9 @@ typedef struct PnvXScomInterfaceClass { #define PNV_XSCOM_PSI_BASE 0x2010900 #define PNV_XSCOM_PSI_SIZE 0x20 =20 +#define PNV_XSCOM_OCC_BASE 0x0066000 +#define PNV_XSCOM_OCC_SIZE 0x6000 + extern void pnv_xscom_realize(PnvChip *chip, Error **errp); extern int pnv_xscom_populate(PnvChip *chip, void *fdt, int offset); =20 --=20 2.7.4 From nobody Sun Apr 28 23:40:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1488970505860882.2377625685389; Wed, 8 Mar 2017 02:55:05 -0800 (PST) Received: from localhost ([::1]:55519 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1clZFI-0008JH-IG for importer@patchew.org; Wed, 08 Mar 2017 05:55:04 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37224) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1clZDu-0007yC-S3 for qemu-devel@nongnu.org; Wed, 08 Mar 2017 05:53:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1clZDr-0003DN-NZ for qemu-devel@nongnu.org; Wed, 08 Mar 2017 05:53:38 -0500 Received: from 3.mo177.mail-out.ovh.net ([46.105.36.172]:43415) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1clZDr-0003Cf-F3 for qemu-devel@nongnu.org; Wed, 08 Mar 2017 05:53:35 -0500 Received: from player714.ha.ovh.net (b7.ovh.net [213.186.33.57]) by mo177.mail-out.ovh.net (Postfix) with ESMTP id DF25438686 for ; Wed, 8 Mar 2017 11:53:33 +0100 (CET) Received: from zorba.kaod.org.com (LFbn-1-10647-27.w90-89.abo.wanadoo.fr [90.89.233.27]) (Authenticated sender: clg@kaod.org) by player714.ha.ovh.net (Postfix) with ESMTPSA id B42D53C00A2; Wed, 8 Mar 2017 11:53:28 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 8 Mar 2017 11:52:51 +0100 Message-Id: <1488970371-8865-9-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1488970371-8865-1-git-send-email-clg@kaod.org> References: <1488970371-8865-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 16333711427478784998 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelhedrgeeggddujecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.36.172 Subject: [Qemu-devel] [PATCH for-2.10 8/8] ppc/pnv: Add support for POWER8+ LPC Controller X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Benjamin Herrenschmidt It adds the Naples chip which supports proper LPC interrupts via the LPC controller rather than via an external CPLD. Signed-off-by: Benjamin Herrenschmidt [clg: - updated for qemu-2.9 - ported on latest PowerNV patchset ] Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: David Gibson --- hw/ppc/pnv.c | 15 ++++++++++++++- hw/ppc/pnv_lpc.c | 47 ++++++++++++++++++++++++++++++++++++++++++++= +-- include/hw/ppc/pnv_lpc.h | 9 +++++++++ 3 files changed, 68 insertions(+), 3 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index ca5a078bc6c6..65dfe5b4c97b 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -376,7 +376,14 @@ static void pnv_lpc_isa_irq_handler_cpld(void *opaque,= int n, int level) =20 static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level) { - /* XXX TODO */ + PnvChip *chip =3D opaque; + PnvLpcController *lpc =3D &chip->lpc; + + /* The Naples HW latches the 1 levels, clearing is done by SW */ + if (level) { + lpc->lpc_hc_irqstat |=3D LPC_HC_IRQ_SERIRQ0 >> n; + pnv_lpc_eval_irqs(lpc); + } } =20 static ISABus *pnv_isa_create(PnvChip *chip) @@ -719,6 +726,12 @@ static void pnv_chip_init(Object *obj) object_property_add_child(obj, "occ", OBJECT(&chip->occ), NULL); object_property_add_const_link(OBJECT(&chip->occ), "psi", OBJECT(&chip->psi), &error_abort); + + /* + * The LPC controller needs PSI to generate interrupts + */ + object_property_add_const_link(OBJECT(&chip->lpc), "psi", + OBJECT(&chip->psi), &error_abort); } =20 static void pnv_chip_icp_realize(PnvChip *chip, Error **errp) diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index 78db52415b11..20cbb6a0dbbd 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -250,6 +250,34 @@ static const MemoryRegionOps pnv_lpc_xscom_ops =3D { .endianness =3D DEVICE_BIG_ENDIAN, }; =20 +void pnv_lpc_eval_irqs(PnvLpcController *lpc) +{ + bool lpc_to_opb_irq =3D false; + + /* Update LPC controller to OPB line */ + if (lpc->lpc_hc_irqser_ctrl & LPC_HC_IRQSER_EN) { + uint32_t irqs; + + irqs =3D lpc->lpc_hc_irqstat & lpc->lpc_hc_irqmask; + lpc_to_opb_irq =3D (irqs !=3D 0); + } + + /* We don't honor the polarity register, it's pointless and unused + * anyway + */ + if (lpc_to_opb_irq) { + lpc->opb_irq_input |=3D OPB_MASTER_IRQ_LPC; + } else { + lpc->opb_irq_input &=3D ~OPB_MASTER_IRQ_LPC; + } + + /* Update OPB internal latch */ + lpc->opb_irq_stat |=3D lpc->opb_irq_input & lpc->opb_irq_mask; + + /* Reflect the interrupt */ + pnv_psi_irq_set(lpc->psi, PSIHB_IRQ_LPC_I2C, lpc->opb_irq_stat !=3D 0); +} + static uint64_t lpc_hc_read(void *opaque, hwaddr addr, unsigned size) { PnvLpcController *lpc =3D opaque; @@ -300,12 +328,15 @@ static void lpc_hc_write(void *opaque, hwaddr addr, u= int64_t val, break; case LPC_HC_IRQSER_CTRL: lpc->lpc_hc_irqser_ctrl =3D val; + pnv_lpc_eval_irqs(lpc); break; case LPC_HC_IRQMASK: lpc->lpc_hc_irqmask =3D val; + pnv_lpc_eval_irqs(lpc); break; case LPC_HC_IRQSTAT: lpc->lpc_hc_irqstat &=3D ~val; + pnv_lpc_eval_irqs(lpc); break; case LPC_HC_ERROR_ADDRESS: break; @@ -363,14 +394,15 @@ static void opb_master_write(void *opaque, hwaddr add= r, switch (addr) { case OPB_MASTER_LS_IRQ_STAT: lpc->opb_irq_stat &=3D ~val; + pnv_lpc_eval_irqs(lpc); break; case OPB_MASTER_LS_IRQ_MASK: - /* XXX Filter out reserved bits */ lpc->opb_irq_mask =3D val; + pnv_lpc_eval_irqs(lpc); break; case OPB_MASTER_LS_IRQ_POL: - /* XXX Filter out reserved bits */ lpc->opb_irq_pol =3D val; + pnv_lpc_eval_irqs(lpc); break; case OPB_MASTER_LS_IRQ_INPUT: /* Read only */ @@ -398,6 +430,8 @@ static const MemoryRegionOps opb_master_ops =3D { static void pnv_lpc_realize(DeviceState *dev, Error **errp) { PnvLpcController *lpc =3D PNV_LPC(dev); + Object *obj; + Error *error =3D NULL; =20 /* Reg inits */ lpc->lpc_hc_fw_rd_acc_size =3D LPC_HC_FW_RD_4B; @@ -441,6 +475,15 @@ static void pnv_lpc_realize(DeviceState *dev, Error **= errp) pnv_xscom_region_init(&lpc->xscom_regs, OBJECT(dev), &pnv_lpc_xscom_ops, lpc, "xscom-lpc", PNV_XSCOM_LPC_SIZE); + + /* get PSI object from chip */ + obj =3D object_property_get_link(OBJECT(dev), "psi", &error); + if (!obj) { + error_setg(errp, "%s: required link 'psi' not found: %s", + __func__, error_get_pretty(error)); + return; + } + lpc->psi =3D PNV_PSI(obj); } =20 static void pnv_lpc_class_init(ObjectClass *klass, void *data) diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h index 38e5506975aa..53040026c37b 100644 --- a/include/hw/ppc/pnv_lpc.h +++ b/include/hw/ppc/pnv_lpc.h @@ -23,6 +23,8 @@ #define PNV_LPC(obj) \ OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV_LPC) =20 +typedef struct PnvPsi PnvPsi; + typedef struct PnvLpcController { DeviceState parent; =20 @@ -62,6 +64,13 @@ typedef struct PnvLpcController { =20 /* XSCOM registers */ MemoryRegion xscom_regs; + + /* PSI to generate interrupts */ + PnvPsi *psi; } PnvLpcController; =20 +#define LPC_HC_IRQ_SERIRQ0 0x80000000 /* all bits down to ...= */ + +void pnv_lpc_eval_irqs(PnvLpcController *lpc); + #endif /* _PPC_PNV_LPC_H */ --=20 2.7.4