From nobody Fri May 3 19:10:40 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1488542422400275.7443931627663; Fri, 3 Mar 2017 04:00:22 -0800 (PST) Received: from localhost ([::1]:57395 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cjlsi-0000Um-3R for importer@patchew.org; Fri, 03 Mar 2017 07:00:20 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34623) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cjlsC-0000SP-DS for qemu-devel@nongnu.org; Fri, 03 Mar 2017 06:59:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cjlsB-0005M7-Mm for qemu-devel@nongnu.org; Fri, 03 Mar 2017 06:59:48 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:48727) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cjls9-0005JZ-OR; Fri, 03 Mar 2017 06:59:45 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1cjlrz-000628-Db; Fri, 03 Mar 2017 11:59:35 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Fri, 3 Mar 2017 11:59:34 +0000 Message-Id: <1488542374-1256-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH for-2.9] hw/misc/imx6_src: Don't crash trying to reset missing CPUs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Chubb , Jean-Christophe DUBOIS , =?UTF-8?q?Alex=20Benn=C3=A9e?= , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Commit 4881658a4b introduced a call to arm_get_cpu_by_id(), and Coverity noticed that we weren't checking that it didn't return NULL (CID 1371652). Normally this won't happen (because all 4 CPUs are expected to exist), but it's possible the user requested fewer CPUs on the command line. Handle this possibility by silently doing nothing, which is the same behaviour as before commit 4881658a4b and also how we handle the other CPU operations (since we ignore the INVALID_PARAM returns from arm_set_cpu_on() and friends). There is a slight behavioural difference to the pre-4881658a4b situation: the "reset this core" bit will remain set rather than not being permitted to be set. The imx6 datasheet is unclear about the behaviour in this odd corner case, so we opt for the simpler code rather than complicated logic to maintain identical behaviour. Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e --- I couldn't actually get this to crash even with -smp 1 with my test image, but we should fix it anyhow. hw/misc/imx6_src.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/misc/imx6_src.c b/hw/misc/imx6_src.c index edbb756..cfb0871 100644 --- a/hw/misc/imx6_src.c +++ b/hw/misc/imx6_src.c @@ -143,13 +143,17 @@ static void imx6_defer_clear_reset_bit(int cpuid, unsigned long reset_shift) { struct SRCSCRResetInfo *ri; + CPUState *cpu =3D arm_get_cpu_by_id(cpuid); + + if (!cpu) { + return; + } =20 ri =3D g_malloc(sizeof(struct SRCSCRResetInfo)); ri->s =3D s; ri->reset_bit =3D reset_shift; =20 - async_run_on_cpu(arm_get_cpu_by_id(cpuid), imx6_clear_reset_bit, - RUN_ON_CPU_HOST_PTR(ri)); + async_run_on_cpu(cpu, imx6_clear_reset_bit, RUN_ON_CPU_HOST_PTR(ri)); } =20 =20 --=20 2.7.4