From nobody Wed Dec 17 21:52:17 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1488302398714248.21712354618887; Tue, 28 Feb 2017 09:19:58 -0800 (PST) Received: from localhost ([::1]:35785 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cilRM-0003oZ-7L for importer@patchew.org; Tue, 28 Feb 2017 12:19:56 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43229) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cilNv-0001fe-So for qemu-devel@nongnu.org; Tue, 28 Feb 2017 12:16:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cilNu-00032G-Gd for qemu-devel@nongnu.org; Tue, 28 Feb 2017 12:16:23 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:48711) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cilNu-0002xz-8b for qemu-devel@nongnu.org; Tue, 28 Feb 2017 12:16:22 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1cilNt-0003R5-E0 for qemu-devel@nongnu.org; Tue, 28 Feb 2017 17:16:21 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 28 Feb 2017 17:16:02 +0000 Message-Id: <1488302176-19463-8-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1488302176-19463-1-git-send-email-peter.maydell@linaro.org> References: <1488302176-19463-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 07/21] armv7m: Make bitband device take the address space to access X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Instead of the bitband device doing a cpu_physical_memory_read/write, make it take a MemoryRegion which specifies where it should be accessing, and use address_space_read/write to access the corresponding AddressSpace. Since this entails pretty much a rewrite, convert away from old_mmio in the process. Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Message-id: 1487604965-23220-8-git-send-email-peter.maydell@linaro.org --- include/hw/arm/armv7m.h | 2 + hw/arm/armv7m.c | 166 +++++++++++++++++++++++---------------------= ---- 2 files changed, 81 insertions(+), 87 deletions(-) diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h index 3333c91..a9b3f2a 100644 --- a/include/hw/arm/armv7m.h +++ b/include/hw/arm/armv7m.h @@ -21,8 +21,10 @@ typedef struct { SysBusDevice parent_obj; /*< public >*/ =20 + AddressSpace *source_as; MemoryRegion iomem; uint32_t base; + MemoryRegion *source_memory; } BitBandState; =20 #define TYPE_ARMV7M "armv7m" diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index de97466..c8a11f2 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -23,103 +23,73 @@ /* Bitbanded IO. Each word corresponds to a single bit. */ =20 /* Get the byte address of the real memory for a bitband access. */ -static inline uint32_t bitband_addr(void * opaque, uint32_t addr) +static inline hwaddr bitband_addr(BitBandState *s, hwaddr offset) { - uint32_t res; - - res =3D *(uint32_t *)opaque; - res |=3D (addr & 0x1ffffff) >> 5; - return res; - -} - -static uint32_t bitband_readb(void *opaque, hwaddr offset) -{ - uint8_t v; - cpu_physical_memory_read(bitband_addr(opaque, offset), &v, 1); - return (v & (1 << ((offset >> 2) & 7))) !=3D 0; -} - -static void bitband_writeb(void *opaque, hwaddr offset, - uint32_t value) -{ - uint32_t addr; - uint8_t mask; - uint8_t v; - addr =3D bitband_addr(opaque, offset); - mask =3D (1 << ((offset >> 2) & 7)); - cpu_physical_memory_read(addr, &v, 1); - if (value & 1) - v |=3D mask; - else - v &=3D ~mask; - cpu_physical_memory_write(addr, &v, 1); -} - -static uint32_t bitband_readw(void *opaque, hwaddr offset) -{ - uint32_t addr; - uint16_t mask; - uint16_t v; - addr =3D bitband_addr(opaque, offset) & ~1; - mask =3D (1 << ((offset >> 2) & 15)); - mask =3D tswap16(mask); - cpu_physical_memory_read(addr, &v, 2); - return (v & mask) !=3D 0; -} - -static void bitband_writew(void *opaque, hwaddr offset, - uint32_t value) -{ - uint32_t addr; - uint16_t mask; - uint16_t v; - addr =3D bitband_addr(opaque, offset) & ~1; - mask =3D (1 << ((offset >> 2) & 15)); - mask =3D tswap16(mask); - cpu_physical_memory_read(addr, &v, 2); - if (value & 1) - v |=3D mask; - else - v &=3D ~mask; - cpu_physical_memory_write(addr, &v, 2); + return s->base | (offset & 0x1ffffff) >> 5; } =20 -static uint32_t bitband_readl(void *opaque, hwaddr offset) +static MemTxResult bitband_read(void *opaque, hwaddr offset, + uint64_t *data, unsigned size, MemTxAttrs = attrs) { - uint32_t addr; - uint32_t mask; - uint32_t v; - addr =3D bitband_addr(opaque, offset) & ~3; - mask =3D (1 << ((offset >> 2) & 31)); - mask =3D tswap32(mask); - cpu_physical_memory_read(addr, &v, 4); - return (v & mask) !=3D 0; + BitBandState *s =3D opaque; + uint8_t buf[4]; + MemTxResult res; + int bitpos, bit; + hwaddr addr; + + assert(size <=3D 4); + + /* Find address in underlying memory and round down to multiple of siz= e */ + addr =3D bitband_addr(s, offset) & (-size); + res =3D address_space_read(s->source_as, addr, attrs, buf, size); + if (res) { + return res; + } + /* Bit position in the N bytes read... */ + bitpos =3D (offset >> 2) & ((size * 8) - 1); + /* ...converted to byte in buffer and bit in byte */ + bit =3D (buf[bitpos >> 3] >> (bitpos & 7)) & 1; + *data =3D bit; + return MEMTX_OK; } =20 -static void bitband_writel(void *opaque, hwaddr offset, - uint32_t value) +static MemTxResult bitband_write(void *opaque, hwaddr offset, uint64_t val= ue, + unsigned size, MemTxAttrs attrs) { - uint32_t addr; - uint32_t mask; - uint32_t v; - addr =3D bitband_addr(opaque, offset) & ~3; - mask =3D (1 << ((offset >> 2) & 31)); - mask =3D tswap32(mask); - cpu_physical_memory_read(addr, &v, 4); - if (value & 1) - v |=3D mask; - else - v &=3D ~mask; - cpu_physical_memory_write(addr, &v, 4); + BitBandState *s =3D opaque; + uint8_t buf[4]; + MemTxResult res; + int bitpos, bit; + hwaddr addr; + + assert(size <=3D 4); + + /* Find address in underlying memory and round down to multiple of siz= e */ + addr =3D bitband_addr(s, offset) & (-size); + res =3D address_space_read(s->source_as, addr, attrs, buf, size); + if (res) { + return res; + } + /* Bit position in the N bytes read... */ + bitpos =3D (offset >> 2) & ((size * 8) - 1); + /* ...converted to byte in buffer and bit in byte */ + bit =3D 1 << (bitpos & 7); + if (value & 1) { + buf[bitpos >> 3] |=3D bit; + } else { + buf[bitpos >> 3] &=3D ~bit; + } + return address_space_write(s->source_as, addr, attrs, buf, size); } =20 static const MemoryRegionOps bitband_ops =3D { - .old_mmio =3D { - .read =3D { bitband_readb, bitband_readw, bitband_readl, }, - .write =3D { bitband_writeb, bitband_writew, bitband_writel, }, - }, + .read_with_attrs =3D bitband_read, + .write_with_attrs =3D bitband_write, .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl.min_access_size =3D 1, + .impl.max_access_size =3D 4, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 4, }; =20 static void bitband_init(Object *obj) @@ -127,11 +97,30 @@ static void bitband_init(Object *obj) BitBandState *s =3D BITBAND(obj); SysBusDevice *dev =3D SYS_BUS_DEVICE(obj); =20 - memory_region_init_io(&s->iomem, obj, &bitband_ops, &s->base, + object_property_add_link(obj, "source-memory", + TYPE_MEMORY_REGION, + (Object **)&s->source_memory, + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_UNREF_ON_RELEASE, + &error_abort); + memory_region_init_io(&s->iomem, obj, &bitband_ops, s, "bitband", 0x02000000); sysbus_init_mmio(dev, &s->iomem); } =20 +static void bitband_realize(DeviceState *dev, Error **errp) +{ + BitBandState *s =3D BITBAND(dev); + + if (!s->source_memory) { + error_setg(errp, "source-memory property not set"); + return; + } + + s->source_as =3D address_space_init_shareable(s->source_memory, + "bitband-source"); +} + /* Board init. */ =20 static const hwaddr bitband_input_addr[ARMV7M_NUM_BITBANDS] =3D { @@ -250,6 +239,8 @@ static void armv7m_realize(DeviceState *dev, Error **er= rp) error_propagate(errp, err); return; } + object_property_set_link(obj, OBJECT(s->board_memory), + "source-memory", &error_abort); object_property_set_bool(obj, true, "realized", &err); if (err !=3D NULL) { error_propagate(errp, err); @@ -365,6 +356,7 @@ static void bitband_class_init(ObjectClass *klass, void= *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 + dc->realize =3D bitband_realize; dc->props =3D bitband_properties; } =20 --=20 2.7.4