From nobody Mon May 20 02:35:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1488277056089697.9610737811854; Tue, 28 Feb 2017 02:17:36 -0800 (PST) Received: from localhost ([::1]:59927 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cieqb-0001Im-KB for importer@patchew.org; Tue, 28 Feb 2017 05:17:33 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58978) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cied8-0006pa-3S for qemu-devel@nongnu.org; Tue, 28 Feb 2017 05:03:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cied2-00047l-QD for qemu-devel@nongnu.org; Tue, 28 Feb 2017 05:03:38 -0500 Received: from greensocs.com ([193.104.36.180]:38345) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cied2-00046s-B3 for qemu-devel@nongnu.org; Tue, 28 Feb 2017 05:03:32 -0500 Received: from localhost (localhost [127.0.0.1]) by greensocs.com (Postfix) with ESMTP id A5BF440CA71; Tue, 28 Feb 2017 11:03:30 +0100 (CET) Received: from greensocs.com ([127.0.0.1]) by localhost (gs-01.greensocs.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ORiU_5TQVane; Tue, 28 Feb 2017 11:03:29 +0100 (CET) Received: from corsair.home (bd231-7-88-127-3-24.fbx.proxad.net [88.127.3.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: fred.konrad@greensocs.com) by greensocs.com (Postfix) with ESMTPSA id 30C213FE898; Tue, 28 Feb 2017 11:03:29 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1488276210; bh=PyqSsv6zU1gTYOXHGDCCBE11OB9EUkoMATPr23aJ3gc=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=oVh1A3pLZwn2V7XSeQ9E55hNH6UuD5NDGitXhaA4f/jAYIfD51wyU22vUX6AoQZgu koKWjsG3Ur3B1uf29Wsft0OCvNgP7DAXUhjlTBmvvx5Yc/nvnquecO1y3G8KK8Ht3d HVtCOA9ahNdWUx1RuGKyT697kEiLFGKBjq7MxXLQ= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1488276209; bh=PyqSsv6zU1gTYOXHGDCCBE11OB9EUkoMATPr23aJ3gc=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=hNP/wrkqt81rE1ds4b8pmFgkE0lIoOCWBi8FWsvDbdg0WJgSRNU2+P3M/z+g4tbDB dPXv+Qs2QWpbYRUeS/6VjUBzBnHjzVBi1tmaFzCaDONXOUM/GcFRurPSXIwz7mpY9B gU8khgjOD2LXAn0FDMFrDH0GdTeGfW64powuFF6Y= From: fred.konrad@greensocs.com To: qemu-devel@nongnu.org Date: Tue, 28 Feb 2017 11:02:56 +0100 Message-Id: <1488276185-31168-2-git-send-email-fred.konrad@greensocs.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1488276185-31168-1-git-send-email-fred.konrad@greensocs.com> References: <1488276185-31168-1-git-send-email-fred.konrad@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v3 01/10] qemu-clk: introduce qemu-clk qom object X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, mark.burton@greensocs.com, alistair.francis@xilinx.com, clg@kaod.org, fred.konrad@greensocs.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: KONRAD Frederic This introduces qemu-clk qom object. Signed-off-by: KONRAD Frederic V2 -> V3: * s/qemu_clk/QEMUClock/g --- Makefile.objs | 1 + include/qemu/qemu-clock.h | 40 +++++++++++++++++++++++++++++++++++++ qemu-clock.c | 50 +++++++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 91 insertions(+) create mode 100644 include/qemu/qemu-clock.h create mode 100644 qemu-clock.c diff --git a/Makefile.objs b/Makefile.objs index e740500..0b8b8ff 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -75,6 +75,7 @@ common-obj-y +=3D backends/ common-obj-$(CONFIG_SECCOMP) +=3D qemu-seccomp.o =20 common-obj-$(CONFIG_FDT) +=3D device_tree.o +common-obj-y +=3D qemu-clock.o =20 ###################################################################### # qapi diff --git a/include/qemu/qemu-clock.h b/include/qemu/qemu-clock.h new file mode 100644 index 0000000..446a490 --- /dev/null +++ b/include/qemu/qemu-clock.h @@ -0,0 +1,40 @@ +/* + * QEMU Clock + * + * Copyright (C) 2016 : GreenSocs Ltd + * http://www.greensocs.com/ , email: info@greensocs.com + * + * Frederic Konrad + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + * + */ + +#ifndef QEMU_CLOCK_H +#define QEMU_CLOCK_H + +#include "qemu/osdep.h" +#include "qom/object.h" + +#define TYPE_CLOCK "qemu-clk" +#define QEMU_CLOCK(obj) OBJECT_CHECK(QEMUClock, (obj), TYPE_CLOCK) + +typedef struct QEMUClock { + /*< private >*/ + Object parent_obj; +} QEMUClock; + +#endif /* QEMU_CLOCK_H */ + + diff --git a/qemu-clock.c b/qemu-clock.c new file mode 100644 index 0000000..3bef144 --- /dev/null +++ b/qemu-clock.c @@ -0,0 +1,50 @@ +/* + * QEMU Clock + * + * Copyright (C) 2016 : GreenSocs Ltd + * http://www.greensocs.com/ , email: info@greensocs.com + * + * Frederic Konrad + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + * + */ + +#include "qemu/osdep.h" +#include "qemu/qemu-clock.h" +#include "hw/hw.h" +#include "qemu/log.h" + +#ifndef DEBUG_QEMU_CLOCK +#define DEBUG_QEMU_CLOCK 0 +#endif + +#define DPRINTF(fmt, args...) do { = \ + if (DEBUG_QEMU_CLOCK) { = \ + qemu_log("%s: " fmt, __func__, ## args); = \ + } = \ +} while (0); + +static const TypeInfo qemu_clk_info =3D { + .name =3D TYPE_CLOCK, + .parent =3D TYPE_OBJECT, + .instance_size =3D sizeof(QEMUClock), +}; + +static void qemu_clk_register_types(void) +{ + type_register_static(&qemu_clk_info); +} + +type_init(qemu_clk_register_types); --=20 1.8.3.1 From nobody Mon May 20 02:35:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 148827634324034.3780042359989; Tue, 28 Feb 2017 02:05:43 -0800 (PST) Received: from localhost ([::1]:59854 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cief7-00084d-JG for importer@patchew.org; Tue, 28 Feb 2017 05:05:41 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58921) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cied5-0006oH-Uo for qemu-devel@nongnu.org; Tue, 28 Feb 2017 05:03:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cied2-00047u-SD for qemu-devel@nongnu.org; Tue, 28 Feb 2017 05:03:35 -0500 Received: from greensocs.com ([193.104.36.180]:38360) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cied2-000472-GR for qemu-devel@nongnu.org; Tue, 28 Feb 2017 05:03:32 -0500 Received: from localhost (localhost [127.0.0.1]) by greensocs.com (Postfix) with ESMTP id 05E9240D43D; Tue, 28 Feb 2017 11:03:31 +0100 (CET) Received: from greensocs.com ([127.0.0.1]) by localhost (gs-01.greensocs.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id VJZ2B-_NxFC4; Tue, 28 Feb 2017 11:03:30 +0100 (CET) Received: from corsair.home (bd231-7-88-127-3-24.fbx.proxad.net [88.127.3.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: fred.konrad@greensocs.com) by greensocs.com (Postfix) with ESMTPSA id C115840CA6C; Tue, 28 Feb 2017 11:03:29 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1488276211; bh=NbzuHVCFaK3tE4gJm4arZsr3i/uHTYFyAl/AEsEdTR0=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=lBimJGORe7yaz24ZjwL4vTmeC8huEuDLreFY+foUdbhS+USag9+Ez4jrZH9rLxwGZ dFNtVNGUhV4kZPYZvom0KLb4OQG3rqDUrYy24sIVGkIYv00Q3TpAfhI1XchaqlKzup cCRHh88sXem12SL1K5ZzPwRLdB2zRsCAbyVnlVBI= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1488276210; bh=NbzuHVCFaK3tE4gJm4arZsr3i/uHTYFyAl/AEsEdTR0=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=2xEhDOrK76i0j8Jq52/V9ncgfBsBYwK/E4TMQ/cMduvQxORk2wUxm7rpqDAgGPOvi M/1I/rGV1Gf/7DX7S2Q6j8y9JR9vUmpCQhGW1nqakEbehl8Lg5yxL2skvmIgrGT4AI GlJMbr0I3riXW0DzI+F0nPfXK9i7793KhLtUQXAg= From: fred.konrad@greensocs.com To: qemu-devel@nongnu.org Date: Tue, 28 Feb 2017 11:02:57 +0100 Message-Id: <1488276185-31168-3-git-send-email-fred.konrad@greensocs.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1488276185-31168-1-git-send-email-fred.konrad@greensocs.com> References: <1488276185-31168-1-git-send-email-fred.konrad@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v3 02/10] qemu-clk: allow to add a clock to a device X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, mark.burton@greensocs.com, alistair.francis@xilinx.com, clg@kaod.org, fred.konrad@greensocs.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: KONRAD Frederic This allows to add a clock to a DeviceState. Contrary to gpios, the clock pins are not contained in the DeviceState but with the child property so they can appears in the qom-tree. Signed-off-by: KONRAD Frederic V2 -> V3: * s/qemu_clk/QEMUClock/g V1 -> V2: * Rename the function use 'add' instead of 'attach' --- include/qemu/qemu-clock.h | 24 +++++++++++++++++++++++- qemu-clock.c | 23 +++++++++++++++++++++++ 2 files changed, 46 insertions(+), 1 deletion(-) diff --git a/include/qemu/qemu-clock.h b/include/qemu/qemu-clock.h index 446a490..ffe743d 100644 --- a/include/qemu/qemu-clock.h +++ b/include/qemu/qemu-clock.h @@ -33,8 +33,30 @@ typedef struct QEMUClock { /*< private >*/ Object parent_obj; + char *name; /* name of this clock in the device. */ } QEMUClock; =20 -#endif /* QEMU_CLOCK_H */ +/** + * qemu_clk_device_add_clock: + * @dev: the device on which the clock needs to be added. + * @clk: the clock which needs to be added. + * @name: the name of the clock can't be NULL. + * + * Add @clk to device @dev as a clock named @name. + * + */ +void qemu_clk_device_add_clock(DeviceState *dev, QEMUClock *clk, + const char *name); =20 +/** + * qemu_clk_device_get_clock: + * @dev: the device which contains the clock. + * @name: the name of the clock. + * + * Get the clock named @name contained in the device @dev, or NULL if not = found. + * + * Returns the clock named @name contained in @dev. + */ +QEMUClock *qemu_clk_device_get_clock(DeviceState *dev, const char *name); =20 +#endif /* QEMU_CLOCK_H */ diff --git a/qemu-clock.c b/qemu-clock.c index 3bef144..6eeecf3 100644 --- a/qemu-clock.c +++ b/qemu-clock.c @@ -25,6 +25,7 @@ #include "qemu/qemu-clock.h" #include "hw/hw.h" #include "qemu/log.h" +#include "qapi/error.h" =20 #ifndef DEBUG_QEMU_CLOCK #define DEBUG_QEMU_CLOCK 0 @@ -36,6 +37,28 @@ } = \ } while (0); =20 +void qemu_clk_device_add_clock(DeviceState *dev, QEMUClock *clk, + const char *name) +{ + assert(name); + assert(!clk->name); + object_property_add_child(OBJECT(dev), name, OBJECT(clk), &error_abort= ); + clk->name =3D g_strdup(name); +} + +QEMUClock *qemu_clk_device_get_clock(DeviceState *dev, const char *name) +{ + gchar *path =3D NULL; + Object *clk; + bool ambiguous; + + path =3D g_strdup_printf("%s/%s", object_get_canonical_path(OBJECT(dev= )), + name); + clk =3D object_resolve_path(path, &ambiguous); + g_free(path); + return QEMU_CLOCK(clk); +} + static const TypeInfo qemu_clk_info =3D { .name =3D TYPE_CLOCK, .parent =3D TYPE_OBJECT, --=20 1.8.3.1 From nobody Mon May 20 02:35:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1488276486798408.9982510419428; Tue, 28 Feb 2017 02:08:06 -0800 (PST) Received: from localhost ([::1]:59869 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ciehR-0001qG-9P for importer@patchew.org; Tue, 28 Feb 2017 05:08:05 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58919) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cied5-0006oF-Uk for qemu-devel@nongnu.org; Tue, 28 Feb 2017 05:03:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cied2-00047h-Pq for qemu-devel@nongnu.org; Tue, 28 Feb 2017 05:03:35 -0500 Received: from greensocs.com ([193.104.36.180]:38376) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cied2-00047G-D2 for qemu-devel@nongnu.org; Tue, 28 Feb 2017 05:03:32 -0500 Received: from localhost (localhost [127.0.0.1]) by greensocs.com (Postfix) with ESMTP id AADEC40CA94; Tue, 28 Feb 2017 11:03:31 +0100 (CET) Received: from greensocs.com ([127.0.0.1]) by localhost (gs-01.greensocs.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id wo1eoV95045R; Tue, 28 Feb 2017 11:03:30 +0100 (CET) Received: from corsair.home (bd231-7-88-127-3-24.fbx.proxad.net [88.127.3.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: fred.konrad@greensocs.com) by greensocs.com (Postfix) with ESMTPSA id 5BBD01A5656; Tue, 28 Feb 2017 11:03:30 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1488276211; bh=NYVATN0wgqVZ7Rb+RKmNRrA+agIKrLHOygt8p6+W4vM=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=mU9nR3rQGqDeTMM+QrY1nKvjGeWLLHCsdpkPKMhmj+d0M+ZzJQq3pnbuxiS6rtXU5 Fr0uG2pqkPWZiiw6ZcB9bsxotLvsG/nxKaxg7fDv+Yo3X6GbgyD/A9vGIYdcwEgxNN 8HOEEaxHCt+6pLdbudDkzrQjGv3857eufwcGIlgA= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1488276210; bh=NYVATN0wgqVZ7Rb+RKmNRrA+agIKrLHOygt8p6+W4vM=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=GRrHOneP0g1eBMbyGTM6n1mzS7/9aRS+rKVoAZEnk1yvMPMj2QYomlySFDBRXzDFE Mnto4+Zz+/Xlv6oRpt+VRcU9FYXffi5VP/NiapbCZjKxevnMY7zsKGKAfo3VHNA6QZ YvL1dsxoXiQXJOJuvwqwdtVied7yJLN3BE4FTl8c= From: fred.konrad@greensocs.com To: qemu-devel@nongnu.org Date: Tue, 28 Feb 2017 11:02:58 +0100 Message-Id: <1488276185-31168-4-git-send-email-fred.konrad@greensocs.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1488276185-31168-1-git-send-email-fred.konrad@greensocs.com> References: <1488276185-31168-1-git-send-email-fred.konrad@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v3 03/10] qemu-clk: allow to bind two clocks together X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, mark.burton@greensocs.com, alistair.francis@xilinx.com, clg@kaod.org, fred.konrad@greensocs.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: KONRAD Frederic This introduces the clock binding and the update part. When the qemu_clk_rate_update(qemu_clk, int) function is called: * The clock callback is called on the qemu_clk so it can change the rate. * The qemu_clk_rate_update function is called on all the driven clock. Signed-off-by: KONRAD Frederic V2 -> V3: * s/qemu_clk/QEMUClock/g * Rename in_rate to ref_rate * Rename out_rate to rate * Rename qemu_clk_bind_clock to qemu_clk_bind V1 -> V2: * Rename qemu_clk_on_rate_update_cb to QEMUClkRateUpdateCallback and move the pointer to the structure instead of having a pointer-to-functi= on type. --- include/qemu/qemu-clock.h | 67 +++++++++++++++++++++++++++++++++++++++++++= ++++ qemu-clock.c | 58 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 125 insertions(+) diff --git a/include/qemu/qemu-clock.h b/include/qemu/qemu-clock.h index ffe743d..f80de56 100644 --- a/include/qemu/qemu-clock.h +++ b/include/qemu/qemu-clock.h @@ -30,12 +30,25 @@ #define TYPE_CLOCK "qemu-clk" #define QEMU_CLOCK(obj) OBJECT_CHECK(QEMUClock, (obj), TYPE_CLOCK) =20 +typedef struct ClkList ClkList; +typedef uint64_t QEMUClkRateUpdateCallback(void *opaque, uint64_t rate); + typedef struct QEMUClock { /*< private >*/ Object parent_obj; char *name; /* name of this clock in the device. */ + uint64_t ref_rate; /* rate of the clock which drive this pin. */ + uint64_t rate; /* rate of this clock pin. */ + void *opaque; + QEMUClkRateUpdateCallback *cb; + QLIST_HEAD(, ClkList) bound; } QEMUClock; =20 +struct ClkList { + QEMUClock *clk; + QLIST_ENTRY(ClkList) node; +}; + /** * qemu_clk_device_add_clock: * @dev: the device on which the clock needs to be added. @@ -59,4 +72,58 @@ void qemu_clk_device_add_clock(DeviceState *dev, QEMUClo= ck *clk, */ QEMUClock *qemu_clk_device_get_clock(DeviceState *dev, const char *name); =20 +/** + * qemu_clk_bind: + * @out: the clock output. + * @in: the clock input. + * + * Connect the clock together. This is unidirectional so a + * qemu_clk_update_rate will go from @out to @in. + * + */ +void qemu_clk_bind(QEMUClock *out, QEMUClock *in); + +/** + * qemu_clk_unbind: + * @out: the clock output. + * @in: the clock input. + * + * Disconnect the clocks if they were bound together. + * + */ +void qemu_clk_unbind(QEMUClock *out, QEMUClock *in); + +/** + * qemu_clk_update_rate: + * @clk: the clock to update. + * @rate: the new rate in Hz. + * + * Update the @clk to the new @rate. + * + */ +void qemu_clk_update_rate(QEMUClock *clk, uint64_t rate); + +/** + * qemu_clk_refresh: + * @clk: the clock to be refreshed. + * + * If a model alters the topology of a clock tree, it must call this funct= ion on + * the clock source to refresh the clock tree. + * + */ +void qemu_clk_refresh(QEMUClock *clk); + +/** + * qemu_clk_set_callback: + * @clk: the clock associated to the callback. + * @cb: the function which is called when a refresh happen on the clock @c= lk. + * @opaque: the opaque data passed to the callback. + * + * Set the callback @cb which will be called when the clock @clk is update= d. + * + */ +void qemu_clk_set_callback(QEMUClock *clk, + QEMUClkRateUpdateCallback *cb, + void *opaque); + #endif /* QEMU_CLOCK_H */ diff --git a/qemu-clock.c b/qemu-clock.c index 6eeecf3..24719e2 100644 --- a/qemu-clock.c +++ b/qemu-clock.c @@ -37,6 +37,64 @@ } = \ } while (0); =20 +void qemu_clk_refresh(QEMUClock *clk) +{ + qemu_clk_update_rate(clk, clk->ref_rate); +} + +void qemu_clk_update_rate(QEMUClock *clk, uint64_t rate) +{ + ClkList *child; + + clk->ref_rate =3D rate; + clk->rate =3D rate; + + if (clk->cb) { + clk->rate =3D clk->cb(clk->opaque, rate); + } + + DPRINTF("%s output rate updated to %" PRIu64 "\n", + object_get_canonical_path(OBJECT(clk)), + clk->rate); + + QLIST_FOREACH(child, &clk->bound, node) { + qemu_clk_update_rate(child->clk, clk->rate); + } +} + +void qemu_clk_bind(QEMUClock *out, QEMUClock *in) +{ + ClkList *child; + + child =3D g_malloc(sizeof(child)); + assert(child); + child->clk =3D in; + object_ref(OBJECT(in)); + QLIST_INSERT_HEAD(&out->bound, child, node); + qemu_clk_update_rate(in, out->rate); +} + +void qemu_clk_unbind(QEMUClock *out, QEMUClock *in) +{ + ClkList *child, *next; + + QLIST_FOREACH_SAFE(child, &out->bound, node, next) { + if (child->clk =3D=3D in) { + QLIST_REMOVE(child, node); + g_free(child); + object_unref(OBJECT(in)); + } + } +} + +void qemu_clk_set_callback(QEMUClock *clk, + QEMUClkRateUpdateCallback *cb, + void *opaque) +{ + clk->cb =3D cb; + clk->opaque =3D opaque; +} + void qemu_clk_device_add_clock(DeviceState *dev, QEMUClock *clk, const char *name) { --=20 1.8.3.1 From nobody Mon May 20 02:35:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1488277193735895.5214115288566; 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charset="utf-8" From: KONRAD Frederic This introduces a clock init array to ease the clock tree construction. Signed-off-by: KONRAD Frederic V2 -> V3: * s/QEMUClock/qemu_clk/g --- include/qemu/qemu-clock.h | 23 +++++++++++++++++++++++ qemu-clock.c | 17 +++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/include/qemu/qemu-clock.h b/include/qemu/qemu-clock.h index f80de56..1c57df4 100644 --- a/include/qemu/qemu-clock.h +++ b/include/qemu/qemu-clock.h @@ -49,6 +49,29 @@ struct ClkList { QLIST_ENTRY(ClkList) node; }; =20 +typedef struct ClockInitElement { + const char *name; /* Name to give to the clock. */ + size_t offset; /* Offset of the qemu_clk field in the object. = */ + QEMUClkRateUpdateCallback *cb; +} ClockInitElement; + +#define DEVICE_CLOCK(_state, _field, _cb) { = \ + .name =3D #_field, = \ + .offset =3D offsetof(_state, _field), = \ + .cb =3D _cb = \ +} + +#define DEVICE_CLOCK_END() { = \ + .name =3D NULL = \ +} + +/** + * qemu_clk_init_device: + * @obj: the Object which need to be initialized. + * @array: the array of ClockInitElement to be used. + */ +void qemu_clk_init_device(Object *obj, ClockInitElement *array); + /** * qemu_clk_device_add_clock: * @dev: the device on which the clock needs to be added. diff --git a/qemu-clock.c b/qemu-clock.c index 24719e2..8f342f6 100644 --- a/qemu-clock.c +++ b/qemu-clock.c @@ -26,6 +26,7 @@ #include "hw/hw.h" #include "qemu/log.h" #include "qapi/error.h" +#include "hw/qdev-core.h" =20 #ifndef DEBUG_QEMU_CLOCK #define DEBUG_QEMU_CLOCK 0 @@ -37,6 +38,22 @@ } = \ } while (0); =20 +void qemu_clk_init_device(Object *obj, ClockInitElement *array) +{ + QEMUClock **cur =3D NULL; + + while (array->name !=3D NULL) { + DPRINTF("init clock named %s\n", array->name); + cur =3D (((void *)obj) + array->offset); + *cur =3D QEMU_CLOCK(object_new(TYPE_CLOCK)); + qemu_clk_device_add_clock(DEVICE(obj), *cur, array->name); + if (array->cb) { + qemu_clk_set_callback(*cur, array->cb, obj); + } + array++; + } +} + void qemu_clk_refresh(QEMUClock *clk) { qemu_clk_update_rate(clk, clk->ref_rate); --=20 1.8.3.1 From nobody Mon May 20 02:35:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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dkim=pass (1024-bit key) header.d=greensocs.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1488276212; bh=aie+LvoBgdg9zPZvxUHc9Zkvkl+jOsixFd9Cwg0s9fg=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=nLIpcsPzTcT+yE+hG8xlbozexm3jRs5/xaqqcARUFX4ErGdwMjxcF9CqQez4tw5fb 7prIhs2drWWcPEE2QWEBsRqOU8aauMhVdCB1FB0KrUR58QVItJCroH8Y+dRb+c2Wle L1wsZ7Npa+T8x3fNTCuaPnwuZ8gK0vq1mXH7qnbc= From: fred.konrad@greensocs.com To: qemu-devel@nongnu.org Date: Tue, 28 Feb 2017 11:03:00 +0100 Message-Id: <1488276185-31168-6-git-send-email-fred.konrad@greensocs.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1488276185-31168-1-git-send-email-fred.konrad@greensocs.com> References: <1488276185-31168-1-git-send-email-fred.konrad@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v3 05/10] qdev-monitor: print the device's clock with info qtree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, mark.burton@greensocs.com, alistair.francis@xilinx.com, clg@kaod.org, fred.konrad@greensocs.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: KONRAD Frederic This prints the clock attached to a DeviceState when using "info qtree" mon= itor command. For example: bus: main-system-bus type System dev: xlnx.zynqmp_crf, id "" gpio-out "sysbus-irq" 1 gpio-out "RST_A9" 4 qemu-clk "dbg_trace" 0.0 qemu-clk "vpll_to_lpd" 12500000.0 qemu-clk "dp_stc_ref" 0.0 qemu-clk "dpll_to_lpd" 12500000.0 qemu-clk "acpu_clk" 0.0 qemu-clk "pcie_ref" 0.0 qemu-clk "topsw_main" 0.0 qemu-clk "topsw_lsbus" 0.0 qemu-clk "dp_audio_ref" 0.0 qemu-clk "sata_ref" 0.0 qemu-clk "dp_video_ref" 1428571.4 qemu-clk "vpll_clk" 50000000.0 qemu-clk "apll_to_lpd" 12500000.0 qemu-clk "dpll_clk" 50000000.0 qemu-clk "gpu_ref" 0.0 qemu-clk "aux_refclk" 0.0 qemu-clk "video_clk" 27000000.0 qemu-clk "gdma_ref" 0.0 qemu-clk "gt_crx_ref_clk" 0.0 qemu-clk "dbg_fdp" 0.0 qemu-clk "apll_clk" 50000000.0 qemu-clk "pss_alt_ref_clk" 0.0 qemu-clk "ddr" 0.0 qemu-clk "pss_ref_clk" 50000000.0 qemu-clk "dpdma_ref" 0.0 qemu-clk "dbg_tstmp" 0.0 mmio 00000000fd1a0000/000000000000010c Signed-off-by: KONRAD Frederic --- include/qemu/qemu-clock.h | 9 +++++++++ qdev-monitor.c | 2 ++ qemu-clock.c | 28 ++++++++++++++++++++++++++++ 3 files changed, 39 insertions(+) diff --git a/include/qemu/qemu-clock.h b/include/qemu/qemu-clock.h index 1c57df4..8f0daa8 100644 --- a/include/qemu/qemu-clock.h +++ b/include/qemu/qemu-clock.h @@ -149,4 +149,13 @@ void qemu_clk_set_callback(QEMUClock *clk, QEMUClkRateUpdateCallback *cb, void *opaque); =20 +/** + * qemu_clk_print: + * @dev: the device for which the clock need to be printed. + * + * Print the clock information for a given device. + * + */ +void qemu_clk_print(Monitor *mon, DeviceState *dev, int indent); + #endif /* QEMU_CLOCK_H */ diff --git a/qdev-monitor.c b/qdev-monitor.c index 549f45f..02f8255 100644 --- a/qdev-monitor.c +++ b/qdev-monitor.c @@ -30,6 +30,7 @@ #include "qemu/help_option.h" #include "sysemu/block-backend.h" #include "migration/migration.h" +#include "qemu/qemu-clock.h" =20 /* * Aliases were a bad idea from the start. Let's keep them @@ -699,6 +700,7 @@ static void qdev_print(Monitor *mon, DeviceState *dev, = int indent) ngl->num_out); } } + qemu_clk_print(mon, dev, indent); class =3D object_get_class(OBJECT(dev)); do { qdev_print_props(mon, dev, DEVICE_CLASS(class)->props, indent); diff --git a/qemu-clock.c b/qemu-clock.c index 8f342f6..d5dd928 100644 --- a/qemu-clock.c +++ b/qemu-clock.c @@ -27,6 +27,7 @@ #include "qemu/log.h" #include "qapi/error.h" #include "hw/qdev-core.h" +#include "monitor/monitor.h" =20 #ifndef DEBUG_QEMU_CLOCK #define DEBUG_QEMU_CLOCK 0 @@ -134,6 +135,33 @@ QEMUClock *qemu_clk_device_get_clock(DeviceState *dev,= const char *name) return QEMU_CLOCK(clk); } =20 +struct print_opaque { + Monitor *mon; + int indent; +}; + +static int qemu_clk_print_rec(Object *obj, void *opaque) +{ + QEMUClock *clk =3D (QEMUClock *)(object_dynamic_cast(obj, TYPE_CLOCK)); + struct print_opaque *po =3D opaque; + + if (clk) { + monitor_printf(po->mon, "%*s" "qemu-clk \"%s\" %" PRIu64 "\n", + po->indent, " ", clk->name, clk->rate); + } + + return 0; +} + +void qemu_clk_print(Monitor *mon, DeviceState *dev, int indent) +{ + struct print_opaque po; + + po.indent =3D indent; + po.mon =3D mon; + object_child_foreach(OBJECT(dev), qemu_clk_print_rec, &po); +} + static const TypeInfo qemu_clk_info =3D { .name =3D TYPE_CLOCK, .parent =3D TYPE_OBJECT, --=20 1.8.3.1 From nobody Mon May 20 02:35:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 148827634369622.109818257337224; Tue, 28 Feb 2017 02:05:43 -0800 (PST) Received: from localhost ([::1]:59855 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cief8-00084v-A5 for importer@patchew.org; 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Tue, 28 Feb 2017 11:03:32 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1488276213; bh=wvVpIGEINmH4uvSZQEAA/AgLWj0FETGispOsHvJiqd8=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=oDEYS596o+BibGaPrU52XkdTiGzpwdTN4tFovMEYjvSwYbtbmdsaPd1VAt6uDmCzL tmZ8bNWDAeTU89gCkNLiq7EwL5wIUFDuq8IwIILIw4qnPykYOiRAqAJZFrK45kIpRj FndR655aFhavtLHuQdenqWVkyzmo8US/Qb4uSQ4Q= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1488276212; bh=wvVpIGEINmH4uvSZQEAA/AgLWj0FETGispOsHvJiqd8=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=5DeI2Uh+x2s0bcyur+HFlx+qKl4qFGY6I6cWpVrlXBkhYG5PE8A/o04r4FFK+U3AP TPBhz0uPShkTyQw8ZCH17VNdVxoMXTGAp4rUb+k0kFaj5fPT3JOQgJTZM/WF1XDA4t YxCOmtccKas0houjeYyO9Uu1kpdZJreWXHz551tI= From: fred.konrad@greensocs.com To: qemu-devel@nongnu.org Date: Tue, 28 Feb 2017 11:03:01 +0100 Message-Id: <1488276185-31168-7-git-send-email-fred.konrad@greensocs.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1488276185-31168-1-git-send-email-fred.konrad@greensocs.com> References: <1488276185-31168-1-git-send-email-fred.konrad@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v3 06/10] docs: add qemu-clock documentation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, mark.burton@greensocs.com, alistair.francis@xilinx.com, clg@kaod.org, fred.konrad@greensocs.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: KONRAD Frederic This adds the qemu-clock documentation. Signed-off-by: KONRAD Frederic V1 -> V2: * Fixed in accordance with the changes in the previous patches. --- docs/clock.txt | 278 +++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 278 insertions(+) create mode 100644 docs/clock.txt diff --git a/docs/clock.txt b/docs/clock.txt new file mode 100644 index 0000000..010ae50 --- /dev/null +++ b/docs/clock.txt @@ -0,0 +1,278 @@ + +What is a QEMU_CLOCK +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +A QEMU_CLOCK is a QOM Object developed for the purpose of modeling a clock= tree +with QEMU. + +It only simulates the clock by keeping a copy of the current frequency and +doesn't model the signal itself such as pin toggle or duty cycle. + +It allows to model the impact of badly configured PLL, clock source select= ion +or disabled clock on the models. + +Binding the clock together to create a tree +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +In order to create a clock tree with QEMU_CLOCK two or more clock must be = bound +together. Let's say there are two clocks clk_a and clk_b: +Using qemu_clk_bind(clk_a, clk_b) will bind clk_a and clk_b. + +Binding two qemu-clk together creates a unidirectional link which means th= at +changing the rate of clk_a will propagate to clk_b and not the opposite. +The binding process automatically refreshes clk_b rate. + +Clock can be bound and unbound during execution for modeling eg: a clock +selector. + +A clock can drive more than one other clock. eg with this code: +qemu_clk_bind(clk_a, clk_b); +qemu_clk_bind(clk_a, clk_c); + +A clock rate change one clk_a will propagate to clk_b and clk_c. + +Implementing a callback on a rate change +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The function prototype is the following: +typedef uint64_t QEMUClkRateUpdateCallback(void *opaque, uint64_t rate); + +It's main goal is to modify the rate before it's passed to the next clocks= in +the tree. + +eg: for a 4x PLL the function will be: +uint64_t qemu_clk_rate_change_cb(void *opaque, uint64_t rate) +{ + return 4 * rate; +} + +To set the callback for the clock: +void qemu_clk_set_callback(qemu_clk clk, QEMUClkRateUpdateCallback *cb, + void *opaque); +can be called. + +The rate update process +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The rate update happen in this way: +When a model wants to update a clock frequency (eg: based on a register ch= ange +or something similar) it will call qemu_clk_update_rate(..) on the clock: + * The callback associated to the clock is called with the new rate. + * qemu_clk_update_rate(..) is then called on all bound clocks with the v= alue + returned by the callback. + +NOTE: When no callback is attached, the clock qemu_clk_update_rate(..) is = called +on the next clock in the tree with the rate unmodified. + +Adding a QEMU_CLOCK to a DeviceState +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Adding a qemu-clk to a DeviceState is required to be able to get the clock +outside the model through qemu_clk_device_get_clock(..). + +It is also required to be able to print the clock and its rate with info q= tree. +For example: + + type System + dev: xlnx.zynqmp_crf, id "" + gpio-out "sysbus-irq" 1 + gpio-out "RST_A9" 4 + qemu-clk "dbg_trace" 0 + qemu-clk "vpll_to_lpd" 625000000 + qemu-clk "dp_stc_ref" 0 + qemu-clk "dpll_to_lpd" 12500000 + qemu-clk "acpu_clk" 0 + qemu-clk "pcie_ref" 0 + qemu-clk "topsw_main" 0 + qemu-clk "topsw_lsbus" 0 + qemu-clk "dp_audio_ref" 0 + qemu-clk "sata_ref" 0 + qemu-clk "dp_video_ref" 71428568 + qemu-clk "vpll_clk" 2500000000 + qemu-clk "apll_to_lpd" 12500000 + qemu-clk "dpll_clk" 50000000 + qemu-clk "gpu_ref" 0 + qemu-clk "aux_refclk" 0 + qemu-clk "video_clk" 27000000 + qemu-clk "gdma_ref" 0 + qemu-clk "gt_crx_ref_clk" 0 + qemu-clk "dbg_fdp" 0 + qemu-clk "apll_clk" 50000000 + qemu-clk "pss_alt_ref_clk" 0 + qemu-clk "ddr" 0 + qemu-clk "pss_ref_clk" 50000000 + qemu-clk "dpdma_ref" 0 + qemu-clk "dbg_tstmp" 0 + mmio 00000000fd1a0000/000000000000010c + +This way a DeviceState can have multiple clock input or output. + +Examples +=3D=3D=3D=3D=3D=3D=3D=3D + +Those are the different way of using the QEMUClock object. + +Modelling a fixed clock generator +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D + +Here is a brief example of a device acting as a clock source: + +typedef struct { + DeviceState parent_obj; + + uint32_t rate; + QEMUClock out; +} FixedClock; + +During the initialization the device must initialize its clock object: + +static void fixed_clock_instance_init(Object *obj) +{ + FixedClock *s =3D FIXED_CLOCK(obj); + + object_initialize(&s->out, sizeof(s->out), TYPE_CLOCK); + qemu_clk_device_add_clock(DEVICE(obj), &s->out, "clk_out"); +} + +As the device acts as a clock source it must refresh the clock tree during= the +realize phase: + +static void fixed_clock_realizefn(DeviceState *dev, Error **errp) +{ + FixedClock *s =3D FIXED_CLOCK(dev); + + qemu_clk_update_rate(&s->out, s->rate); +} + +This means that the clock tree must be finished before realize is called o= n the +fixed clock. + +Modelling a clock user device +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D + +Here is a brief example of a clock user: + +typedef struct { + DeviceState parent_obj; + + QEMUClock in; +} ClockUser; + +As before the clock must be initialized through the device initialize func= tion: + +static void clock_user_instance_init(Object *obj) +{ + ClockUser *s =3D CLOCK_USER(obj); + + object_initialize(&s->in, sizeof(s->in), TYPE_CLOCK); + qemu_clk_device_add_clock(DEVICE(obj), &s->in, "clk_in"); + /* + * Call on_rate_change_cb when something change on clk_in. + */ + qemu_clk_set_callback(s->in, on_rate_change_cb, obj); +} + +The callback is in this case used as a notifier when the clock tree which +sources the device change: + +static uint64_t on_rate_change_cb(void *opaque, uint64_t input_rate) +{ + printf("the new rate is %ld\n", input_rate); + + /* The return is ignored if nothing is bound to clk_in. */ + return input_rate; +} + +Modelling a clock multiplier +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D + +Here is a brief example of a device acting as a clock modifier: + +typedef struct { + DeviceState parent_obj; + + uint32_t rate; + QEMUClock out; + QEMUClock in; +} ClockMultiplier; + +As before the clocks must be initialized through the device initialize fun= ction +but they must be bound together so a change on the input will propagate on= the +output: + +static void clock_multiplier_instance_init(Object *obj) +{ + ClockMultiplier *s =3D CLOCK_MULTIPLIER(obj); + + object_initialize(&s->out, sizeof(s->out), TYPE_CLOCK); + object_initialize(&s->in, sizeof(s->in), TYPE_CLOCK); + + qemu_clk_device_add_clock(DEVICE(obj), &s->in, "clk_in"); + qemu_clk_device_add_clock(DEVICE(obj), &s->out, "clk_out"); + /* + * Propagate the change from in to out, this can be done dynamically d= uring + * the simulation but we need to do the initial binding here to get the + * initial refresh happening when the realize function is called on the + * fixed clock. + */ + qemu_clk_bind(s->in, s->out); + /* + * But before propagating the rate modify it with multiplier_cb. + */ + qemu_clk_set_callback(s->out, multiplier_cb, obj); +} + +In this example when clk_in changes it will trigger a change on clk_out an= d this +callback can modify the rate of clk_out (the return value of this callback) +accordingly to clk_in rate (input_rate). + +static uint64_t multiplier_cb(void *opaque, uint64_t input_rate) +{ + return input_rate * 4; +} + +This device doesn't refresh the clock tree as it will be done by the clock= tree +source. + +Modelling a clock selector +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D + +Here is a brief example of a device acting as a device which alter the clo= ck +topology such as a clock selector: + +typedef struct { + DeviceState parent_obj; + + QEMUClock out; + QEMUClock in_a; + QEMUClock in_b; +} ClockSelector; + +The clocks must be initialized through the device initialize function but = they +must be bound together like they will be when the device is reset so a cha= nge on +the input during the realize of the fixed clock will propagate to the outp= ut: + +static void clock_selector_instance_init(Object *obj) +{ + ClockSelector *s =3D CLOCK_SELECTOR(obj); + + object_initialize(&s->out, sizeof(s->out), TYPE_CLOCK); + object_initialize(&s->in_a, sizeof(s->in_a), TYPE_CLOCK); + object_initialize(&s->in_b, sizeof(s->in_b), TYPE_CLOCK); + + qemu_clk_device_add_clock(DEVICE(obj), &s->in_a, "clk_in_a"); + qemu_clk_device_add_clock(DEVICE(obj), &s->in_b, "clk_in_b"); + qemu_clk_device_add_clock(DEVICE(obj), &s->out, "clk_out"); + + /* Assuming at the reset that the input_a is connected to output. */ + qemu_clk_bind(s->in_a, s->out); +} + +/* This is called for example by a register change or something like that = */ +void update_topology(ClockSelector *s) +{ + /* Unbind the old clock */ + qemu_clk_unbind(s->in_a, s->out); + /* Bind the new one, the rate is automatically refreshed. */ + qemu_clk_bind(s->in_b, s->out); +} --=20 1.8.3.1 From nobody Mon May 20 02:35:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1488276610847501.2555768046949; Tue, 28 Feb 2017 02:10:10 -0800 (PST) Received: from localhost ([::1]:59877 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ciejR-0003Ug-Ie for importer@patchew.org; Tue, 28 Feb 2017 05:10:09 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58955) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cied7-0006oz-5M for qemu-devel@nongnu.org; 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charset="utf-8" From: KONRAD Frederic This is a fixed clock device. It justs behave as an empty device with a parametrable output rate. Signed-off-by: KONRAD Frederic --- hw/misc/Makefile.objs | 1 + hw/misc/fixed-clock.c | 88 +++++++++++++++++++++++++++++++++++++++= ++++ include/hw/misc/fixed-clock.h | 30 +++++++++++++++ 3 files changed, 119 insertions(+) create mode 100644 hw/misc/fixed-clock.c create mode 100644 include/hw/misc/fixed-clock.h diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index 898e4cc..e9c4dd3 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -55,3 +55,4 @@ obj-$(CONFIG_EDU) +=3D edu.o obj-$(CONFIG_HYPERV_TESTDEV) +=3D hyperv_testdev.o obj-$(CONFIG_AUX) +=3D auxbus.o obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_scu.o aspeed_sdmc.o +obj-y +=3D fixed-clock.o diff --git a/hw/misc/fixed-clock.c b/hw/misc/fixed-clock.c new file mode 100644 index 0000000..b5af24d --- /dev/null +++ b/hw/misc/fixed-clock.c @@ -0,0 +1,88 @@ +/* + * Fixed clock + * + * Copyright (C) 2016 : GreenSocs Ltd + * http://www.greensocs.com/ , email: info@greensocs.com + * + * Frederic Konrad + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + * + */ + +#include "qemu/osdep.h" +#include "hw/qdev.h" +#include "hw/misc/fixed-clock.h" +#include "qemu/qemu-clock.h" +#include "qapi/error.h" + +#ifndef DEBUG_FIXED_CLOCK +#define DEBUG_FIXED_CLOCK 0 +#endif + +#define DPRINTF(fmt, ...) do { = \ + if (DEBUG_FIXED_CLOCK) { = \ + qemu_log(__FILE__": " fmt , ## __VA_ARGS__); = \ + } = \ +} while (0); + +typedef struct { + DeviceState parent_obj; + + uint32_t rate; + QEMUClock out; +} FixedClock; + +static Property fixed_clock_properties[] =3D { + DEFINE_PROP_UINT32("rate", FixedClock, rate, 0), + DEFINE_PROP_END_OF_LIST() +}; + +static void fixed_clock_realizefn(DeviceState *dev, Error **errp) +{ + FixedClock *s =3D FIXED_CLOCK(dev); + + qemu_clk_update_rate(&s->out, s->rate); +} + +static void fixed_clock_instance_init(Object *obj) +{ + FixedClock *s =3D FIXED_CLOCK(obj); + + object_initialize(&s->out, sizeof(s->out), TYPE_CLOCK); + qemu_clk_device_add_clock(DEVICE(obj), &s->out, "clk_out"); +} + +static void fixed_clock_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D fixed_clock_realizefn; + dc->props =3D fixed_clock_properties; +} + +static const TypeInfo fixed_clock_info =3D { + .name =3D TYPE_FIXED_CLOCK, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(FixedClock), + .instance_init =3D fixed_clock_instance_init, + .class_init =3D fixed_clock_class_init, +}; + +static void fixed_clock_register_types(void) +{ + type_register_static(&fixed_clock_info); +} + +type_init(fixed_clock_register_types); diff --git a/include/hw/misc/fixed-clock.h b/include/hw/misc/fixed-clock.h new file mode 100644 index 0000000..1376444 --- /dev/null +++ b/include/hw/misc/fixed-clock.h @@ -0,0 +1,30 @@ +/* + * Fixed clock + * + * Copyright (C) 2016 : GreenSocs Ltd + * http://www.greensocs.com/ , email: info@greensocs.com + * + * Frederic Konrad + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + * + */ + +#ifndef FIXED_CLOCK_H +#define FIXED_CLOCK_H + +#define TYPE_FIXED_CLOCK "fixed-clock" +#define FIXED_CLOCK(obj) OBJECT_CHECK(FixedClock, (obj), TYPE_FIXED_CLOCK) + +#endif /* FIXED_CLOCK_H */ --=20 1.8.3.1 From nobody Mon May 20 02:35:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1488276624013656.7995586959195; Tue, 28 Feb 2017 02:10:24 -0800 (PST) Received: from localhost ([::1]:59879 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cieje-0003f0-Ki for importer@patchew.org; Tue, 28 Feb 2017 05:10:22 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59021) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ciedF-0006ya-UF for qemu-devel@nongnu.org; Tue, 28 Feb 2017 05:03:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cied7-0004AU-D6 for qemu-devel@nongnu.org; Tue, 28 Feb 2017 05:03:45 -0500 Received: from greensocs.com ([193.104.36.180]:38453) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cied6-00049k-PD for qemu-devel@nongnu.org; Tue, 28 Feb 2017 05:03:37 -0500 Received: from localhost (localhost [127.0.0.1]) by greensocs.com (Postfix) with ESMTP id 1296A4251B8; Tue, 28 Feb 2017 11:03:36 +0100 (CET) Received: from greensocs.com ([127.0.0.1]) by localhost (gs-01.greensocs.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id qmodSafSuxig; Tue, 28 Feb 2017 11:03:34 +0100 (CET) Received: from corsair.home (bd231-7-88-127-3-24.fbx.proxad.net [88.127.3.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: fred.konrad@greensocs.com) by greensocs.com (Postfix) with ESMTPSA id CEE5440CA6C; Tue, 28 Feb 2017 11:03:33 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1488276216; bh=XnZyEhqrAERDvDk3rxjSmz2tz1nWYx8YZ9xMpx4LQ3Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=y7+kKEG9u+gE10EuFVHg3okBRgKyDVPf6zKerNSR6DnThD3XRsMmtViNmszMOGGOH DGjRXBK1ZcDjDg9kqUNHozA/0iYk4Brc2QzaQcT02Y+4tiv/WBnOs/FgKOVZDf9aAC He+lTs2xj6pbYLsc+WaTjcC+JwgFg6RLi+fvtk/U= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1488276214; bh=XnZyEhqrAERDvDk3rxjSmz2tz1nWYx8YZ9xMpx4LQ3Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=2bKY1p1pbAPIBEtwsqZAh+BTOWDzCqkldXrbbnSPNX15yEvGCL5Z6Sqw2NtIupR7f DJpvoA0Op5V3OC8Z4PEoB6oz4mNmvdHzrFliiduQ79Z+yiiv+JQLO7C561SZ3NNGt7 l+z5n7U2qgxrxLT3Ax7TihAgOS/R5wcA3t54fr88= From: fred.konrad@greensocs.com To: qemu-devel@nongnu.org Date: Tue, 28 Feb 2017 11:03:03 +0100 Message-Id: <1488276185-31168-9-git-send-email-fred.konrad@greensocs.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1488276185-31168-1-git-send-email-fred.konrad@greensocs.com> References: <1488276185-31168-1-git-send-email-fred.konrad@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v3 08/10] introduce zynqmp_crf X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, mark.burton@greensocs.com, alistair.francis@xilinx.com, clg@kaod.org, fred.konrad@greensocs.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: KONRAD Frederic This introduce Xilinx zynqmp-crf. It is extracted from the qemu xilinx tree (02d2f0203dd489ed30d9c8d90c14a52c= 57332b25) and is used as an example for the clock framework. --- hw/misc/Makefile.objs | 1 + hw/misc/xilinx_zynqmp_crf.c | 968 ++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 969 insertions(+) create mode 100644 hw/misc/xilinx_zynqmp_crf.c diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index e9c4dd3..92cdb40 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -45,6 +45,7 @@ obj-$(CONFIG_RASPI) +=3D bcm2835_property.o obj-$(CONFIG_SLAVIO) +=3D slavio_misc.o obj-$(CONFIG_ZYNQ) +=3D zynq_slcr.o obj-$(CONFIG_ZYNQ) +=3D zynq-xadc.o +obj-$(CONFIG_ZYNQ) +=3D xilinx_zynqmp_crf.o obj-$(CONFIG_STM32F2XX_SYSCFG) +=3D stm32f2xx_syscfg.o obj-$(CONFIG_MIPS_CPS) +=3D mips_cmgcr.o obj-$(CONFIG_MIPS_CPS) +=3D mips_cpc.o diff --git a/hw/misc/xilinx_zynqmp_crf.c b/hw/misc/xilinx_zynqmp_crf.c new file mode 100644 index 0000000..fa3a9cb --- /dev/null +++ b/hw/misc/xilinx_zynqmp_crf.c @@ -0,0 +1,968 @@ +/* + * QEMU model of the CRF_APB APB control registers for clock controller. T= he + * RST_ctrl_fpd will be added to this as well + * + * Copyright (c) 2014 Xilinx Inc. + * + * Autogenerated by xregqemu.py 2014-01-22. + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/register.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "qemu/qemu-clock.h" + +#ifndef XILINX_CRF_APB_ERR_DEBUG +#define XILINX_CRF_APB_ERR_DEBUG 0 +#endif + +#define TYPE_XILINX_CRF_APB "xlnx.zynqmp_crf" + +#define XILINX_CRF_APB(obj) \ + OBJECT_CHECK(CRF_APB, (obj), TYPE_XILINX_CRF_APB) + +REG32(ERR_CTRL, 0x0) + FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1) +REG32(IR_STATUS, 0x4) + FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1) +REG32(IR_MASK, 0x8) + FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1) +REG32(IR_ENABLE, 0xc) + FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1) +REG32(IR_DISABLE, 0x10) + FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1) +REG32(CRF_ECO, 0x18) +REG32(APLL_CTRL, 0x20) + FIELD(APLL_CTRL, POST_SRC, 24, 3) + FIELD(APLL_CTRL, PRE_SRC, 20, 3) + FIELD(APLL_CTRL, CLKOUTDIV, 17, 1) + FIELD(APLL_CTRL, DIV2, 16, 1) + FIELD(APLL_CTRL, FBDIV, 8, 7) + FIELD(APLL_CTRL, BYPASS, 3, 1) + FIELD(APLL_CTRL, RESET, 0, 1) +REG32(APLL_CFG, 0x24) + FIELD(APLL_CFG, LOCK_DLY, 25, 7) + FIELD(APLL_CFG, LOCK_CNT, 13, 10) + FIELD(APLL_CFG, LFHF, 10, 2) + FIELD(APLL_CFG, CP, 5, 4) + FIELD(APLL_CFG, RES, 0, 4) +REG32(APLL_FRAC_CFG, 0x28) + FIELD(APLL_FRAC_CFG, ENABLED, 31, 1) + FIELD(APLL_FRAC_CFG, SEED, 22, 3) + FIELD(APLL_FRAC_CFG, ALGRTHM, 19, 1) + FIELD(APLL_FRAC_CFG, ORDER, 18, 1) + FIELD(APLL_FRAC_CFG, DATA, 0, 16) +REG32(DPLL_CTRL, 0x2c) + FIELD(DPLL_CTRL, POST_SRC, 24, 3) + FIELD(DPLL_CTRL, PRE_SRC, 20, 3) + FIELD(DPLL_CTRL, CLKOUTDIV, 17, 1) + FIELD(DPLL_CTRL, DIV2, 16, 1) + FIELD(DPLL_CTRL, FBDIV, 8, 7) + FIELD(DPLL_CTRL, BYPASS, 3, 1) + FIELD(DPLL_CTRL, RESET, 0, 1) +REG32(DPLL_CFG, 0x30) + FIELD(DPLL_CFG, LOCK_DLY, 25, 7) + FIELD(DPLL_CFG, LOCK_CNT, 13, 10) + FIELD(DPLL_CFG, LFHF, 10, 2) + FIELD(DPLL_CFG, CP, 5, 4) + FIELD(DPLL_CFG, RES, 0, 4) +REG32(DPLL_FRAC_CFG, 0x34) + FIELD(DPLL_FRAC_CFG, ENABLED, 31, 1) + FIELD(DPLL_FRAC_CFG, SEED, 22, 3) + FIELD(DPLL_FRAC_CFG, ALGRTHM, 19, 1) + FIELD(DPLL_FRAC_CFG, ORDER, 18, 1) + FIELD(DPLL_FRAC_CFG, DATA, 0, 16) +REG32(VPLL_CTRL, 0x38) + FIELD(VPLL_CTRL, POST_SRC, 24, 3) + FIELD(VPLL_CTRL, PRE_SRC, 20, 3) + FIELD(VPLL_CTRL, CLKOUTDIV, 17, 1) + FIELD(VPLL_CTRL, DIV2, 16, 1) + FIELD(VPLL_CTRL, FBDIV, 8, 7) + FIELD(VPLL_CTRL, BYPASS, 3, 1) + FIELD(VPLL_CTRL, RESET, 0, 1) +REG32(VPLL_CFG, 0x3c) + FIELD(VPLL_CFG, LOCK_DLY, 25, 7) + FIELD(VPLL_CFG, LOCK_CNT, 13, 10) + FIELD(VPLL_CFG, LFHF, 10, 2) + FIELD(VPLL_CFG, CP, 5, 4) + FIELD(VPLL_CFG, RES, 0, 4) +REG32(VPLL_FRAC_CFG, 0x40) + FIELD(VPLL_FRAC_CFG, ENABLED, 31, 1) + FIELD(VPLL_FRAC_CFG, SEED, 22, 3) + FIELD(VPLL_FRAC_CFG, ALGRTHM, 19, 1) + FIELD(VPLL_FRAC_CFG, ORDER, 18, 1) + FIELD(VPLL_FRAC_CFG, DATA, 0, 16) +REG32(PLL_STATUS, 0x44) + FIELD(PLL_STATUS, VPLL_STABLE, 5, 1) + FIELD(PLL_STATUS, DPLL_STABLE, 4, 1) + FIELD(PLL_STATUS, APLL_STABLE, 3, 1) + FIELD(PLL_STATUS, VPLL_LOCK, 2, 1) + FIELD(PLL_STATUS, DPLL_LOCK, 1, 1) + FIELD(PLL_STATUS, APLL_LOCK, 0, 1) +REG32(APLL_TO_LPD_CTRL, 0x48) + FIELD(APLL_TO_LPD_CTRL, DIVISOR0, 8, 6) +REG32(DPLL_TO_LPD_CTRL, 0x4c) + FIELD(DPLL_TO_LPD_CTRL, DIVISOR0, 8, 6) +REG32(VPLL_TO_LPD_CTRL, 0x50) + FIELD(VPLL_TO_LPD_CTRL, DIVISOR0, 8, 6) +REG32(CPU_A9_CTRL, 0x60) + FIELD(CPU_A9_CTRL, A9CLKSTOP, 26, 2) + FIELD(CPU_A9_CTRL, CLKACT_HALF, 25, 1) + FIELD(CPU_A9_CTRL, CLKACT_FULL, 24, 1) + FIELD(CPU_A9_CTRL, DIVISOR0, 8, 6) + FIELD(CPU_A9_CTRL, SRCSEL, 0, 3) +REG32(DBG_TRACE_CTRL, 0x64) + FIELD(DBG_TRACE_CTRL, CLKACT, 24, 1) + FIELD(DBG_TRACE_CTRL, DIVISOR0, 8, 6) + FIELD(DBG_TRACE_CTRL, SRCSEL, 0, 3) +REG32(DBG_FPD_CTRL, 0x68) + FIELD(DBG_FPD_CTRL, CLKACT, 24, 1) + FIELD(DBG_FPD_CTRL, DIVISOR0, 8, 6) + FIELD(DBG_FPD_CTRL, SRCSEL, 0, 3) +REG32(DP_VIDEO_REF_CTRL, 0x70) + FIELD(DP_VIDEO_REF_CTRL, CLKACT, 24, 1) + FIELD(DP_VIDEO_REF_CTRL, DIVISOR0, 8, 6) + FIELD(DP_VIDEO_REF_CTRL, SRCSEL, 0, 3) +REG32(DP_AUDIO_REF_CTRL, 0x74) + FIELD(DP_AUDIO_REF_CTRL, CLKACT, 24, 1) + FIELD(DP_AUDIO_REF_CTRL, DIVISOR0, 8, 6) + FIELD(DP_AUDIO_REF_CTRL, SRCSEL, 0, 3) +REG32(DP_LINK_REF_CTRL, 0x78) + FIELD(DP_LINK_REF_CTRL, CLKACT, 24, 1) + FIELD(DP_LINK_REF_CTRL, DIVISOR1, 16, 6) + FIELD(DP_LINK_REF_CTRL, DIVISOR0, 8, 6) + FIELD(DP_LINK_REF_CTRL, SRCSEL, 0, 3) +REG32(DP_STC_REF_CTRL, 0x7c) + FIELD(DP_STC_REF_CTRL, CLKACT, 24, 1) + FIELD(DP_STC_REF_CTRL, DIVISOR1, 16, 6) + FIELD(DP_STC_REF_CTRL, DIVISOR0, 8, 6) + FIELD(DP_STC_REF_CTRL, SRCSEL, 0, 3) +REG32(DDR_CTRL, 0x80) + FIELD(DDR_CTRL, CLKACT, 24, 1) + FIELD(DDR_CTRL, DIVISOR0, 8, 6) + FIELD(DDR_CTRL, SRCSEL, 0, 3) +REG32(GPU_REF_CTRL, 0x84) + FIELD(GPU_REF_CTRL, PP1_CLKACT, 26, 1) + FIELD(GPU_REF_CTRL, PP0_CLKACT, 25, 1) + FIELD(GPU_REF_CTRL, CLKACT, 24, 1) + FIELD(GPU_REF_CTRL, DIVISOR0, 8, 6) + FIELD(GPU_REF_CTRL, SRCSEL, 0, 3) +REG32(AFI0_REF_CTRL, 0x88) + FIELD(AFI0_REF_CTRL, CLKACT, 24, 1) + FIELD(AFI0_REF_CTRL, DIVISOR0, 8, 6) + FIELD(AFI0_REF_CTRL, SRCSEL, 0, 3) +REG32(AFI1_REF_CTRL, 0x8c) + FIELD(AFI1_REF_CTRL, CLKACT, 24, 1) + FIELD(AFI1_REF_CTRL, DIVISOR0, 8, 6) + FIELD(AFI1_REF_CTRL, SRCSEL, 0, 3) +REG32(AFI2_REF_CTRL, 0x90) + FIELD(AFI2_REF_CTRL, CLKACT, 24, 1) + FIELD(AFI2_REF_CTRL, DIVISOR0, 8, 6) + FIELD(AFI2_REF_CTRL, SRCSEL, 0, 3) +REG32(AFI3_REF_CTRL, 0x94) + FIELD(AFI3_REF_CTRL, CLKACT, 24, 1) + FIELD(AFI3_REF_CTRL, DIVISOR0, 8, 6) + FIELD(AFI3_REF_CTRL, SRCSEL, 0, 3) +REG32(AFI4_REF_CTRL, 0x98) + FIELD(AFI4_REF_CTRL, CLKACT, 24, 1) + FIELD(AFI4_REF_CTRL, DIVISOR0, 8, 6) + FIELD(AFI4_REF_CTRL, SRCSEL, 0, 3) +REG32(AFI5_REF_CTRL, 0x9c) + FIELD(AFI5_REF_CTRL, CLKACT, 24, 1) + FIELD(AFI5_REF_CTRL, DIVISOR0, 8, 6) + FIELD(AFI5_REF_CTRL, SRCSEL, 0, 3) +REG32(SATA_REF_CTRL, 0xa0) + FIELD(SATA_REF_CTRL, CLKACT, 24, 1) + FIELD(SATA_REF_CTRL, DIVISOR0, 8, 6) + FIELD(SATA_REF_CTRL, SRCSEL, 0, 3) +REG32(PCIE_REF_CTRL, 0xb4) + FIELD(PCIE_REF_CTRL, CLKACT, 24, 1) + FIELD(PCIE_REF_CTRL, DIVISOR0, 8, 6) + FIELD(PCIE_REF_CTRL, SRCSEL, 0, 3) +REG32(GDMA_REF_CTRL, 0xb8) + FIELD(GDMA_REF_CTRL, CLKACT, 24, 1) + FIELD(GDMA_REF_CTRL, DIVISOR0, 8, 6) + FIELD(GDMA_REF_CTRL, SRCSEL, 0, 3) +REG32(DPDMA_REF_CTRL, 0xbc) + FIELD(DPDMA_REF_CTRL, CLKACT, 24, 1) + FIELD(DPDMA_REF_CTRL, DIVISOR0, 8, 6) + FIELD(DPDMA_REF_CTRL, SRCSEL, 0, 3) +REG32(TOPSW_MAIN_CTRL, 0xc0) + FIELD(TOPSW_MAIN_CTRL, CLKACT, 24, 1) + FIELD(TOPSW_MAIN_CTRL, DIVISOR0, 8, 6) + FIELD(TOPSW_MAIN_CTRL, SRCSEL, 0, 3) +REG32(TOPSW_LSBUS_CTRL, 0xc4) + FIELD(TOPSW_LSBUS_CTRL, CLKACT, 24, 1) + FIELD(TOPSW_LSBUS_CTRL, DIVISOR0, 8, 6) + FIELD(TOPSW_LSBUS_CTRL, SRCSEL, 0, 3) +REG32(GTGREF0_REF_CTRL, 0xc8) + FIELD(GTGREF0_REF_CTRL, CLKACT, 24, 1) + FIELD(GTGREF0_REF_CTRL, DIVISOR0, 8, 6) + FIELD(GTGREF0_REF_CTRL, SRCSEL, 0, 3) +REG32(GTGREF1_REF_CTRL, 0xcc) + FIELD(GTGREF1_REF_CTRL, CLKACT, 24, 1) + FIELD(GTGREF1_REF_CTRL, DIVISOR0, 8, 6) + FIELD(GTGREF1_REF_CTRL, SRCSEL, 0, 3) +REG32(DFT300_REF_CTRL, 0xd0) + FIELD(DFT300_REF_CTRL, CLKACT, 24, 1) + FIELD(DFT300_REF_CTRL, DIVISOR0, 8, 6) + FIELD(DFT300_REF_CTRL, SRCSEL, 0, 3) +REG32(DFT270_REF_CTRL, 0xd4) + FIELD(DFT270_REF_CTRL, CLKACT, 24, 1) + FIELD(DFT270_REF_CTRL, DIVISOR0, 8, 6) + FIELD(DFT270_REF_CTRL, SRCSEL, 0, 3) +REG32(DFT250_REF_CTRL, 0xd8) + FIELD(DFT250_REF_CTRL, CLKACT, 24, 1) + FIELD(DFT250_REF_CTRL, DIVISOR0, 8, 6) + FIELD(DFT250_REF_CTRL, SRCSEL, 0, 3) +REG32(DFT125_REF_CTRL, 0xdc) + FIELD(DFT125_REF_CTRL, CLKACT, 24, 1) + FIELD(DFT125_REF_CTRL, DIVISOR0, 8, 6) + FIELD(DFT125_REF_CTRL, SRCSEL, 0, 3) + +REG32(RST_FPD_TOP, 0x100) + FIELD(RST_FPD_TOP, PCIE_BRDG_RESET, 18, 1) + FIELD(RST_FPD_TOP, PCIE_CTRL_RESET, 17, 1) + FIELD(RST_FPD_TOP, DP_RESET, 16, 1) + FIELD(RST_FPD_TOP, AFI_FM5_RESET, 12, 1) + FIELD(RST_FPD_TOP, AFI_FM4_RESET, 11, 1) + FIELD(RST_FPD_TOP, AFI_FM3_RESET, 10, 1) + FIELD(RST_FPD_TOP, AFI_FM2_RESET, 9, 1) + FIELD(RST_FPD_TOP, AFI_FM1_RESET, 8, 1) + FIELD(RST_FPD_TOP, AFI_FM0_RESET, 7, 1) + FIELD(RST_FPD_TOP, GDMA_RESET, 6, 1) + FIELD(RST_FPD_TOP, GPU_PP1_RESET, 5, 1) + FIELD(RST_FPD_TOP, GPU_PP0_RESET, 4, 1) + FIELD(RST_FPD_TOP, GPU_RESET, 3, 1) + FIELD(RST_FPD_TOP, GT_RESET, 2, 1) + FIELD(RST_FPD_TOP, SATA_RESET, 1, 1) +REG32(RST_FPD_APU, 0x104) + FIELD(RST_FPD_APU, PERI_RESET, 13, 1) + FIELD(RST_FPD_APU, SCU_RESET, 12, 1) + FIELD(RST_FPD_APU, CPU1_AWDT_RESET, 9, 1) + FIELD(RST_FPD_APU, CPU0_AWDT_RESET, 8, 1) + FIELD(RST_FPD_APU, CPU1_CP14_RESET, 5, 1) + FIELD(RST_FPD_APU, CPU0_CP14_RESET, 4, 1) + FIELD(RST_FPD_APU, CPU3_A9_RESET, 3, 1) + FIELD(RST_FPD_APU, CPU2_A9_RESET, 2, 1) + FIELD(RST_FPD_APU, CPU1_A9_RESET, 1, 1) + FIELD(RST_FPD_APU, CPU0_A9_RESET, 0, 1) +REG32(RST_DDR_SS, 0x108) + FIELD(RST_DDR_SS, DDR_RESET, 3, 1) + FIELD(RST_DDR_SS, APM_RESET, 2, 1) + FIELD(RST_DDR_SS, QOS_RESET, 1, 1) + FIELD(RST_DDR_SS, XMPU_RESET, 0, 1) + +#define R_MAX (R_RST_DDR_SS + 1) + +typedef struct CRF_APB { + SysBusDevice parent_obj; + MemoryRegion iomem; + qemu_irq irq_ir; + + uint32_t regs[R_MAX]; + RegisterInfo regs_info[R_MAX]; + + /* input clocks */ + QEMUClock *pss_ref_clk; + QEMUClock *video_clk; + QEMUClock *pss_alt_ref_clk; + QEMUClock *aux_refclk; + QEMUClock *gt_crx_ref_clk; + + /* internal clocks */ + QEMUClock *apll_clk; + QEMUClock *dpll_clk; + QEMUClock *vpll_clk; + + /* output clocks */ + QEMUClock *acpu_clk; + QEMUClock *dbg_trace; + QEMUClock *dbg_fdp; + QEMUClock *dp_video_ref; + QEMUClock *dp_audio_ref; + QEMUClock *dp_stc_ref; + QEMUClock *ddr; + QEMUClock *gpu_ref; + QEMUClock *sata_ref; + QEMUClock *pcie_ref; + QEMUClock *gdma_ref; + QEMUClock *dpdma_ref; + QEMUClock *topsw_main; + QEMUClock *topsw_lsbus; + QEMUClock *dbg_tstmp; + QEMUClock *apll_to_lpd; + QEMUClock *dpll_to_lpd; + QEMUClock *vpll_to_lpd; +} CRF_APB; + +static uint64_t apll_to_lpd_update_rate(void *opaque, uint64_t input_rate); +static uint64_t dpll_to_lpd_update_rate(void *opaque, uint64_t input_rate); +static uint64_t vpll_to_lpd_update_rate(void *opaque, uint64_t input_rate); +static uint64_t apll_update_rate(void *opaque, uint64_t input_rate); +static uint64_t dpll_update_rate(void *opaque, uint64_t input_rate); +static uint64_t vpll_update_rate(void *opaque, uint64_t input_rate); +static uint64_t dp_video_update_rate(void *opaque, uint64_t input_rate); + +/* Clock array */ +ClockInitElement crf_clock[] =3D { + /* input clocks */ + DEVICE_CLOCK(CRF_APB, pss_ref_clk, NULL), + DEVICE_CLOCK(CRF_APB, video_clk, NULL), + DEVICE_CLOCK(CRF_APB, pss_alt_ref_clk, NULL), + DEVICE_CLOCK(CRF_APB, aux_refclk, NULL), + DEVICE_CLOCK(CRF_APB, gt_crx_ref_clk, NULL), + /* internal clocks */ + DEVICE_CLOCK(CRF_APB, apll_clk, apll_update_rate), + DEVICE_CLOCK(CRF_APB, dpll_clk, dpll_update_rate), + DEVICE_CLOCK(CRF_APB, vpll_clk, vpll_update_rate), + /* output clocks */ + DEVICE_CLOCK(CRF_APB, acpu_clk, NULL), + DEVICE_CLOCK(CRF_APB, dbg_trace, NULL), + DEVICE_CLOCK(CRF_APB, dbg_fdp, NULL), + DEVICE_CLOCK(CRF_APB, dp_video_ref, dp_video_update_rate), + DEVICE_CLOCK(CRF_APB, dp_audio_ref, NULL), + DEVICE_CLOCK(CRF_APB, dp_stc_ref, NULL), + DEVICE_CLOCK(CRF_APB, ddr, NULL), + DEVICE_CLOCK(CRF_APB, gpu_ref, NULL), + DEVICE_CLOCK(CRF_APB, sata_ref, NULL), + DEVICE_CLOCK(CRF_APB, pcie_ref, NULL), + DEVICE_CLOCK(CRF_APB, gdma_ref, NULL), + DEVICE_CLOCK(CRF_APB, dpdma_ref, NULL), + DEVICE_CLOCK(CRF_APB, topsw_main, NULL), + DEVICE_CLOCK(CRF_APB, topsw_lsbus, NULL), + DEVICE_CLOCK(CRF_APB, dbg_tstmp, NULL), + DEVICE_CLOCK(CRF_APB, apll_to_lpd, apll_to_lpd_update_rate), + DEVICE_CLOCK(CRF_APB, dpll_to_lpd, dpll_to_lpd_update_rate), + DEVICE_CLOCK(CRF_APB, vpll_to_lpd, vpll_to_lpd_update_rate), + DEVICE_CLOCK_END() +}; + +static const MemoryRegionOps crf_apb_ops =3D { + .read =3D register_read_memory, + .write =3D register_write_memory, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, +}; + +static void ir_update_irq(CRF_APB *s) +{ + bool pending =3D s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK]; + qemu_set_irq(s->irq_ir, pending); +} + +static void ir_status_postw(RegisterInfo *reg, uint64_t val64) +{ + CRF_APB *s =3D XILINX_CRF_APB(reg->opaque); + ir_update_irq(s); +} + +static uint64_t ir_enable_prew(RegisterInfo *reg, uint64_t val64) +{ + CRF_APB *s =3D XILINX_CRF_APB(reg->opaque); + uint32_t val =3D val64; + + s->regs[R_IR_MASK] &=3D ~val; + ir_update_irq(s); + return 0; +} + +static uint64_t ir_disable_prew(RegisterInfo *reg, uint64_t val64) +{ + CRF_APB *s =3D XILINX_CRF_APB(reg->opaque); + uint32_t val =3D val64; + + s->regs[R_IR_MASK] |=3D val; + ir_update_irq(s); + return 0; +} + +enum clk_src { + VIDEO_CLK =3D 4, + PSS_ALT_REF_CLK =3D 5, + AUX_REF_CLK =3D 6, + GT_CRX_REF_CLK =3D 7, + PSS_REF_CLK =3D 0 +}; + +static void apll_to_lpd_postw(RegisterInfo *reg, uint64_t val64) +{ + CRF_APB *s =3D XILINX_CRF_APB(reg->opaque); + + qemu_clk_refresh(s->apll_to_lpd); +} + +static uint64_t apll_to_lpd_update_rate(void *opaque, uint64_t input_rate) +{ + CRF_APB *s =3D XILINX_CRF_APB(opaque); + uint32_t divisor =3D FIELD_EX32(s->regs[R_APLL_TO_LPD_CTRL], + APLL_TO_LPD_CTRL, + DIVISOR0); + + if (!divisor) { + return 0.0f; + } else { + return input_rate / (float)divisor; + } +} + +static void dpll_to_lpd_postw(RegisterInfo *reg, uint64_t val64) +{ + CRF_APB *s =3D XILINX_CRF_APB(reg->opaque); + + qemu_clk_refresh(s->dpll_to_lpd); +} + +static uint64_t dpll_to_lpd_update_rate(void *opaque, uint64_t input_rate) +{ + CRF_APB *s =3D XILINX_CRF_APB(opaque); + uint32_t divisor =3D FIELD_EX32(s->regs[R_DPLL_TO_LPD_CTRL], + DPLL_TO_LPD_CTRL, + DIVISOR0); + + if (!divisor) { + return 0.0f; + } else { + return input_rate / (float)divisor; + } +} + +static void vpll_to_lpd_postw(RegisterInfo *reg, uint64_t val64) +{ + CRF_APB *s =3D XILINX_CRF_APB(reg->opaque); + + qemu_clk_refresh(s->vpll_to_lpd); +} + +static uint64_t vpll_to_lpd_update_rate(void *opaque, uint64_t input_rate) +{ + CRF_APB *s =3D XILINX_CRF_APB(opaque); + uint32_t divisor =3D FIELD_EX32(s->regs[R_VPLL_TO_LPD_CTRL], + VPLL_TO_LPD_CTRL, DIVISOR0); + + if (!divisor) { + return 0; + } else { + return input_rate / (float)divisor; + } +} + +static void apll_ctrl_postw(RegisterInfo *reg, uint64_t val64) +{ + CRF_APB *s =3D XILINX_CRF_APB(reg->opaque); + uint32_t source =3D FIELD_EX32(s->regs[R_APLL_CTRL], APLL_CTRL, BYPASS) + ? FIELD_EX32(s->regs[R_APLL_CTRL], APLL_CTRL, POST_SRC) + : FIELD_EX32(s->regs[R_APLL_CTRL], APLL_CTRL, PRE_SRC); + + /* + * We must ensure that only one clock is bound to the apll internal cl= ock. + */ + qemu_clk_unbind(s->pss_ref_clk, s->apll_clk); + qemu_clk_unbind(s->video_clk, s->apll_clk); + qemu_clk_unbind(s->pss_alt_ref_clk, s->apll_clk); + qemu_clk_unbind(s->aux_refclk, s->apll_clk); + qemu_clk_unbind(s->gt_crx_ref_clk, s->apll_clk); + + switch (source) { + case VIDEO_CLK: + qemu_clk_bind(s->video_clk, s->apll_clk); + break; + case PSS_ALT_REF_CLK: + qemu_clk_bind(s->pss_alt_ref_clk, s->apll_clk); + break; + case AUX_REF_CLK: + qemu_clk_bind(s->aux_refclk, s->apll_clk); + break; + case GT_CRX_REF_CLK: + qemu_clk_bind(s->gt_crx_ref_clk, s->apll_clk); + break; + default: + qemu_clk_bind(s->pss_ref_clk, s->apll_clk); + break; + } +} + +static void dpll_ctrl_postw(RegisterInfo *reg, uint64_t val64) +{ + CRF_APB *s =3D XILINX_CRF_APB(reg->opaque); + uint32_t source =3D FIELD_EX32(s->regs[R_DPLL_CTRL], DPLL_CTRL, BYPASS) + ? FIELD_EX32(s->regs[R_DPLL_CTRL], DPLL_CTRL, POST_SRC) + : FIELD_EX32(s->regs[R_DPLL_CTRL], DPLL_CTRL, PRE_SRC); + + /* + * We must ensure that only one clock is bound to the dpll internal cl= ock. + */ + qemu_clk_unbind(s->pss_ref_clk, s->dpll_clk); + qemu_clk_unbind(s->video_clk, s->dpll_clk); + qemu_clk_unbind(s->pss_alt_ref_clk, s->dpll_clk); + qemu_clk_unbind(s->aux_refclk, s->dpll_clk); + qemu_clk_unbind(s->gt_crx_ref_clk, s->dpll_clk); + + switch (source) { + case VIDEO_CLK: + qemu_clk_bind(s->video_clk, s->dpll_clk); + break; + case PSS_ALT_REF_CLK: + qemu_clk_bind(s->pss_alt_ref_clk, s->dpll_clk); + break; + case AUX_REF_CLK: + qemu_clk_bind(s->aux_refclk, s->dpll_clk); + break; + case GT_CRX_REF_CLK: + qemu_clk_bind(s->gt_crx_ref_clk, s->dpll_clk); + break; + default: + qemu_clk_bind(s->pss_ref_clk, s->dpll_clk); + break; + } +} + +static void vpll_ctrl_postw(RegisterInfo *reg, uint64_t val64) +{ + CRF_APB *s =3D XILINX_CRF_APB(reg->opaque); + uint32_t source =3D FIELD_EX32(s->regs[R_VPLL_CTRL], VPLL_CTRL, BYPASS) + ? FIELD_EX32(s->regs[R_VPLL_CTRL], VPLL_CTRL, POST_SRC) + : FIELD_EX32(s->regs[R_VPLL_CTRL], VPLL_CTRL, PRE_SRC); + + /* + * We must ensure that only one clock is bound to the vpll internal cl= ock. + */ + qemu_clk_unbind(s->pss_ref_clk, s->vpll_clk); + qemu_clk_unbind(s->video_clk, s->vpll_clk); + qemu_clk_unbind(s->pss_alt_ref_clk, s->vpll_clk); + qemu_clk_unbind(s->aux_refclk, s->vpll_clk); + qemu_clk_unbind(s->gt_crx_ref_clk, s->vpll_clk); + + switch (source) { + case VIDEO_CLK: + qemu_clk_bind(s->video_clk, s->vpll_clk); + break; + case PSS_ALT_REF_CLK: + qemu_clk_bind(s->pss_alt_ref_clk, s->vpll_clk); + break; + case AUX_REF_CLK: + qemu_clk_bind(s->aux_refclk, s->vpll_clk); + break; + case GT_CRX_REF_CLK: + qemu_clk_bind(s->gt_crx_ref_clk, s->vpll_clk); + break; + default: + qemu_clk_bind(s->pss_ref_clk, s->vpll_clk); + break; + } +} + +/* + * This happen when apll get updated. + * As we ensure that only one clk_pin can drive apll we can just do the + * computation from input_rate. + */ +static uint64_t apll_update_rate(void *opaque, uint64_t input_rate) +{ + CRF_APB *s =3D XILINX_CRF_APB(opaque); + bool bypass =3D FIELD_EX32(s->regs[R_APLL_CTRL], APLL_CTRL, BYPASS); + bool reset =3D FIELD_EX32(s->regs[R_APLL_CTRL], APLL_CTRL, RESET); + float div2 =3D FIELD_EX32(s->regs[R_APLL_CTRL], APLL_CTRL, DIV2) ? 0.5f + : 1.0f; + float integer =3D (float)(FIELD_EX32(s->regs[R_APLL_CTRL], + APLL_CTRL, FBDIV)); + float frac =3D FIELD_EX32(s->regs[R_APLL_FRAC_CFG], APLL_FRAC_CFG, ENA= BLED) + ? (float)(FIELD_EX32(s->regs[R_APLL_FRAC_CFG], + APLL_FRAC_CFG, DATA)) + / 65536.0f + : 0.0f; + + if (bypass) { + return input_rate; + } else { + if (reset) { + /* + * This is not supposed to happen user must ensure that BYPASS= is + * set before the PLL are reset. + */ + qemu_log_mask(LOG_GUEST_ERROR, + "APLL is reseted but not bypassed."); + return 0; + } else { + return input_rate * div2 * (integer + frac); + } + } +} + +/* + * This happen when dpll get updated. + * As we ensure that only one clk_pin can drive dpll we can just do the + * computation from input_rate. + */ +static uint64_t dpll_update_rate(void *opaque, uint64_t input_rate) +{ + CRF_APB *s =3D XILINX_CRF_APB(opaque); + bool bypass =3D FIELD_EX32(s->regs[R_DPLL_CTRL], DPLL_CTRL, BYPASS); + bool reset =3D FIELD_EX32(s->regs[R_DPLL_CTRL], DPLL_CTRL, RESET); + float div2 =3D FIELD_EX32(s->regs[R_DPLL_CTRL], DPLL_CTRL, DIV2) ? 0.5f + : 1.0f; + float integer =3D (float)(FIELD_EX32(s->regs[R_DPLL_CTRL], DPLL_CTRL, + FBDIV)); + float frac =3D FIELD_EX32(s->regs[R_DPLL_FRAC_CFG], DPLL_FRAC_CFG, ENA= BLED) + ? (float)(FIELD_EX32(s->regs[R_DPLL_FRAC_CFG], + DPLL_FRAC_CFG, DATA)) + / 65536.0f + : 0.0f; + + if (bypass) { + return input_rate; + } else { + if (reset) { + /* + * This is not supposed to happen user must ensure that BYPASS= is + * set before the PLL are reset. + */ + qemu_log_mask(LOG_GUEST_ERROR, + "DPLL is reseted but not bypassed."); + return 0; + } else { + return input_rate * div2 * (integer + frac); + } + } +} + +/* + * This happen when vpll get updated. + * As we ensure that only one clk_pin can drive vpll we can just do the + * computation from input_rate. + */ +static uint64_t vpll_update_rate(void *opaque, uint64_t input_rate) +{ + CRF_APB *s =3D XILINX_CRF_APB(opaque); + bool bypass =3D FIELD_EX32(s->regs[R_VPLL_CTRL], VPLL_CTRL, BYPASS); + bool reset =3D FIELD_EX32(s->regs[R_VPLL_CTRL], VPLL_CTRL, RESET); + float div2 =3D FIELD_EX32(s->regs[R_VPLL_CTRL], VPLL_CTRL, DIV2) ? 0.5f + : 1.0f; + float integer =3D (float)(FIELD_EX32(s->regs[R_VPLL_CTRL], VPLL_CTRL, + FBDIV)); + float frac =3D FIELD_EX32(s->regs[R_VPLL_FRAC_CFG], VPLL_FRAC_CFG, ENA= BLED) + ? (float)(FIELD_EX32(s->regs[R_VPLL_FRAC_CFG], + VPLL_FRAC_CFG, DATA)) + / 65536.0f + : 0.0f; + + if (bypass) { + return input_rate; + } else { + if (reset) { + /* + * This is not supposed to happen user must ensure that BYPASS= is + * set before the PLL are reset. + */ + qemu_log_mask(LOG_GUEST_ERROR, + "VPLL is reseted but not bypassed."); + return 0; + } else { + return input_rate * div2 * (integer + frac); + } + } +} + +/* + * FIXME: Only DP video reference clock is modeled here, others are missin= g. + */ +static uint64_t dp_video_update_rate(void *opaque, uint64_t input_rate) +{ + CRF_APB *s =3D XILINX_CRF_APB(opaque); + bool clock_act =3D FIELD_EX32(s->regs[R_DP_VIDEO_REF_CTRL], + DP_VIDEO_REF_CTRL, CLKACT); + uint32_t divisor0 =3D FIELD_EX32(s->regs[R_DP_VIDEO_REF_CTRL], + DP_VIDEO_REF_CTRL, DIVISOR0); + + if ((!divisor0) || (!clock_act)) { + return 0.0f; + } else { + return input_rate / (float)(divisor0); + } +} + +static void dp_video_ref_ctrl_postw(RegisterInfo *reg, uint64_t val64) +{ + CRF_APB *s =3D XILINX_CRF_APB(reg->opaque); + uint32_t source =3D FIELD_EX32(s->regs[R_APLL_CTRL], APLL_CTRL, BYPASS) + ? FIELD_EX32(s->regs[R_APLL_CTRL], APLL_CTRL, POST_SRC) + : FIELD_EX32(s->regs[R_APLL_CTRL], APLL_CTRL, PRE_SRC); + + /* + * We must ensure that only one clock is bound to the dp_video_ref + * internal clock, so the callback have always the right rate in it. + */ + qemu_clk_unbind(s->vpll_clk, s->dp_video_ref); + qemu_clk_unbind(s->dpll_clk, s->dp_video_ref); + + switch (source) { + case 0x00: + qemu_clk_bind(s->vpll_clk, s->dp_video_ref); + break; + case 0x02: + qemu_clk_bind(s->dpll_clk, s->dp_video_ref); + break; + default: + abort(); + break; + } +} + +static RegisterAccessInfo crf_apb_regs_info[] =3D { + { .name =3D "ERR_CTRL", .addr =3D A_ERR_CTRL, + },{ .name =3D "IR_STATUS", .addr =3D A_IR_STATUS, + .w1c =3D 0x1, + .post_write =3D ir_status_postw, + },{ .name =3D "IR_MASK", .addr =3D A_IR_MASK, + .reset =3D 0x1, + .ro =3D 0x1, + },{ .name =3D "IR_ENABLE", .addr =3D A_IR_ENABLE, + .pre_write =3D ir_enable_prew, + },{ .name =3D "IR_DISABLE", .addr =3D A_IR_DISABLE, + .pre_write =3D ir_disable_prew, + },{ .name =3D "CRF_ECO", .addr =3D A_CRF_ECO, + },{ .name =3D "APLL_CTRL", .addr =3D A_APLL_CTRL, + .reset =3D 0x2809, + .rsvd =3D 0xf88c80f6L, + .post_write =3D apll_ctrl_postw, + },{ .name =3D "APLL_CFG", .addr =3D A_APLL_CFG, + .rsvd =3D 0x1801210, + },{ .name =3D "APLL_FRAC_CFG", .addr =3D A_APLL_FRAC_CFG, + .rsvd =3D 0x7e330000, + },{ .name =3D "DPLL_CTRL", .addr =3D A_DPLL_CTRL, + .reset =3D 0x2809, + .rsvd =3D 0xf88c80f6L, + .post_write =3D dpll_ctrl_postw, + },{ .name =3D "DPLL_CFG", .addr =3D A_DPLL_CFG, + .rsvd =3D 0x1801210, + },{ .name =3D "DPLL_FRAC_CFG", .addr =3D A_DPLL_FRAC_CFG, + .rsvd =3D 0x7e330000, + },{ .name =3D "VPLL_CTRL", .addr =3D A_VPLL_CTRL, + .reset =3D 0x2809, + .rsvd =3D 0xf88c80f6L, + .post_write =3D vpll_ctrl_postw, + },{ .name =3D "VPLL_CFG", .addr =3D A_VPLL_CFG, + .rsvd =3D 0x1801210, + },{ .name =3D "VPLL_FRAC_CFG", .addr =3D A_VPLL_FRAC_CFG, + .rsvd =3D 0x7e330000, + },{ .name =3D "PLL_STATUS", .addr =3D A_PLL_STATUS, + .reset =3D 0x3f, + .rsvd =3D 0xc0, + .ro =3D 0x3f, + },{ .name =3D "APLL_TO_LPD_CTRL", .addr =3D A_APLL_TO_LPD_CTRL, + .reset =3D 0x400, + .rsvd =3D 0xc0ff, + .post_write =3D apll_to_lpd_postw, + },{ .name =3D "DPLL_TO_LPD_CTRL", .addr =3D A_DPLL_TO_LPD_CTRL, + .reset =3D 0x400, + .rsvd =3D 0xc0ff, + .post_write =3D dpll_to_lpd_postw, + },{ .name =3D "VPLL_TO_LPD_CTRL", .addr =3D A_VPLL_TO_LPD_CTRL, + .reset =3D 0x400, + .rsvd =3D 0xc0ff, + .post_write =3D vpll_to_lpd_postw, + },{ .name =3D "CPU_A9_CTRL", .addr =3D A_CPU_A9_CTRL, + .reset =3D 0xf000400, + .rsvd =3D 0xf0ffc0f8L, + },{ .name =3D "DBG_TRACE_CTRL", .addr =3D A_DBG_TRACE_CTRL, + .reset =3D 0x2500, + .rsvd =3D 0xfeffc0f8L, + },{ .name =3D "DBG_FPD_CTRL", .addr =3D A_DBG_FPD_CTRL, + .reset =3D 0x1002500, + .rsvd =3D 0xfeffc0f8L, + },{ .name =3D "DP_VIDEO_REF_CTRL", .addr =3D A_DP_VIDEO_REF_CTRL, + .reset =3D 0x1002300, + .rsvd =3D 0xfeffc0f8L, + .post_write =3D dp_video_ref_ctrl_postw, + },{ .name =3D "DP_AUDIO_REF_CTRL", .addr =3D A_DP_AUDIO_REF_CTRL, + .reset =3D 0x1002300, + .rsvd =3D 0xfeffc0f8L, + },{ .name =3D "DP_LINK_REF_CTRL", .addr =3D A_DP_LINK_REF_CTRL, + .reset =3D 0x1203200, + .rsvd =3D 0xfec0c0f8L, + },{ .name =3D "DP_STC_REF_CTRL", .addr =3D A_DP_STC_REF_CTRL, + .reset =3D 0x1203200, + .rsvd =3D 0xfec0c0f8L, + },{ .name =3D "DDR_CTRL", .addr =3D A_DDR_CTRL, + .reset =3D 0x1000500, + .rsvd =3D 0xfeffc0f8L, + },{ .name =3D "GPU_REF_CTRL", .addr =3D A_GPU_REF_CTRL, + .reset =3D 0x1500, + .rsvd =3D 0xf8ffc0f8L, + },{ .name =3D "AFI0_REF_CTRL", .addr =3D A_AFI0_REF_CTRL, + .reset =3D 0x600, + .rsvd =3D 0x7effc0f8, + },{ .name =3D "AFI1_REF_CTRL", .addr =3D A_AFI1_REF_CTRL, + .reset =3D 0x600, + .rsvd =3D 0x7effc0f8, + },{ .name =3D "AFI2_REF_CTRL", .addr =3D A_AFI2_REF_CTRL, + .reset =3D 0x600, + .rsvd =3D 0x7effc0f8, + },{ .name =3D "AFI3_REF_CTRL", .addr =3D A_AFI3_REF_CTRL, + .reset =3D 0x600, + .rsvd =3D 0x7effc0f8, + },{ .name =3D "AFI4_REF_CTRL", .addr =3D A_AFI4_REF_CTRL, + .reset =3D 0x600, + .rsvd =3D 0x7effc0f8, + },{ .name =3D "AFI5_REF_CTRL", .addr =3D A_AFI5_REF_CTRL, + .reset =3D 0x600, + .rsvd =3D 0x7effc0f8, + },{ .name =3D "SATA_REF_CTRL", .addr =3D A_SATA_REF_CTRL, + .reset =3D 0x1001600, + .rsvd =3D 0xfeffc0f8L, + },{ .name =3D "PCIE_REF_CTRL", .addr =3D A_PCIE_REF_CTRL, + .reset =3D 0x1500, + .rsvd =3D 0xfeffc0f8L, + },{ .name =3D "GDMA_REF_CTRL", .addr =3D A_GDMA_REF_CTRL, + .reset =3D 0x1000500, + .rsvd =3D 0xfeffc0f8L, + },{ .name =3D "DPDMA_REF_CTRL", .addr =3D A_DPDMA_REF_CTRL, + .reset =3D 0x1000500, + .rsvd =3D 0xfeffc0f8L, + },{ .name =3D "TOPSW_MAIN_CTRL", .addr =3D A_TOPSW_MAIN_CTRL, + .reset =3D 0x1000500, + .rsvd =3D 0xfeffc0f8L, + },{ .name =3D "TOPSW_LSBUS_CTRL", .addr =3D A_TOPSW_LSBUS_CTRL, + .reset =3D 0x1000800, + .rsvd =3D 0xfeffc0f8L, + },{ .name =3D "GTGREF0_REF_CTRL", .addr =3D A_GTGREF0_REF_CTRL, + .reset =3D 0x800, + .rsvd =3D 0xfeffc0f8L, + },{ .name =3D "GTGREF1_REF_CTRL", .addr =3D A_GTGREF1_REF_CTRL, + .reset =3D 0x800, + .rsvd =3D 0xfeffc0f8L, + },{ .name =3D "DFT300_REF_CTRL", .addr =3D A_DFT300_REF_CTRL, + .reset =3D 0x800, + .rsvd =3D 0xfeffc0f8L, + },{ .name =3D "DFT270_REF_CTRL", .addr =3D A_DFT270_REF_CTRL, + .reset =3D 0x800, + .rsvd =3D 0xfeffc0f8L, + },{ .name =3D "DFT250_REF_CTRL", .addr =3D A_DFT250_REF_CTRL, + .reset =3D 0x800, + .rsvd =3D 0xfeffc0f8L, + },{ .name =3D "DFT125_REF_CTRL", .addr =3D A_DFT125_REF_CTRL, + .reset =3D 0x800, + .rsvd =3D 0xfeffc0f8L, + },{ .name =3D "RST_FPD_TOP", .addr =3D A_RST_FPD_TOP, + .reset =3D 0x71ffe, + .rsvd =3D 0xf8e001, + },{ .name =3D "RST_FPD_APU", .addr =3D A_RST_FPD_APU, + .reset =3D 0x334f, + .rsvd =3D 0xffcccc, + },{ .name =3D "RST_DDR_SS", .addr =3D A_RST_DDR_SS, + .reset =3D 0xf, + .rsvd =3D 0xf0, + } +}; + +static void crf_apb_reset(DeviceState *dev) +{ + CRF_APB *s =3D XILINX_CRF_APB(dev); + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(s->regs_info); ++i) { + register_reset(&s->regs_info[i]); + } + + ir_update_irq(s); + + /* + * During reset, the clock selection registers bound the clock like th= is. + */ + qemu_clk_bind(s->pss_ref_clk, s->apll_clk); + qemu_clk_bind(s->pss_ref_clk, s->dpll_clk); + qemu_clk_bind(s->pss_ref_clk, s->vpll_clk); + qemu_clk_bind(s->vpll_clk, s->dp_video_ref); +} + +static void crf_apb_realize(DeviceState *d, Error **errp) +{ + CRF_APB *s =3D XILINX_CRF_APB(d); + + qemu_clk_bind(s->apll_clk, s->apll_to_lpd); + qemu_clk_bind(s->dpll_clk, s->dpll_to_lpd); + qemu_clk_bind(s->vpll_clk, s->vpll_to_lpd); + + crf_apb_reset(d); +} + +static void crf_apb_init(Object *obj) +{ + CRF_APB *s =3D XILINX_CRF_APB(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + RegisterInfoArray *reg_array; + + memory_region_init(&s->iomem, obj, TYPE_XILINX_CRF_APB, R_MAX * 4); + reg_array =3D register_init_block32(DEVICE(obj), crf_apb_regs_info, + ARRAY_SIZE(crf_apb_regs_info), + s->regs_info, s->regs, + &crf_apb_ops, + XILINX_CRF_APB_ERR_DEBUG, + R_RST_DDR_SS); + memory_region_add_subregion(&s->iomem, + A_ERR_CTRL, + ®_array->mem); + + sysbus_init_mmio(sbd, &s->iomem); + sysbus_init_irq(sbd, &s->irq_ir); + + qemu_clk_init_device(obj, crf_clock); +} + +static const VMStateDescription vmstate_crf_apb =3D { + .name =3D TYPE_XILINX_CRF_APB, + .version_id =3D 1, + .minimum_version_id =3D 1, + .minimum_version_id_old =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, CRF_APB, R_MAX), + VMSTATE_END_OF_LIST(), + } +}; + +static void crf_apb_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->reset =3D crf_apb_reset; + dc->vmsd =3D &vmstate_crf_apb; + dc->realize =3D crf_apb_realize; +} + +static const TypeInfo crf_apb_info =3D { + .name =3D TYPE_XILINX_CRF_APB, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(CRF_APB), + .class_init =3D crf_apb_class_init, + .instance_init =3D crf_apb_init, +}; + +static void crf_apb_register_types(void) +{ + type_register_static(&crf_apb_info); +} + +type_init(crf_apb_register_types) --=20 1.8.3.1 From nobody Mon May 20 02:35:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1488276610365366.2347200934927; Tue, 28 Feb 2017 02:10:10 -0800 (PST) Received: from localhost ([::1]:59878 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ciejQ-0003VP-Sy for importer@patchew.org; Tue, 28 Feb 2017 05:10:08 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58970) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cied7-0006pN-PL for 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qemu-devel@nongnu.org Date: Tue, 28 Feb 2017 11:03:04 +0100 Message-Id: <1488276185-31168-10-git-send-email-fred.konrad@greensocs.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1488276185-31168-1-git-send-email-fred.konrad@greensocs.com> References: <1488276185-31168-1-git-send-email-fred.konrad@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v3 09/10] zynqmp: add the zynqmp_crf to the platform X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, mark.burton@greensocs.com, alistair.francis@xilinx.com, clg@kaod.org, fred.konrad@greensocs.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: KONRAD Frederic This adds the zynqmp_crf to the zynqmp platform. Signed-off-by: KONRAD Frederic --- hw/arm/xlnx-zynqmp.c | 7 +++++++ include/hw/arm/xlnx-zynqmp.h | 2 ++ 2 files changed, 9 insertions(+) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index bc4e66b..27dccdb 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -177,6 +177,11 @@ static void xlnx_zynqmp_init(Object *obj) =20 object_initialize(&s->dpdma, sizeof(s->dpdma), TYPE_XLNX_DPDMA); qdev_set_parent_bus(DEVICE(&s->dpdma), sysbus_get_default()); + + s->crf =3D object_new("xlnx.zynqmp_crf"); + qdev_set_parent_bus(DEVICE(s->crf), sysbus_get_default()); + object_property_add_child(obj, "xlnx.zynqmp_crf", OBJECT(s->crf), + &error_abort); } =20 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) @@ -424,6 +429,8 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error= **errp) &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR); sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]); + + sysbus_mmio_map(SYS_BUS_DEVICE(s->crf), 0, 0xFD1A0000); } =20 static Property xlnx_zynqmp_props[] =3D { diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index c2931bf..379a17a 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -86,6 +86,8 @@ typedef struct XlnxZynqMPState { XlnxDPState dp; XlnxDPDMAState dpdma; =20 + Object *crf; + char *boot_cpu; ARMCPU *boot_cpu_ptr; =20 --=20 1.8.3.1 From nobody Mon May 20 02:35:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1488276853566547.6149799325118; Tue, 28 Feb 2017 02:14:13 -0800 (PST) Received: from localhost ([::1]:59905 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cienM-0007Dc-6G for importer@patchew.org; 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Tue, 28 Feb 2017 11:03:35 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1488276216; bh=EoFkxZEF+JVKSGUhI0esH/4DD6Nzf+TjtYyFtNJTs3s=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Nd8noSRbv/FxBC+InQKE2CJf7ZThkuv3wj3/vEMdC1qoId75mykF4tyQ4NyBIM9PA 6MoQsbmx4lHztb4FlDYuqu2M+PQN3aWc6ko6YGjEJCgn9muAKl7Ly/oEzKckjh1PiA vEZoG6rYFf0xpHSq5NHObsSW5HKb9Okp41vQn5X4= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1488276215; bh=EoFkxZEF+JVKSGUhI0esH/4DD6Nzf+TjtYyFtNJTs3s=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=2ZDx8XukNoI4s3NQ6c8VkKMHAK/ud4zBq6oNcOnwSaFUar2kInWlkRhTfN/cJw3f1 UPTZtFqDHaCrcevaedErgo0s3cb0aYZ8S58LcAzLofQLG6WgZnv7jcmXx70Qj445Hf ALME6mMhRQnzFKgtLd0sGJvQoO+rY2k7DWWFie7M= From: fred.konrad@greensocs.com To: qemu-devel@nongnu.org Date: Tue, 28 Feb 2017 11:03:05 +0100 Message-Id: <1488276185-31168-11-git-send-email-fred.konrad@greensocs.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1488276185-31168-1-git-send-email-fred.konrad@greensocs.com> References: <1488276185-31168-1-git-send-email-fred.konrad@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v3 10/10] zynqmp: add reference clock X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, mark.burton@greensocs.com, alistair.francis@xilinx.com, clg@kaod.org, fred.konrad@greensocs.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: KONRAD Frederic This adds some fixed reference clock to the zynqmp platform. They will feed the zynqmp_crf block. Signed-off-by: KONRAD Frederic --- hw/arm/xlnx-zynqmp.c | 49 ++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/arm/xlnx-zynqmp.h | 6 ++++++ 2 files changed, 55 insertions(+) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 27dccdb..b9cd856 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -24,6 +24,7 @@ #include "exec/address-spaces.h" #include "sysemu/kvm.h" #include "kvm_arm.h" +#include "qemu/qemu-clock.h" =20 #define GIC_NUM_SPI_INTR 160 =20 @@ -182,6 +183,22 @@ static void xlnx_zynqmp_init(Object *obj) qdev_set_parent_bus(DEVICE(s->crf), sysbus_get_default()); object_property_add_child(obj, "xlnx.zynqmp_crf", OBJECT(s->crf), &error_abort); + + s->pss_ref_clk =3D object_new(TYPE_FIXED_CLOCK); + object_property_add_child(obj, "pss_ref_clk", s->pss_ref_clk, + &error_abort); + object_property_set_int(s->pss_ref_clk, 50000000, "rate", &error_abort= ); + s->video_clk =3D object_new(TYPE_FIXED_CLOCK); + object_property_add_child(obj, "video_clk", s->video_clk, &error_abort= ); + object_property_set_int(s->video_clk, 27000000, "rate", &error_abort); + s->pss_alt_ref_clk =3D object_new(TYPE_FIXED_CLOCK); + object_property_add_child(obj, "pss_alt_ref_clk", s->pss_alt_ref_clk, + &error_abort); + s->aux_refclk =3D object_new(TYPE_FIXED_CLOCK); + object_property_add_child(obj, "aux_refclk", s->aux_refclk, &error_abo= rt); + s->gt_crx_ref_clk =3D object_new(TYPE_FIXED_CLOCK); + object_property_add_child(obj, "gt_crx_ref_clk", s->gt_crx_ref_clk, + &error_abort); } =20 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) @@ -431,6 +448,38 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Erro= r **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]); =20 sysbus_mmio_map(SYS_BUS_DEVICE(s->crf), 0, 0xFD1A0000); + + /* Bind the clock */ + qemu_clk_bind(qemu_clk_device_get_clock(DEVICE(s->pss_ref_clk), + "clk_out"), + qemu_clk_device_get_clock(DEVICE(s->crf), + "pss_ref_clk")); + + qemu_clk_bind(qemu_clk_device_get_clock(DEVICE(s->video_clk), + "clk_out"), + qemu_clk_device_get_clock(DEVICE(s->crf), "video_c= lk")); + + qemu_clk_bind(qemu_clk_device_get_clock(DEVICE(s->pss_alt_ref_clk), + "clk_out"), + qemu_clk_device_get_clock(DEVICE(s->crf), + "pss_alt_ref_clk")); + + qemu_clk_bind(qemu_clk_device_get_clock(DEVICE(s->aux_refclk), + "clk_out"), + qemu_clk_device_get_clock(DEVICE(s->crf), + "aux_refclk")); + + qemu_clk_bind(qemu_clk_device_get_clock(DEVICE(s->gt_crx_ref_clk), + "clk_out"), + qemu_clk_device_get_clock(DEVICE(s->crf), + "gt_crx_ref_clk")); + + object_property_set_bool(s->crf, true, "realized", &err); + object_property_set_bool(s->pss_ref_clk, true, "realized", &err); + object_property_set_bool(s->video_clk, true, "realized", &err); + object_property_set_bool(s->pss_alt_ref_clk, true, "realized", &err); + object_property_set_bool(s->aux_refclk, true, "realized", &err); + object_property_set_bool(s->gt_crx_ref_clk, true, "realized", &err); } =20 static Property xlnx_zynqmp_props[] =3D { diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 379a17a..d0cc57f 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -28,6 +28,7 @@ #include "hw/ssi/xilinx_spips.h" #include "hw/dma/xlnx_dpdma.h" #include "hw/display/xlnx_dp.h" +#include "hw/misc/fixed-clock.h" =20 #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \ @@ -86,6 +87,11 @@ typedef struct XlnxZynqMPState { XlnxDPState dp; XlnxDPDMAState dpdma; =20 + Object *pss_ref_clk; + Object *video_clk; + Object *pss_alt_ref_clk; + Object *aux_refclk; + Object *gt_crx_ref_clk; Object *crf; =20 char *boot_cpu; --=20 1.8.3.1