From nobody Sun Feb 8 22:21:59 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1488220697010349.1316296116096; Mon, 27 Feb 2017 10:38:17 -0800 (PST) Received: from localhost ([::1]:55682 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ciQBa-0005V4-Mj for importer@patchew.org; Mon, 27 Feb 2017 13:38:14 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52219) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ciPfk-0002R4-1a for qemu-devel@nongnu.org; Mon, 27 Feb 2017 13:05:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ciPfh-0001x0-C5 for qemu-devel@nongnu.org; Mon, 27 Feb 2017 13:05:20 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:48679) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ciPfh-0001rj-27 for qemu-devel@nongnu.org; Mon, 27 Feb 2017 13:05:17 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1ciPfR-0002JF-S4 for qemu-devel@nongnu.org; Mon, 27 Feb 2017 18:05:01 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 27 Feb 2017 18:04:32 +0000 Message-Id: <1488218699-31035-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1488218699-31035-1-git-send-email-peter.maydell@linaro.org> References: <1488218699-31035-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 03/30] sd: sdhci: mask transfer mode register value X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Prasad J Pandit In SDHCI protocol, the transfer mode register is defined to be of 6 bits. Mask its value with '0x0037' so that an invalid value could not be assigned. Signed-off-by: Prasad J Pandit Reviewed-by: Alistair Francis Message-id: 20170214185225.7994-2-ppandit@redhat.com Signed-off-by: Peter Maydell --- hw/sd/sdhci.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index da32b5f..a65c77d 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -119,6 +119,7 @@ (SDHC_CAPAB_BASECLKFREQ << 8) | (SDHC_CAPAB_TOUNIT << 7) | \ (SDHC_CAPAB_TOCLKFREQ)) =20 +#define MASK_TRNMOD 0x0037 #define MASKED_WRITE(reg, mask, val) (reg =3D (reg & (mask)) | (val)) =20 static uint8_t sdhci_slotint(SDHCIState *s) @@ -1050,7 +1051,7 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val= , unsigned size) if (!(s->capareg & SDHC_CAN_DO_DMA)) { value &=3D ~SDHC_TRNS_DMA; } - MASKED_WRITE(s->trnmod, mask, value); + MASKED_WRITE(s->trnmod, mask, value & MASK_TRNMOD); MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16); =20 /* Writing to the upper byte of CMDREG triggers SD command generat= ion */ --=20 2.7.4