From nobody Tue Apr 15 15:30:29 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1488219363081943.5830683219997; Mon, 27 Feb 2017 10:16:03 -0800 (PST) Received: from localhost ([::1]:55547 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ciPq4-00038h-LS for importer@patchew.org; Mon, 27 Feb 2017 13:16:00 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51960) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ciPfd-0002Kw-TS for qemu-devel@nongnu.org; Mon, 27 Feb 2017 13:05:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ciPfc-0001rr-9V for qemu-devel@nongnu.org; Mon, 27 Feb 2017 13:05:13 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:48677) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ciPfc-0001lG-2s for qemu-devel@nongnu.org; Mon, 27 Feb 2017 13:05:12 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1ciPfb-0002Pw-02 for qemu-devel@nongnu.org; Mon, 27 Feb 2017 18:05:11 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 27 Feb 2017 18:04:50 +0000 Message-Id: <1488218699-31035-22-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1488218699-31035-1-git-send-email-peter.maydell@linaro.org> References: <1488218699-31035-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 21/30] armv7m: Extract "exception taken" code into functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Extract the code from the tail end of arm_v7m_do_interrupt() which enters the exception handler into a pair of utility functions v7m_exception_taken() and v7m_push_stack(), which correspond roughly to the pseudocode PushStack() and ExceptionTaken(). This also requires us to move the arm_v7m_load_vector() utility routine up so we can call it. Handling illegal exception returns has some cases where we want to take a UsageFault either on an existing stack frame or with a new stack frame but with a specific LR value, so we want to be able to call these without having to go via arm_v7m_cpu_do_interrupt(). Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e --- target/arm/helper.c | 118 ++++++++++++++++++++++++++++++------------------= ---- 1 file changed, 68 insertions(+), 50 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 664f030..be731dc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6002,6 +6002,72 @@ static void switch_v7m_sp(CPUARMState *env, bool new= _spsel) } } =20 +static uint32_t arm_v7m_load_vector(ARMCPU *cpu) +{ + CPUState *cs =3D CPU(cpu); + CPUARMState *env =3D &cpu->env; + MemTxResult result; + hwaddr vec =3D env->v7m.vecbase + env->v7m.exception * 4; + uint32_t addr; + + addr =3D address_space_ldl(cs->as, vec, + MEMTXATTRS_UNSPECIFIED, &result); + if (result !=3D MEMTX_OK) { + /* Architecturally this should cause a HardFault setting HSFR.VECT= TBL, + * which would then be immediately followed by our failing to load + * the entry vector for that HardFault, which is a Lockup case. + * Since we don't model Lockup, we just report this guest error + * via cpu_abort(). + */ + cpu_abort(cs, "Failed to read from exception vector table " + "entry %08x\n", (unsigned)vec); + } + return addr; +} + +static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr) +{ + /* Do the "take the exception" parts of exception entry, + * but not the pushing of state to the stack. This is + * similar to the pseudocode ExceptionTaken() function. + */ + CPUARMState *env =3D &cpu->env; + uint32_t addr; + + armv7m_nvic_acknowledge_irq(env->nvic); + switch_v7m_sp(env, 0); + /* Clear IT bits */ + env->condexec_bits =3D 0; + env->regs[14] =3D lr; + addr =3D arm_v7m_load_vector(cpu); + env->regs[15] =3D addr & 0xfffffffe; + env->thumb =3D addr & 1; +} + +static void v7m_push_stack(ARMCPU *cpu) +{ + /* Do the "set up stack frame" part of exception entry, + * similar to pseudocode PushStack(). + */ + CPUARMState *env =3D &cpu->env; + uint32_t xpsr =3D xpsr_read(env); + + /* Align stack pointer if the guest wants that */ + if ((env->regs[13] & 4) && (env->v7m.ccr & R_V7M_CCR_STKALIGN_MASK)) { + env->regs[13] -=3D 4; + xpsr |=3D 0x200; + } + /* Switch to the handler mode. */ + v7m_push(env, xpsr); + v7m_push(env, env->regs[15]); + v7m_push(env, env->regs[14]); + v7m_push(env, env->regs[12]); + v7m_push(env, env->regs[3]); + v7m_push(env, env->regs[2]); + v7m_push(env, env->regs[1]); + v7m_push(env, env->regs[0]); +} + static void do_v7m_exception_exit(CPUARMState *env) { uint32_t type; @@ -6063,37 +6129,11 @@ static void arm_log_exception(int idx) } } =20 -static uint32_t arm_v7m_load_vector(ARMCPU *cpu) - -{ - CPUState *cs =3D CPU(cpu); - CPUARMState *env =3D &cpu->env; - MemTxResult result; - hwaddr vec =3D env->v7m.vecbase + env->v7m.exception * 4; - uint32_t addr; - - addr =3D address_space_ldl(cs->as, vec, - MEMTXATTRS_UNSPECIFIED, &result); - if (result !=3D MEMTX_OK) { - /* Architecturally this should cause a HardFault setting HSFR.VECT= TBL, - * which would then be immediately followed by our failing to load - * the entry vector for that HardFault, which is a Lockup case. - * Since we don't model Lockup, we just report this guest error - * via cpu_abort(). - */ - cpu_abort(cs, "Failed to read from exception vector table " - "entry %08x\n", (unsigned)vec); - } - return addr; -} - void arm_v7m_cpu_do_interrupt(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; - uint32_t xpsr =3D xpsr_read(env); uint32_t lr; - uint32_t addr; =20 arm_log_exception(cs->exception_index); =20 @@ -6151,31 +6191,9 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) return; /* Never happens. Keep compiler happy. */ } =20 - armv7m_nvic_acknowledge_irq(env->nvic); - + v7m_push_stack(cpu); + v7m_exception_taken(cpu, lr); qemu_log_mask(CPU_LOG_INT, "... as %d\n", env->v7m.exception); - - /* Align stack pointer if the guest wants that */ - if ((env->regs[13] & 4) && (env->v7m.ccr & R_V7M_CCR_STKALIGN_MASK)) { - env->regs[13] -=3D 4; - xpsr |=3D 0x200; - } - /* Switch to the handler mode. */ - v7m_push(env, xpsr); - v7m_push(env, env->regs[15]); - v7m_push(env, env->regs[14]); - v7m_push(env, env->regs[12]); - v7m_push(env, env->regs[3]); - v7m_push(env, env->regs[2]); - v7m_push(env, env->regs[1]); - v7m_push(env, env->regs[0]); - switch_v7m_sp(env, 0); - /* Clear IT bits */ - env->condexec_bits =3D 0; - env->regs[14] =3D lr; - addr =3D arm_v7m_load_vector(cpu); - env->regs[15] =3D addr & 0xfffffffe; - env->thumb =3D addr & 1; } =20 /* Function used to synchronize QEMU's AArch64 register set with AArch32 --=20 2.7.4