From nobody Tue Apr 15 15:30:29 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1488219647048573.4924080992022; Mon, 27 Feb 2017 10:20:47 -0800 (PST) Received: from localhost ([::1]:55573 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ciPud-0006u1-Iq for importer@patchew.org; Mon, 27 Feb 2017 13:20:43 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52046) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ciPfg-0002N7-BB for qemu-devel@nongnu.org; Mon, 27 Feb 2017 13:05:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ciPfd-0001sy-Cv for qemu-devel@nongnu.org; Mon, 27 Feb 2017 13:05:16 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:48678) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ciPfd-0001qs-3y for qemu-devel@nongnu.org; Mon, 27 Feb 2017 13:05:13 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1ciPfY-0002O7-Bv for qemu-devel@nongnu.org; Mon, 27 Feb 2017 18:05:08 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 27 Feb 2017 18:04:45 +0000 Message-Id: <1488218699-31035-17-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1488218699-31035-1-git-send-email-peter.maydell@linaro.org> References: <1488218699-31035-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 16/30] arm: gic: Remove references to NVIC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: Michael Davidsaver Now that the NVIC is its own separate implementation, we can clean up the GIC code by removing REV_NVIC and conditionals which use it. Signed-off-by: Michael Davidsaver Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e --- hw/intc/gic_internal.h | 7 ++----- hw/intc/arm_gic.c | 31 +++++-------------------------- hw/intc/arm_gic_common.c | 23 ++++++++--------------- 3 files changed, 15 insertions(+), 46 deletions(-) diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h index 3f31174..7fe87b1 100644 --- a/hw/intc/gic_internal.h +++ b/hw/intc/gic_internal.h @@ -25,9 +25,7 @@ =20 #define ALL_CPU_MASK ((unsigned)(((1 << GIC_NCPU) - 1))) =20 -/* The NVIC has 16 internal vectors. However these are not exposed - through the normal GIC interface. */ -#define GIC_BASE_IRQ ((s->revision =3D=3D REV_NVIC) ? 32 : 0) +#define GIC_BASE_IRQ 0 =20 #define GIC_SET_ENABLED(irq, cm) s->irq_state[irq].enabled |=3D (cm) #define GIC_CLEAR_ENABLED(irq, cm) s->irq_state[irq].enabled &=3D ~(cm) @@ -75,7 +73,6 @@ =20 /* The special cases for the revision property: */ #define REV_11MPCORE 0 -#define REV_NVIC 0xffffffff =20 void gic_set_pending_private(GICState *s, int cpu, int irq); uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs); @@ -87,7 +84,7 @@ void gic_set_priority(GICState *s, int cpu, int irq, uint= 8_t val, =20 static inline bool gic_test_pending(GICState *s, int irq, int cm) { - if (s->revision =3D=3D REV_NVIC || s->revision =3D=3D REV_11MPCORE) { + if (s->revision =3D=3D REV_11MPCORE) { return s->irq_state[irq].pending & cm; } else { /* Edge-triggered interrupts are marked pending on a rising edge, = but diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 521aac3..8e5a9d8 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -156,17 +156,6 @@ static void gic_set_irq_11mpcore(GICState *s, int irq,= int level, } } =20 -static void gic_set_irq_nvic(GICState *s, int irq, int level, - int cm, int target) -{ - if (level) { - GIC_SET_LEVEL(irq, cm); - GIC_SET_PENDING(irq, target); - } else { - GIC_CLEAR_LEVEL(irq, cm); - } -} - static void gic_set_irq_generic(GICState *s, int irq, int level, int cm, int target) { @@ -214,8 +203,6 @@ static void gic_set_irq(void *opaque, int irq, int leve= l) =20 if (s->revision =3D=3D REV_11MPCORE) { gic_set_irq_11mpcore(s, irq, level, cm, target); - } else if (s->revision =3D=3D REV_NVIC) { - gic_set_irq_nvic(s, irq, level, cm, target); } else { gic_set_irq_generic(s, irq, level, cm, target); } @@ -367,7 +354,7 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemT= xAttrs attrs) return 1023; } =20 - if (s->revision =3D=3D REV_11MPCORE || s->revision =3D=3D REV_NVIC) { + if (s->revision =3D=3D REV_11MPCORE) { /* Clear pending flags for both level and edge triggered interrupt= s. * Level triggered IRQs will be reasserted once they become inacti= ve. */ @@ -589,11 +576,6 @@ void gic_complete_irq(GICState *s, int cpu, int irq, M= emTxAttrs attrs) DPRINTF("Set %d pending mask %x\n", irq, cm); GIC_SET_PENDING(irq, cm); } - } else if (s->revision =3D=3D REV_NVIC) { - if (GIC_TEST_LEVEL(irq, cm)) { - DPRINTF("Set nvic %d pending mask %x\n", irq, cm); - GIC_SET_PENDING(irq, cm); - } } =20 group =3D gic_has_groups(s) && GIC_TEST_GROUP(irq, cm); @@ -768,7 +750,7 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr off= set, MemTxAttrs attrs) } else if (offset < 0xf10) { goto bad_reg; } else if (offset < 0xf30) { - if (s->revision =3D=3D REV_11MPCORE || s->revision =3D=3D REV_NVIC= ) { + if (s->revision =3D=3D REV_11MPCORE) { goto bad_reg; } =20 @@ -802,9 +784,6 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr off= set, MemTxAttrs attrs) case 2: res =3D gic_id_gicv2[(offset - 0xfd0) >> 2]; break; - case REV_NVIC: - /* Shouldn't be able to get here */ - abort(); default: res =3D 0; } @@ -1028,7 +1007,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offs= et, continue; /* Ignore Non-secure access of Group0 IRQ */ } =20 - if (s->revision =3D=3D REV_11MPCORE || s->revision =3D=3D REV_= NVIC) { + if (s->revision =3D=3D REV_11MPCORE) { if (value & (1 << (i * 2))) { GIC_SET_MODEL(irq + i); } else { @@ -1046,7 +1025,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offs= et, goto bad_reg; } else if (offset < 0xf20) { /* GICD_CPENDSGIRn */ - if (s->revision =3D=3D REV_11MPCORE || s->revision =3D=3D REV_NVIC= ) { + if (s->revision =3D=3D REV_11MPCORE) { goto bad_reg; } irq =3D (offset - 0xf10); @@ -1060,7 +1039,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offs= et, } } else if (offset < 0xf30) { /* GICD_SPENDSGIRn */ - if (s->revision =3D=3D REV_11MPCORE || s->revision =3D=3D REV_NVIC= ) { + if (s->revision =3D=3D REV_11MPCORE) { goto bad_reg; } irq =3D (offset - 0xf20); diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index 4a8df44..70f1134 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -99,9 +99,7 @@ void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler= handler, * [N+32..N+63] PPIs for CPU 1 * ... */ - if (s->revision !=3D REV_NVIC) { - i +=3D (GIC_INTERNAL * s->num_cpu); - } + i +=3D (GIC_INTERNAL * s->num_cpu); qdev_init_gpio_in(DEVICE(s), handler, i); =20 for (i =3D 0; i < s->num_cpu; i++) { @@ -121,16 +119,12 @@ void gic_init_irqs_and_mmio(GICState *s, qemu_irq_han= dler handler, memory_region_init_io(&s->iomem, OBJECT(s), ops, s, "gic_dist", 0x1000= ); sysbus_init_mmio(sbd, &s->iomem); =20 - if (s->revision !=3D REV_NVIC) { - /* This is the main CPU interface "for this core". It is always - * present because it is required by both software emulation and K= VM. - * NVIC is not handled here because its CPU interface is different, - * neither it can use KVM. - */ - memory_region_init_io(&s->cpuiomem[0], OBJECT(s), ops ? &ops[1] : = NULL, - s, "gic_cpu", s->revision =3D=3D 2 ? 0x2000 = : 0x100); - sysbus_init_mmio(sbd, &s->cpuiomem[0]); - } + /* This is the main CPU interface "for this core". It is always + * present because it is required by both software emulation and KVM. + */ + memory_region_init_io(&s->cpuiomem[0], OBJECT(s), ops ? &ops[1] : NULL, + s, "gic_cpu", s->revision =3D=3D 2 ? 0x2000 : 0x= 100); + sysbus_init_mmio(sbd, &s->cpuiomem[0]); } =20 static void arm_gic_common_realize(DeviceState *dev, Error **errp) @@ -162,7 +156,7 @@ static void arm_gic_common_realize(DeviceState *dev, Er= ror **errp) } =20 if (s->security_extn && - (s->revision =3D=3D REV_11MPCORE || s->revision =3D=3D REV_NVIC)) { + (s->revision =3D=3D REV_11MPCORE)) { error_setg(errp, "this GIC revision does not implement " "the security extensions"); return; @@ -255,7 +249,6 @@ static Property arm_gic_common_properties[] =3D { DEFINE_PROP_UINT32("num-irq", GICState, num_irq, 32), /* Revision can be 1 or 2 for GIC architecture specification * versions 1 or 2, or 0 to indicate the legacy 11MPCore GIC. - * (Internally, 0xffffffff also indicates "not a GIC but an NVIC".) */ DEFINE_PROP_UINT32("revision", GICState, revision, 1), /* True if the GIC should implement the security extensions */ --=20 2.7.4