From nobody Tue Feb 10 03:39:06 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1488180305472204.0116860419787; Sun, 26 Feb 2017 23:25:05 -0800 (PST) Received: from localhost ([::1]:50766 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ciFg8-0002Un-3O for importer@patchew.org; Mon, 27 Feb 2017 02:25:04 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51996) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ciFe3-0001OG-BV for qemu-devel@nongnu.org; Mon, 27 Feb 2017 02:22:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ciFe2-0004DB-Gl for qemu-devel@nongnu.org; Mon, 27 Feb 2017 02:22:55 -0500 Received: from [59.151.112.132] (port=17765 helo=heian.cn.fujitsu.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ciFe2-0004Cx-4h for qemu-devel@nongnu.org; Mon, 27 Feb 2017 02:22:54 -0500 Received: from unknown (HELO cn.fujitsu.com) ([10.167.33.5]) by heian.cn.fujitsu.com with ESMTP; 27 Feb 2017 15:22:52 +0800 Received: from G08CNEXCHPEKD03.g08.fujitsu.local (unknown [10.167.33.85]) by cn.fujitsu.com (Postfix) with ESMTP id CF75F47C4EB6; Mon, 27 Feb 2017 15:22:48 +0800 (CST) Received: from G08FNSTD140223.g08.fujitsu.local (10.167.226.69) by G08CNEXCHPEKD03.g08.fujitsu.local (10.167.33.89) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 27 Feb 2017 15:22:52 +0800 X-IronPort-AV: E=Sophos;i="5.22,518,1449504000"; d="scan'208";a="15992175" From: Cao jin To: Date: Mon, 27 Feb 2017 15:30:25 +0800 Message-ID: <1488180627-18258-2-git-send-email-caoj.fnst@cn.fujitsu.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1488180627-18258-1-git-send-email-caoj.fnst@cn.fujitsu.com> References: <1488180627-18258-1-git-send-email-caoj.fnst@cn.fujitsu.com> MIME-Version: 1.0 X-Originating-IP: [10.167.226.69] X-yoursite-MailScanner-ID: CF75F47C4EB6.AF0CB X-yoursite-MailScanner: Found to be clean X-yoursite-MailScanner-From: caoj.fnst@cn.fujitsu.com X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 59.151.112.132 Subject: [Qemu-devel] [PATCH 1/3] pcie aer: verify if AER functionality is available X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: izumi.taku@jp.fujitsu.com, alex.williamson@redhat.com, Dou Liyang , mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For devices which support AER, verify it can work or not in the system: 1. AER capable device is a PCIe device, it can't be plugged into PCI bus 2. If root port doesn't support AER, then there is no need to expose the AER capability Signed-off-by: Dou Liyang Signed-off-by: Cao jin --- hw/pci/pcie_aer.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/hw/pci/pcie_aer.c b/hw/pci/pcie_aer.c index daf1f65..a2e9818 100644 --- a/hw/pci/pcie_aer.c +++ b/hw/pci/pcie_aer.c @@ -100,6 +100,34 @@ static void aer_log_clear_all_err(PCIEAERLog *aer_log) int pcie_aer_init(PCIDevice *dev, uint8_t cap_ver, uint16_t offset, uint16_t size, Error **errp) { + PCIDevice *parent_dev; + uint8_t type; + uint8_t parent_type; + + /* Topology test: see if there is need to expose AER cap */ + type =3D pcie_cap_get_type(dev); + parent_dev =3D pci_bridge_get_device(dev->bus); + while (parent_dev) { + parent_type =3D pcie_cap_get_type(parent_dev); + + if (type =3D=3D PCI_EXP_TYPE_ENDPOINT && + (parent_type !=3D PCI_EXP_TYPE_ROOT_PORT && + parent_type !=3D PCI_EXP_TYPE_DOWNSTREAM)) { + error_setg(errp, "Parent device is not a PCIe component"); + return -ENOTSUP; + } + + if (parent_type =3D=3D PCI_EXP_TYPE_ROOT_PORT) { + if (!parent_dev->exp.aer_cap) + { + error_setg(errp, "Root port does not support AER"); + return -ENOTSUP; + } + } + + parent_dev =3D pci_bridge_get_device(parent_dev->bus); + } + pcie_add_capability(dev, PCI_EXT_CAP_ID_ERR, cap_ver, offset, size); dev->exp.aer_cap =3D offset; --=20 1.8.3.1