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Violators will be prosecuted; Fri, 24 Feb 2017 01:27:00 +0530 Received: from d28relay05.in.ibm.com (d28relay05.in.ibm.com [9.184.220.62]) by d28dlp01.in.ibm.com (Postfix) with ESMTP id 4EEDFE005A; Fri, 24 Feb 2017 01:28:39 +0530 (IST) Received: from d28av02.in.ibm.com (d28av02.in.ibm.com [9.184.220.64]) by d28relay05.in.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v1NJuu1C11665516; Fri, 24 Feb 2017 01:26:56 +0530 Received: from d28av02.in.ibm.com (localhost [127.0.0.1]) by d28av02.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id v1NJuw9F024727; Fri, 24 Feb 2017 01:26:58 +0530 Received: from abhimanyu.in.ibm.com ([9.102.3.191]) by d28av02.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id v1NJurVO024530; Fri, 24 Feb 2017 01:26:57 +0530 From: Nikunj A Dadhania To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net Date: Fri, 24 Feb 2017 01:26:32 +0530 X-Mailer: git-send-email 2.7.4 In-Reply-To: <1487879800-12352-1-git-send-email-nikunj@linux.vnet.ibm.com> References: <1487879800-12352-1-git-send-email-nikunj@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 17022319-0020-0000-0000-000000C1BB9E X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17022319-0021-0000-0000-0000027DC34B Message-Id: <1487879800-12352-8-git-send-email-nikunj@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-02-23_13:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1612050000 definitions=main-1702230177 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH v4 07/15] target/ppc: support for 32-bit carry and overflow X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com, bharata@linux.vnet.ibm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" POWER ISA 3.0 adds CA32 and OV32 status in 64-bit mode. Add the flags and corresponding defines. Moreover, CA32 is updated when CA is updated and OV32 is updated when OV is updated. Arithmetic instructions: * Addition and Substractions: addic, addic., subfic, addc, subfc, adde, subfe, addme, subfme, addze, and subfze always updates CA and CA32. =3D> CA reflects the carry out of bit 0 in 64-bit mode and out of bit 32 in 32-bit mode. =3D> CA32 reflects the carry out of bit 32 independent of the mode. =3D> SO and OV reflects overflow of the 64-bit result in 64-bit mode and overflow of the low-order 32-bit result in 32-bit mode =3D> OV32 reflects overflow of the low-order 32-bit independent of the mode * Multiply Low and Divide: For mulld, divd, divde, divdu and divdeu: SO, OV, and OV32 bits reflects overflow of the 64-bit result For mullw, divw, divwe, divwu and divweu: SO, OV, and OV32 bits reflects overflow of the 32-bit result * Negate with OE=3D1 (nego) For 64-bit mode if the register RA contains 0x8000_0000_0000_0000, OV and OV32 are set to 1. For 32-bit mode if the register RA contains 0x8000_0000, OV and OV32 are set to 1. Signed-off-by: Nikunj A Dadhania --- target/ppc/cpu.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index f1a7ca0..e789d4b 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1369,14 +1369,20 @@ int ppc_compat_max_threads(PowerPCCPU *cpu); #define XER_SO_BIT 31 #define XER_OV_BIT 30 #define XER_CA_BIT 29 +#define XER_OV32_BIT 19 +#define XER_CA32_BIT 18 #define XER_CMP_BIT 8 #define XER_BC_BIT 0 #define XER_SO (1 << XER_SO_BIT) #define XER_OV (1 << XER_OV_BIT) #define XER_CA (1 << XER_CA_BIT) +#define XER_OV32 (1 << XER_OV32_BIT) +#define XER_CA32 (1 << XER_CA32_BIT) #define xer_so ((env->xer & XER_SO) >> XER_SO_BIT) #define xer_ov ((env->xer & XER_OV) >> XER_OV_BIT) #define xer_ca ((env->xer & XER_CA) >> XER_CA_BIT) +#define xer_ov32 ((env->xer & XER_OV32) >> XER_OV32_BIT) +#define xer_ca32 ((env->xer & XER_CA32) >> XER_CA32_BIT) #define xer_cmp ((env->xer >> XER_CMP_BIT) & 0xFF) #define xer_bc ((env->xer >> XER_BC_BIT) & 0x7F) =20 @@ -2343,6 +2349,7 @@ enum { =20 /*************************************************************************= ****/ =20 +#define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300)) target_ulong cpu_read_xer(CPUPPCState *env); void cpu_write_xer(CPUPPCState *env, target_ulong xer); =20 --=20 2.7.4