From nobody Sun Feb 8 22:34:45 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1487883118019167.14270755225914; Thu, 23 Feb 2017 12:51:58 -0800 (PST) Received: from localhost ([::1]:32793 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ch0Mm-0001Dy-Pc for importer@patchew.org; Thu, 23 Feb 2017 15:51:56 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41240) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cgzVl-0005Mb-JI for qemu-devel@nongnu.org; Thu, 23 Feb 2017 14:57:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cgzVh-0001js-CK for qemu-devel@nongnu.org; Thu, 23 Feb 2017 14:57:09 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:37981) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cgzVh-0001jE-3K for qemu-devel@nongnu.org; Thu, 23 Feb 2017 14:57:05 -0500 Received: from pps.filterd (m0098404.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v1NJshXZ009646 for ; Thu, 23 Feb 2017 14:57:04 -0500 Received: from e28smtp02.in.ibm.com (e28smtp02.in.ibm.com [125.16.236.2]) by mx0a-001b2d01.pphosted.com with ESMTP id 28t6050x9v-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Thu, 23 Feb 2017 14:57:03 -0500 Received: from localhost by e28smtp02.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Fri, 24 Feb 2017 01:26:57 +0530 Received: from d28relay05.in.ibm.com (d28relay05.in.ibm.com [9.184.220.62]) by d28dlp01.in.ibm.com (Postfix) with ESMTP id 210F1E005A; Fri, 24 Feb 2017 01:28:37 +0530 (IST) Received: from d28av02.in.ibm.com (d28av02.in.ibm.com [9.184.220.64]) by d28relay05.in.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v1NJusTd11993270; Fri, 24 Feb 2017 01:26:54 +0530 Received: from d28av02.in.ibm.com (localhost [127.0.0.1]) by d28av02.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id v1NJuu7t024635; Fri, 24 Feb 2017 01:26:56 +0530 Received: from abhimanyu.in.ibm.com ([9.102.3.191]) by d28av02.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id v1NJurVL024530; Fri, 24 Feb 2017 01:26:55 +0530 From: Nikunj A Dadhania To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net Date: Fri, 24 Feb 2017 01:26:29 +0530 X-Mailer: git-send-email 2.7.4 In-Reply-To: <1487879800-12352-1-git-send-email-nikunj@linux.vnet.ibm.com> References: <1487879800-12352-1-git-send-email-nikunj@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 17022319-0004-0000-0000-00000542B84A X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17022319-0005-0000-0000-0000133CC051 Message-Id: <1487879800-12352-5-git-send-email-nikunj@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-02-23_13:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=2 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1612050000 definitions=main-1702230177 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 Subject: [Qemu-devel] [PATCH v4 04/15] target/ppc: add gen_op_update_ca_legacy() helper X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com, bharata@linux.vnet.ibm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Update cpu_ca using the helper routine. This will help in consolidating xer flags code Signed-off-by: Nikunj A Dadhania --- target/ppc/translate.c | 91 ++++++++++++++++++++++++++++++++++------------= ---- 1 file changed, 63 insertions(+), 28 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index b09e16f..ae7b43d 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -792,6 +792,11 @@ static void gen_cmpb(DisasContext *ctx) =20 /*** Integer arithmetic = ***/ =20 +static inline void gen_op_update_ca_legacy(TCGv ca) +{ + tcg_gen_mov_tl(cpu_ca, ca); +} + static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub) { @@ -818,11 +823,16 @@ static inline void gen_op_arith_add(DisasContext *ctx= , TCGv ret, TCGv arg1, bool compute_ov, bool compute_rc0) { TCGv t0 =3D ret; + TCGv ca =3D tcg_temp_new(); =20 if (compute_ca || compute_ov) { t0 =3D tcg_temp_new(); } =20 + if (add_ca) { + tcg_gen_mov_tl(ca, cpu_ca); + } + if (compute_ca) { if (NARROW_MODE(ctx)) { /* Caution: a non-obvious corner case of the spec is that we @@ -832,32 +842,34 @@ static inline void gen_op_arith_add(DisasContext *ctx= , TCGv ret, TCGv arg1, tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ tcg_gen_add_tl(t0, arg1, arg2); if (add_ca) { - tcg_gen_add_tl(t0, t0, cpu_ca); + tcg_gen_add_tl(t0, t0, ca); } - tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carr= y */ + tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ tcg_temp_free(t1); - tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */ - tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); + tcg_gen_extract_tl(ca, ca, 32, 1); } else { TCGv zero =3D tcg_const_tl(0); if (add_ca) { - tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero); - tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero); + tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); + tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); } else { - tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero); + tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); } tcg_temp_free(zero); } } else { tcg_gen_add_tl(t0, arg1, arg2); if (add_ca) { - tcg_gen_add_tl(t0, t0, cpu_ca); + tcg_gen_add_tl(t0, t0, ca); } } =20 if (compute_ov) { gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); } + if (compute_ca) { + gen_op_update_ca_legacy(ca); + } if (unlikely(compute_rc0)) { gen_set_Rc0(ctx, t0); } @@ -866,6 +878,7 @@ static inline void gen_op_arith_add(DisasContext *ctx, = TCGv ret, TCGv arg1, tcg_gen_mov_tl(ret, t0); tcg_temp_free(t0); } + tcg_temp_free(ca); } /* Add functions with two operands */ #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) = \ @@ -1327,10 +1340,14 @@ static inline void gen_op_arith_subf(DisasContext *= ctx, TCGv ret, TCGv arg1, bool compute_ov, bool compute_rc0) { TCGv t0 =3D ret; + TCGv ca =3D tcg_temp_new(); =20 if (compute_ca || compute_ov) { t0 =3D tcg_temp_new(); } + if (add_ca) { + tcg_gen_extract_tl(ca, cpu_xer, XER_CA_BIT, 1); + } =20 if (compute_ca) { /* dest =3D ~arg1 + arg2 [+ ca]. */ @@ -1342,34 +1359,33 @@ static inline void gen_op_arith_subf(DisasContext *= ctx, TCGv ret, TCGv arg1, TCGv t1 =3D tcg_temp_new(); tcg_gen_not_tl(inv1, arg1); if (add_ca) { - tcg_gen_add_tl(t0, arg2, cpu_ca); + tcg_gen_add_tl(t0, arg2, ca); } else { tcg_gen_addi_tl(t0, arg2, 1); } tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ tcg_gen_add_tl(t0, t0, inv1); tcg_temp_free(inv1); - tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ car= ry */ + tcg_gen_xor_tl(ca, t0, t1); /* bits changes w/ carry */ tcg_temp_free(t1); - tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */ - tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); + tcg_gen_extract_tl(ca, ca, 32, 1); /* extract bit 32 */ } else if (add_ca) { TCGv zero, inv1 =3D tcg_temp_new(); tcg_gen_not_tl(inv1, arg1); zero =3D tcg_const_tl(0); - tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); - tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); + tcg_gen_add2_tl(t0, ca, arg2, zero, ca, zero); + tcg_gen_add2_tl(t0, ca, t0, ca, inv1, zero); tcg_temp_free(zero); tcg_temp_free(inv1); } else { - tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); + tcg_gen_setcond_tl(TCG_COND_GEU, ca, arg2, arg1); tcg_gen_sub_tl(t0, arg2, arg1); } } else if (add_ca) { /* Since we're ignoring carry-out, we can simplify the standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */ tcg_gen_sub_tl(t0, arg2, arg1); - tcg_gen_add_tl(t0, t0, cpu_ca); + tcg_gen_add_tl(t0, t0, ca); tcg_gen_subi_tl(t0, t0, 1); } else { tcg_gen_sub_tl(t0, arg2, arg1); @@ -1378,6 +1394,9 @@ static inline void gen_op_arith_subf(DisasContext *ct= x, TCGv ret, TCGv arg1, if (compute_ov) { gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); } + if (compute_ca) { + gen_op_update_ca_legacy(ca); + } if (unlikely(compute_rc0)) { gen_set_Rc0(ctx, t0); } @@ -1386,6 +1405,7 @@ static inline void gen_op_arith_subf(DisasContext *ct= x, TCGv ret, TCGv arg1, tcg_gen_mov_tl(ret, t0); tcg_temp_free(t0); } + tcg_temp_free(ca); } /* Sub functions with Two operands functions */ #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) = \ @@ -2119,23 +2139,27 @@ static void gen_srawi(DisasContext *ctx) int sh =3D SH(ctx->opcode); TCGv dst =3D cpu_gpr[rA(ctx->opcode)]; TCGv src =3D cpu_gpr[rS(ctx->opcode)]; + TCGv ca =3D tcg_temp_new(); + if (sh =3D=3D 0) { tcg_gen_ext32s_tl(dst, src); - tcg_gen_movi_tl(cpu_ca, 0); + tcg_gen_movi_tl(ca, 0); } else { TCGv t0; tcg_gen_ext32s_tl(dst, src); - tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); + tcg_gen_andi_tl(ca, dst, (1ULL << sh) - 1); t0 =3D tcg_temp_new(); tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); - tcg_gen_and_tl(cpu_ca, cpu_ca, t0); + tcg_gen_and_tl(ca, ca, t0); tcg_temp_free(t0); - tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); + tcg_gen_setcondi_tl(TCG_COND_NE, ca, ca, 0); tcg_gen_sari_tl(dst, dst, sh); } if (unlikely(Rc(ctx->opcode) !=3D 0)) { gen_set_Rc0(ctx, dst); } + gen_op_update_ca_legacy(ca); + tcg_temp_free(ca); } =20 /* srw & srw. */ @@ -2197,22 +2221,25 @@ static inline void gen_sradi(DisasContext *ctx, int= n) int sh =3D SH(ctx->opcode) + (n << 5); TCGv dst =3D cpu_gpr[rA(ctx->opcode)]; TCGv src =3D cpu_gpr[rS(ctx->opcode)]; + TCGv ca =3D tcg_temp_new(); if (sh =3D=3D 0) { tcg_gen_mov_tl(dst, src); - tcg_gen_movi_tl(cpu_ca, 0); + tcg_gen_movi_tl(ca, 0); } else { TCGv t0; - tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); + tcg_gen_andi_tl(ca, src, (1ULL << sh) - 1); t0 =3D tcg_temp_new(); tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); - tcg_gen_and_tl(cpu_ca, cpu_ca, t0); + tcg_gen_and_tl(ca, ca, t0); tcg_temp_free(t0); - tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); + tcg_gen_setcondi_tl(TCG_COND_NE, ca, ca, 0); tcg_gen_sari_tl(dst, src, sh); } if (unlikely(Rc(ctx->opcode) !=3D 0)) { gen_set_Rc0(ctx, dst); } + gen_op_update_ca_legacy(ca); + tcg_temp_free(ca); } =20 static void gen_sradi0(DisasContext *ctx) @@ -4990,16 +5017,20 @@ static void gen_sraiq(DisasContext *ctx) TCGLabel *l1 =3D gen_new_label(); TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); + TCGv ca =3D tcg_temp_local_new(); + tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); tcg_gen_or_tl(t0, t0, t1); gen_store_spr(SPR_MQ, t0); - tcg_gen_movi_tl(cpu_ca, 0); + tcg_gen_movi_tl(ca, 0); tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); - tcg_gen_movi_tl(cpu_ca, 1); + tcg_gen_movi_tl(ca, 1); gen_set_label(l1); tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh= ); + gen_op_update_ca_legacy(ca); + tcg_temp_free(ca); tcg_temp_free(t0); tcg_temp_free(t1); if (unlikely(Rc(ctx->opcode) !=3D 0)) @@ -5014,6 +5045,8 @@ static void gen_sraq(DisasContext *ctx) TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_local_new(); TCGv t2 =3D tcg_temp_local_new(); + TCGv ca =3D tcg_temp_local_new(); + tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); @@ -5028,11 +5061,13 @@ static void gen_sraq(DisasContext *ctx) gen_set_label(l1); tcg_temp_free(t0); tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); - tcg_gen_movi_tl(cpu_ca, 0); + tcg_gen_movi_tl(ca, 0); tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); - tcg_gen_movi_tl(cpu_ca, 1); + tcg_gen_movi_tl(ca, 1); gen_set_label(l2); + gen_op_update_ca_legacy(ca); + tcg_temp_free(ca); tcg_temp_free(t1); tcg_temp_free(t2); if (unlikely(Rc(ctx->opcode) !=3D 0)) --=20 2.7.4