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[158.140.1.28]) by smtp.gmail.com with ESMTPSA id p66sm11132334pfb.88.2017.02.23.10.53.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 23 Feb 2017 10:53:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=7azVcQ54QstrUp5WBYjMSLyiEWehgz51ixQj/9YzxFI=; b=BNKDgXLxrWZRPR83P2oiUl5mqgExcb7s1Lf84zKKZXnZYA7JVepMfGHfV22yZ8ULtJ dHFUHRuXh7GAspNKRXYM1pn5+GZgg5LZepoQVtJe9pHkJrQgzKwiV4uiOVPptWjt1Zaa WRhn5ugBvBm8LD0LpuMHJPmWgGN8vHtlJzoeocYWbcCSePoUpZMUFGufLucaMxFASGfa GqNCEXfRb9449+X/hEE6leUcm9NQ7SllEtbV12+xnxC7SP8+9LE4Ja4Q9xL5QO1zgAbX /m2SocNsImaDNwec9yh0OiqX1JVr/6IFqlYtQem7WNdDN+CNSOdWEDalKF61OZekh8db +cHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=7azVcQ54QstrUp5WBYjMSLyiEWehgz51ixQj/9YzxFI=; b=M5tK4cMlPQ6XDWjpUkjTqoOz3u73GuvC2LiRHu1FF8ZFdWgCgyNTZe1yN5WZ57opuA /riSxvdeFEWOWEwqVepZ8iSrMx2D3+SJc3RSZOoO/gm00q/tfln3Hy0lmZsZEfWbeXdX s2o+GMGZasY+4qi6Snc3AcpHBfoFG04ghsOp1odJrGpJQnJdxiKY34sdnH2m8Ie4mMEl 6RIGUdNyqEKDaUN66UGWj5kHuFNE+JICzHsbMcIkiHz5gj+GrT44MqZJ0wGqrHVIR1Ng Mn+6jqnbLmGt/hdAAhyBAMIxZuk/vGKxmWvrD6AB43/48+9g5Z1bYP6yrTlOY8qOn8ru Y63w== X-Gm-Message-State: AMke39mykRzWYGGTWFovNYuhQsxOOQsF2fS9jxt0VI9lgTmF6WeCij/r3DxoYKygIoI3MA== X-Received: by 10.99.112.75 with SMTP id a11mr49865012pgn.7.1487875985373; Thu, 23 Feb 2017 10:53:05 -0800 (PST) From: Max Filippov To: qemu-devel@nongnu.org Date: Thu, 23 Feb 2017 10:52:48 -0800 Message-Id: <1487875968-23454-1-git-send-email-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.1.4 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH] target/xtensa: sim: instantiate local memories X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Xtensa core may have a number of RAM and ROM areas configured. Record their size and location from the core configuration overlay and instantiate them as RAM regions in the SIM machine. Signed-off-by: Max Filippov --- hw/xtensa/sim.c | 40 ++++++++--- target/xtensa/cpu.h | 16 +++++ target/xtensa/overlay_tool.h | 160 +++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 207 insertions(+), 9 deletions(-) diff --git a/hw/xtensa/sim.c b/hw/xtensa/sim.c index 5e94004..d2d1d3a 100644 --- a/hw/xtensa/sim.c +++ b/hw/xtensa/sim.c @@ -37,6 +37,27 @@ #include "exec/address-spaces.h" #include "qemu/error-report.h" =20 +static void xtensa_create_memory_regions(const XtensaMemory *memory, + const char *name) +{ + unsigned i; + char *num_name =3D malloc(strlen(name) + sizeof(i) * 3 + 1); + + for (i =3D 0; i < memory->num; ++i) { + MemoryRegion *m; + + sprintf(num_name, "%s%u", name, i); + m =3D g_malloc(sizeof(*m)); + memory_region_init_ram(m, NULL, num_name, + memory->location[i].size, + &error_fatal); + vmstate_register_ram_global(m); + memory_region_add_subregion(get_system_memory(), + memory->location[i].addr, m); + } + free(num_name); +} + static uint64_t translate_phys_addr(void *opaque, uint64_t addr) { XtensaCPU *cpu =3D opaque; @@ -55,7 +76,6 @@ static void xtensa_sim_init(MachineState *machine) { XtensaCPU *cpu =3D NULL; CPUXtensaState *env =3D NULL; - MemoryRegion *ram, *rom; ram_addr_t ram_size =3D machine->ram_size; const char *cpu_model =3D machine->cpu_model; const char *kernel_filename =3D machine->kernel_filename; @@ -82,15 +102,17 @@ static void xtensa_sim_init(MachineState *machine) sim_reset(cpu); } =20 - ram =3D g_malloc(sizeof(*ram)); - memory_region_init_ram(ram, NULL, "xtensa.sram", ram_size, &error_fata= l); - vmstate_register_ram_global(ram); - memory_region_add_subregion(get_system_memory(), 0, ram); + if (env) { + XtensaMemory sysram =3D env->config->sysram; =20 - rom =3D g_malloc(sizeof(*rom)); - memory_region_init_ram(rom, NULL, "xtensa.rom", 0x1000, &error_fatal); - vmstate_register_ram_global(rom); - memory_region_add_subregion(get_system_memory(), 0xfe000000, rom); + sysram.location[0].size =3D ram_size; + xtensa_create_memory_regions(&env->config->instrom, "xtensa.instro= m"); + xtensa_create_memory_regions(&env->config->instram, "xtensa.instra= m"); + xtensa_create_memory_regions(&env->config->datarom, "xtensa.dataro= m"); + xtensa_create_memory_regions(&env->config->dataram, "xtensa.datara= m"); + xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom"= ); + xtensa_create_memory_regions(&sysram, "xtensa.sysram"); + } =20 if (kernel_filename) { uint64_t elf_entry; diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 7e7131a..ecca17d 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -212,6 +212,7 @@ enum { #define MAX_NCCOMPARE 3 #define MAX_TLB_WAY_SIZE 8 #define MAX_NDBREAK 2 +#define MAX_NMEMORY 4 =20 #define REGION_PAGE_MASK 0xe0000000 =20 @@ -321,6 +322,14 @@ typedef struct XtensaCcompareTimer { QEMUTimer *timer; } XtensaCcompareTimer; =20 +typedef struct XtensaMemory { + unsigned num; + struct XtensaMemoryRegion { + uint32_t addr; + uint32_t size; + } location[MAX_NMEMORY]; +} XtensaMemory; + struct XtensaConfig { const char *name; uint64_t options; @@ -352,6 +361,13 @@ struct XtensaConfig { unsigned dcache_ways; uint32_t memctl_mask; =20 + XtensaMemory instrom; + XtensaMemory instram; + XtensaMemory datarom; + XtensaMemory dataram; + XtensaMemory sysrom; + XtensaMemory sysram; + uint32_t configid[2]; =20 uint32_t clock_freq_khz; diff --git a/target/xtensa/overlay_tool.h b/target/xtensa/overlay_tool.h index 38e9be9..12bde44 100644 --- a/target/xtensa/overlay_tool.h +++ b/target/xtensa/overlay_tool.h @@ -318,6 +318,16 @@ .itlb =3D ITLB(XCHAL_HAVE_SPANNING_WAY), \ .dtlb =3D DTLB(XCHAL_HAVE_SPANNING_WAY) =20 +#ifndef XCHAL_SYSROM0_PADDR +#define XCHAL_SYSROM0_PADDR 0xfe000000 +#define XCHAL_SYSROM0_SIZE 0x02000000 +#endif + +#ifndef XCHAL_SYSRAM0_PADDR +#define XCHAL_SYSRAM0_PADDR 0x00000000 +#define XCHAL_SYSRAM0_SIZE 0x08000000 +#endif + #elif XCHAL_HAVE_XLT_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR =20 #define TLB_TEMPLATE { \ @@ -331,6 +341,28 @@ .itlb =3D TLB_TEMPLATE, \ .dtlb =3D TLB_TEMPLATE =20 +#ifndef XCHAL_SYSROM0_PADDR +#define XCHAL_SYSROM0_PADDR 0x60000000 +#define XCHAL_SYSROM0_SIZE 0x04000000 +#endif + +#ifndef XCHAL_SYSRAM0_PADDR +#define XCHAL_SYSRAM0_PADDR 0x50000000 +#define XCHAL_SYSRAM0_SIZE 0x04000000 +#endif + +#else + +#ifndef XCHAL_SYSROM0_PADDR +#define XCHAL_SYSROM0_PADDR 0x60000000 +#define XCHAL_SYSROM0_SIZE 0x04000000 +#endif + +#ifndef XCHAL_SYSRAM0_PADDR +#define XCHAL_SYSRAM0_PADDR 0x50000000 +#define XCHAL_SYSRAM0_SIZE 0x04000000 +#endif + #endif =20 #if (defined(TARGET_WORDS_BIGENDIAN) !=3D 0) =3D=3D (XCHAL_HAVE_BE !=3D 0) @@ -362,6 +394,53 @@ MEMCTL_ISNP | MEMCTL_DSNP | \ (XCHAL_HAVE_LOOPS && XCHAL_LOOP_BUFFER_SIZE ? MEMCTL_IL0EN : 0) =20 +#define MEM_LOCATION(name, n) \ + { \ + .addr =3D XCHAL_ ## name ## n ## _PADDR, \ + .size =3D XCHAL_ ## name ## n ## _SIZE, \ + } + +#define MEM_SECTIONS(name) \ + MEM_LOCATION(name, 0), \ + MEM_LOCATION(name, 1), \ + MEM_LOCATION(name, 2), \ + MEM_LOCATION(name, 3) + +#define MEM_SECTION(name) \ + .num =3D XCHAL_NUM_ ## name, \ + .location =3D { \ + MEM_SECTIONS(name) \ + } + +#define SYSMEM_SECTION(name) \ + .num =3D 1, \ + .location =3D { \ + { \ + .addr =3D XCHAL_ ## name ## 0_PADDR, \ + .size =3D XCHAL_ ## name ## 0_SIZE, \ + } \ + } + +#define LOCAL_MEMORIES_SECTION \ + .instrom =3D { \ + MEM_SECTION(INSTROM) \ + }, \ + .instram =3D { \ + MEM_SECTION(INSTRAM) \ + }, \ + .datarom =3D { \ + MEM_SECTION(DATAROM) \ + }, \ + .dataram =3D { \ + MEM_SECTION(DATARAM) \ + }, \ + .sysrom =3D { \ + SYSMEM_SECTION(SYSROM) \ + }, \ + .sysram =3D { \ + SYSMEM_SECTION(SYSRAM) \ + } + #define CONFIG_SECTION \ .configid =3D { \ XCHAL_HW_CONFIGID0, \ @@ -377,6 +456,7 @@ TLB_SECTION, \ DEBUG_SECTION, \ CACHE_SECTION, \ + LOCAL_MEMORIES_SECTION, \ CONFIG_SECTION =20 =20 @@ -629,3 +709,83 @@ =20 =20 #define XTHAL_TIMER_UNCONFIGURED 0 + +#if XCHAL_NUM_INSTROM < 1 +#define XCHAL_INSTROM0_PADDR 0 +#define XCHAL_INSTROM0_SIZE 0 +#endif +#if XCHAL_NUM_INSTROM < 2 +#define XCHAL_INSTROM1_PADDR 0 +#define XCHAL_INSTROM1_SIZE 0 +#endif +#if XCHAL_NUM_INSTROM < 3 +#define XCHAL_INSTROM2_PADDR 0 +#define XCHAL_INSTROM2_SIZE 0 +#endif +#if XCHAL_NUM_INSTROM < 4 +#define XCHAL_INSTROM3_PADDR 0 +#define XCHAL_INSTROM3_SIZE 0 +#endif +#if XCHAL_NUM_INSTROM > MAX_NMEMORY +#error XCHAL_NUM_INSTROM > MAX_NMEMORY +#endif + +#if XCHAL_NUM_INSTRAM < 1 +#define XCHAL_INSTRAM0_PADDR 0 +#define XCHAL_INSTRAM0_SIZE 0 +#endif +#if XCHAL_NUM_INSTRAM < 2 +#define XCHAL_INSTRAM1_PADDR 0 +#define XCHAL_INSTRAM1_SIZE 0 +#endif +#if XCHAL_NUM_INSTRAM < 3 +#define XCHAL_INSTRAM2_PADDR 0 +#define XCHAL_INSTRAM2_SIZE 0 +#endif +#if XCHAL_NUM_INSTRAM < 4 +#define XCHAL_INSTRAM3_PADDR 0 +#define XCHAL_INSTRAM3_SIZE 0 +#endif +#if XCHAL_NUM_INSTRAM > MAX_NMEMORY +#error XCHAL_NUM_INSTRAM > MAX_NMEMORY +#endif + +#if XCHAL_NUM_DATAROM < 1 +#define XCHAL_DATAROM0_PADDR 0 +#define XCHAL_DATAROM0_SIZE 0 +#endif +#if XCHAL_NUM_DATAROM < 2 +#define XCHAL_DATAROM1_PADDR 0 +#define XCHAL_DATAROM1_SIZE 0 +#endif +#if XCHAL_NUM_DATAROM < 3 +#define XCHAL_DATAROM2_PADDR 0 +#define XCHAL_DATAROM2_SIZE 0 +#endif +#if XCHAL_NUM_DATAROM < 4 +#define XCHAL_DATAROM3_PADDR 0 +#define XCHAL_DATAROM3_SIZE 0 +#endif +#if XCHAL_NUM_DATAROM > MAX_NMEMORY +#error XCHAL_NUM_DATAROM > MAX_NMEMORY +#endif + +#if XCHAL_NUM_DATARAM < 1 +#define XCHAL_DATARAM0_PADDR 0 +#define XCHAL_DATARAM0_SIZE 0 +#endif +#if XCHAL_NUM_DATARAM < 2 +#define XCHAL_DATARAM1_PADDR 0 +#define XCHAL_DATARAM1_SIZE 0 +#endif +#if XCHAL_NUM_DATARAM < 3 +#define XCHAL_DATARAM2_PADDR 0 +#define XCHAL_DATARAM2_SIZE 0 +#endif +#if XCHAL_NUM_DATARAM < 4 +#define XCHAL_DATARAM3_PADDR 0 +#define XCHAL_DATARAM3_SIZE 0 +#endif +#if XCHAL_NUM_DATARAM > MAX_NMEMORY +#error XCHAL_NUM_DATARAM > MAX_NMEMORY +#endif --=20 2.1.4