From nobody Sat Apr 27 16:17:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1487685391091504.53316904255746; Tue, 21 Feb 2017 05:56:31 -0800 (PST) Received: from localhost ([::1]:45433 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cgAvd-0007yQ-II for importer@patchew.org; Tue, 21 Feb 2017 08:56:29 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36969) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cgAZh-000451-OT for qemu-devel@nongnu.org; Tue, 21 Feb 2017 08:33:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cgAZg-0001QC-UC for qemu-devel@nongnu.org; Tue, 21 Feb 2017 08:33:49 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:48627) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cgAZg-0001Pw-JU for qemu-devel@nongnu.org; Tue, 21 Feb 2017 08:33:48 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1cgAZa-0006KY-30; Tue, 21 Feb 2017 13:33:42 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 21 Feb 2017 13:33:41 +0000 Message-Id: <1487684021-22713-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH] hw/ppc/ppc405_uc.c: Avoid integer overflows X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Gibson , qemu-ppc@nongnu.org, Alexander Graf , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When performing clock calculations, the ppc405_uc code has several places where it multiplies together two 32-bit variables and assigns the result to a 64-bit variable. This doesn't quite do what is intended because C will compute a 32-bit multiply result. Add casts to ensure we don't truncate the result. (Spotted by Coverity, CID 1005504, 1005505.) Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/ppc/ppc405_uc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index d6d3fc2..d5df94a 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -1881,7 +1881,7 @@ static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc) D1 =3D (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */ D2 =3D 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */ M =3D D0 * D1 * D2; - VCO_out =3D cpc->sysclk * M; + VCO_out =3D (uint64_t)cpc->sysclk * M; if (VCO_out < 400000000 || VCO_out > 800000000) { /* PLL cannot lock */ cpc->pllmr &=3D ~0x80000000; @@ -1892,7 +1892,7 @@ static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc) /* Bypass PLL */ bypass_pll: M =3D D0; - PLL_out =3D cpc->sysclk * M; + PLL_out =3D (uint64_t)cpc->sysclk * M; } CPU_clk =3D PLL_out; if (cpc->cr1 & 0x00800000) @@ -2242,7 +2242,7 @@ static void ppc405ep_compute_clocks (ppc405ep_cpc_t *= cpc) #ifdef DEBUG_CLOCKS_LL printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D); #endif - VCO_out =3D cpc->sysclk * M * D; + VCO_out =3D (uint64_t)cpc->sysclk * M * D; if (VCO_out < 500000000UL || VCO_out > 1000000000UL) { /* Error - unlock the PLL */ printf("VCO out of range %" PRIu64 "\n", VCO_out); --=20 2.7.4