From nobody Mon Apr 29 07:32:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1487623669870585.2599133311246; Mon, 20 Feb 2017 12:47:49 -0800 (PST) Received: from localhost ([::1]:41009 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cfus8-0004iH-AA for importer@patchew.org; Mon, 20 Feb 2017 15:47:48 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38980) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cfunt-0001a5-Ru for qemu-devel@nongnu.org; Mon, 20 Feb 2017 15:43:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cfuns-0008VR-Tc for qemu-devel@nongnu.org; Mon, 20 Feb 2017 15:43:25 -0500 Received: from mx1.redhat.com ([209.132.183.28]:34272) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cfuns-0008Uc-No for qemu-devel@nongnu.org; Mon, 20 Feb 2017 15:43:24 -0500 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id D2BD68047A for ; Mon, 20 Feb 2017 20:43:24 +0000 (UTC) Received: from work.redhat.com (ovpn-116-63.ams2.redhat.com [10.36.116.63]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id v1KKhGNr027258; Mon, 20 Feb 2017 15:43:21 -0500 From: Marcel Apfelbaum To: qemu-devel@nongnu.org Date: Mon, 20 Feb 2017 22:43:10 +0200 Message-Id: <1487623393-2492-2-git-send-email-marcel@redhat.com> In-Reply-To: <1487623393-2492-1-git-send-email-marcel@redhat.com> References: <1487623393-2492-1-git-send-email-marcel@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Mon, 20 Feb 2017 20:43:24 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH V2 1/4] hw/pcie: fix Extended Configuration Space for devices with no Extended Capabilities X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marcel@redhat.com, mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Absence of any Extended Capabilities is required to be indicated by an Extended Capability header with a Capability ID of 0000h, a Capability Version of 0h, and a Next Capability Offset of 000h. Instead of inserting a 'NULL' capability is simpler to mark the start of the Extended Configuration Space as read-only to achieve the same behaviour. Signed-off-by: Marcel Apfelbaum --- hw/pci/pci.c | 2 ++ hw/pci/pcie.c | 6 ++++++ include/hw/compat.h | 4 ++++ include/hw/pci/pci.h | 2 ++ 4 files changed, 14 insertions(+) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index a563555..4d2c0e1 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -64,6 +64,8 @@ static Property pci_props[] =3D { QEMU_PCI_CAP_SERR_BITNR, true), DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present, QEMU_PCIE_LNKSTA_DLLLA_BITNR, true), + DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice, cap_present, + QEMU_PCIE_EXTCAP_INIT_BITNR, true), DEFINE_PROP_END_OF_LIST() }; =20 diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index cbd4bb4..2526e3a 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -109,6 +109,12 @@ int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint= 8_t type, uint8_t port) PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP); =20 pci_set_word(dev->wmask + pos + PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_EETLP= PB); + + if (dev->cap_present & QEMU_PCIE_EXTCAP_INIT) { + /* read-only to behave like a 'NULL' Extended Capability Header */ + pci_set_long(dev->wmask + PCI_CONFIG_SPACE_SIZE, 0); + } + return pos; } =20 diff --git a/include/hw/compat.h b/include/hw/compat.h index b7db438..ce3bfe3 100644 --- a/include/hw/compat.h +++ b/include/hw/compat.h @@ -18,6 +18,10 @@ .driver =3D "pci-bridge",\ .property =3D "shpc",\ .value =3D "on",\ + },{\ + .driver =3D TYPE_PCI_DEVICE,\ + .property =3D "x-pcie-extcap-init",\ + .value =3D "off",\ }, =20 #define HW_COMPAT_2_7 \ diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index cbc1fdf..ded978c 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -182,6 +182,8 @@ enum { /* Link active status in endpoint capability is always set */ #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8 QEMU_PCIE_LNKSTA_DLLLA =3D (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR), +#define QEMU_PCIE_EXTCAP_INIT_BITNR 9 + QEMU_PCIE_EXTCAP_INIT =3D (1 << QEMU_PCIE_EXTCAP_INIT_BITNR), }; =20 #define TYPE_PCI_DEVICE "pci-device" --=20 2.5.5 From nobody Mon Apr 29 07:32:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1487623902289959.7646659295366; Mon, 20 Feb 2017 12:51:42 -0800 (PST) Received: from localhost ([::1]:41028 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cfuvm-0007Va-SQ for importer@patchew.org; Mon, 20 Feb 2017 15:51:34 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38996) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cfunw-0001cI-EM for qemu-devel@nongnu.org; Mon, 20 Feb 2017 15:43:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cfunv-00005J-I0 for qemu-devel@nongnu.org; Mon, 20 Feb 2017 15:43:28 -0500 Received: from mx1.redhat.com ([209.132.183.28]:56932) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cfunv-0008WR-9D for qemu-devel@nongnu.org; Mon, 20 Feb 2017 15:43:27 -0500 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 6C0524E4D8 for ; Mon, 20 Feb 2017 20:43:27 +0000 (UTC) Received: from work.redhat.com (ovpn-116-63.ams2.redhat.com [10.36.116.63]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id v1KKhGNs027258; Mon, 20 Feb 2017 15:43:25 -0500 From: Marcel Apfelbaum To: qemu-devel@nongnu.org Date: Mon, 20 Feb 2017 22:43:11 +0200 Message-Id: <1487623393-2492-3-git-send-email-marcel@redhat.com> In-Reply-To: <1487623393-2492-1-git-send-email-marcel@redhat.com> References: <1487623393-2492-1-git-send-email-marcel@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Mon, 20 Feb 2017 20:43:27 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH V2 2/4] hw/virtio: fix error enabling flags in Device Control register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marcel@redhat.com, mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When the virtio devices are PCI Express, make error-enabling flags writable to respect the PCIe spec. Signed-off-by: Marcel Apfelbaum --- hw/virtio/virtio-pci.c | 12 ++++++++++++ hw/virtio/virtio-pci.h | 4 ++++ include/hw/compat.h | 4 ++++ 3 files changed, 20 insertions(+) diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index 5ce42af..9e2bca6 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -1819,6 +1819,11 @@ static void virtio_pci_realize(PCIDevice *pci_dev, E= rror **errp) */ pci_set_word(pci_dev->config + pos + PCI_PM_PMC, 0x3); =20 + if (proxy->flags & VIRTIO_PCI_FLAG_INIT_DEVERR) { + /* Init error enabling flags */ + pcie_cap_deverr_init(pci_dev); + } + if (proxy->flags & VIRTIO_PCI_FLAG_ATS) { pcie_ats_init(pci_dev, 256); } @@ -1849,6 +1854,7 @@ static void virtio_pci_reset(DeviceState *qdev) { VirtIOPCIProxy *proxy =3D VIRTIO_PCI(qdev); VirtioBusState *bus =3D VIRTIO_BUS(&proxy->bus); + PCIDevice *dev =3D PCI_DEVICE(qdev); int i; =20 virtio_pci_stop_ioeventfd(proxy); @@ -1858,6 +1864,10 @@ static void virtio_pci_reset(DeviceState *qdev) for (i =3D 0; i < VIRTIO_QUEUE_MAX; i++) { proxy->vqs[i].enabled =3D 0; } + + if (pci_is_express(dev)) { + pcie_cap_deverr_reset(dev); + } } =20 static Property virtio_pci_properties[] =3D { @@ -1878,6 +1888,8 @@ static Property virtio_pci_properties[] =3D { ignore_backend_features, false), DEFINE_PROP_BIT("ats", VirtIOPCIProxy, flags, VIRTIO_PCI_FLAG_ATS_BIT, false), + DEFINE_PROP_BIT("x-pcie-deverr-init", VirtIOPCIProxy, flags, + VIRTIO_PCI_FLAG_INIT_DEVERR_BIT, true), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/hw/virtio/virtio-pci.h b/hw/virtio/virtio-pci.h index d00064c..120661d 100644 --- a/hw/virtio/virtio-pci.h +++ b/hw/virtio/virtio-pci.h @@ -73,6 +73,7 @@ enum { VIRTIO_PCI_FLAG_DISABLE_PCIE_BIT, VIRTIO_PCI_FLAG_PAGE_PER_VQ_BIT, VIRTIO_PCI_FLAG_ATS_BIT, + VIRTIO_PCI_FLAG_INIT_DEVERR_BIT, }; =20 /* Need to activate work-arounds for buggy guests at vmstate load. */ @@ -100,6 +101,9 @@ enum { /* address space translation service */ #define VIRTIO_PCI_FLAG_ATS (1 << VIRTIO_PCI_FLAG_ATS_BIT) =20 +/* Init error enabling flags */ +#define VIRTIO_PCI_FLAG_INIT_DEVERR (1 << VIRTIO_PCI_FLAG_INIT_DEVERR_BIT) + typedef struct { MSIMessage msg; int virq; diff --git a/include/hw/compat.h b/include/hw/compat.h index ce3bfe3..c98776a 100644 --- a/include/hw/compat.h +++ b/include/hw/compat.h @@ -22,6 +22,10 @@ .driver =3D TYPE_PCI_DEVICE,\ .property =3D "x-pcie-extcap-init",\ .value =3D "off",\ + },{\ + .driver =3D "virtio-pci",\ + .property =3D "x-pcie-deverr-init",\ + .value =3D "off",\ }, =20 #define HW_COMPAT_2_7 \ --=20 2.5.5 From nobody Mon Apr 29 07:32:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1487623905715759.3861279029684; Mon, 20 Feb 2017 12:51:45 -0800 (PST) Received: from localhost ([::1]:41029 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cfuvw-0007cZ-Fu for importer@patchew.org; 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Mon, 20 Feb 2017 15:43:27 -0500 From: Marcel Apfelbaum To: qemu-devel@nongnu.org Date: Mon, 20 Feb 2017 22:43:12 +0200 Message-Id: <1487623393-2492-4-git-send-email-marcel@redhat.com> In-Reply-To: <1487623393-2492-1-git-send-email-marcel@redhat.com> References: <1487623393-2492-1-git-send-email-marcel@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Mon, 20 Feb 2017 20:43:29 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH V2 3/4] hw/virtio: fix Link Control Register for PCI Express virtio devices X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marcel@redhat.com, mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Make several Link Control Register flags writable to conform with the PCI Express spec. Signed-off-by: Marcel Apfelbaum --- hw/pci/pcie.c | 14 ++++++++++++++ hw/virtio/virtio-pci.c | 8 ++++++++ hw/virtio/virtio-pci.h | 4 ++++ include/hw/compat.h | 4 ++++ include/hw/pci/pcie.h | 3 +++ 5 files changed, 33 insertions(+) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 2526e3a..1804163 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -223,6 +223,20 @@ void pcie_cap_deverr_reset(PCIDevice *dev) PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE= ); } =20 +void pcie_cap_lnkctl_init(PCIDevice *dev) +{ + uint32_t pos =3D dev->exp.exp_cap; + pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_ES); +} + +void pcie_cap_lnkctl_reset(PCIDevice *dev) +{ + uint8_t *lnkctl =3D dev->config + dev->exp.exp_cap + PCI_EXP_LNKCTL; + pci_long_test_and_clear_mask(lnkctl, + PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_ES); +} + static void hotplug_event_update_event_status(PCIDevice *dev) { uint32_t pos =3D dev->exp.exp_cap; diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index 9e2bca6..1fb0a03 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -1824,6 +1824,11 @@ static void virtio_pci_realize(PCIDevice *pci_dev, E= rror **errp) pcie_cap_deverr_init(pci_dev); } =20 + if (proxy->flags & VIRTIO_PCI_FLAG_INIT_LNKCTL) { + /* Init Link Control Register */ + pcie_cap_lnkctl_init(pci_dev); + } + if (proxy->flags & VIRTIO_PCI_FLAG_ATS) { pcie_ats_init(pci_dev, 256); } @@ -1867,6 +1872,7 @@ static void virtio_pci_reset(DeviceState *qdev) =20 if (pci_is_express(dev)) { pcie_cap_deverr_reset(dev); + pcie_cap_lnkctl_reset(dev); } } =20 @@ -1890,6 +1896,8 @@ static Property virtio_pci_properties[] =3D { VIRTIO_PCI_FLAG_ATS_BIT, false), DEFINE_PROP_BIT("x-pcie-deverr-init", VirtIOPCIProxy, flags, VIRTIO_PCI_FLAG_INIT_DEVERR_BIT, true), + DEFINE_PROP_BIT("x-pcie-lnkctl-init", VirtIOPCIProxy, flags, + VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT, true), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/hw/virtio/virtio-pci.h b/hw/virtio/virtio-pci.h index 120661d..9b5dd5a 100644 --- a/hw/virtio/virtio-pci.h +++ b/hw/virtio/virtio-pci.h @@ -74,6 +74,7 @@ enum { VIRTIO_PCI_FLAG_PAGE_PER_VQ_BIT, VIRTIO_PCI_FLAG_ATS_BIT, VIRTIO_PCI_FLAG_INIT_DEVERR_BIT, + VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT, }; =20 /* Need to activate work-arounds for buggy guests at vmstate load. */ @@ -104,6 +105,9 @@ enum { /* Init error enabling flags */ #define VIRTIO_PCI_FLAG_INIT_DEVERR (1 << VIRTIO_PCI_FLAG_INIT_DEVERR_BIT) =20 +/* Init Link Control register */ +#define VIRTIO_PCI_FLAG_INIT_LNKCTL (1 << VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT) + typedef struct { MSIMessage msg; int virq; diff --git a/include/hw/compat.h b/include/hw/compat.h index c98776a..0931aa5 100644 --- a/include/hw/compat.h +++ b/include/hw/compat.h @@ -26,6 +26,10 @@ .driver =3D "virtio-pci",\ .property =3D "x-pcie-deverr-init",\ .value =3D "off",\ + },{\ + .driver =3D "virtio-pci",\ + .property =3D "x-pcie-lnkctl-init",\ + .value =3D "off",\ }, =20 #define HW_COMPAT_2_7 \ diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h index 163c519..11c6247 100644 --- a/include/hw/pci/pcie.h +++ b/include/hw/pci/pcie.h @@ -96,6 +96,9 @@ uint8_t pcie_cap_flags_get_vector(PCIDevice *dev); void pcie_cap_deverr_init(PCIDevice *dev); void pcie_cap_deverr_reset(PCIDevice *dev); =20 +void pcie_cap_lnkctl_init(PCIDevice *dev); +void pcie_cap_lnkctl_reset(PCIDevice *dev); + void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot); void pcie_cap_slot_reset(PCIDevice *dev); void pcie_cap_slot_write_config(PCIDevice *dev, --=20 2.5.5 From nobody Mon Apr 29 07:32:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1487624076616716.4690457761852; Mon, 20 Feb 2017 12:54:36 -0800 (PST) Received: from localhost ([::1]:41042 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cfuyh-0001je-5m for importer@patchew.org; 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Mon, 20 Feb 2017 15:43:30 -0500 From: Marcel Apfelbaum To: qemu-devel@nongnu.org Date: Mon, 20 Feb 2017 22:43:13 +0200 Message-Id: <1487623393-2492-5-git-send-email-marcel@redhat.com> In-Reply-To: <1487623393-2492-1-git-send-email-marcel@redhat.com> References: <1487623393-2492-1-git-send-email-marcel@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.39]); Mon, 20 Feb 2017 20:43:32 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH V2 4/4] hw/virtio: fix Power Management Control Register for PCI Express virtio devices X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marcel@redhat.com, mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Make Power Management State flag writable to conform with the PCI Express spec. Signed-off-by: Marcel Apfelbaum --- hw/virtio/virtio-pci.c | 11 +++++++++++ hw/virtio/virtio-pci.h | 4 ++++ include/hw/compat.h | 4 ++++ include/hw/pci/pcie.h | 2 ++ 4 files changed, 21 insertions(+) diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index 1fb0a03..fb86e58 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -1812,6 +1812,7 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Er= ror **errp) =20 pos =3D pci_add_capability(pci_dev, PCI_CAP_ID_PM, 0, PCI_PM_SIZEO= F); assert(pos > 0); + pci_dev->exp.pm_cap =3D pos; =20 /* * Indicates that this function complies with revision 1.2 of the @@ -1829,6 +1830,12 @@ static void virtio_pci_realize(PCIDevice *pci_dev, E= rror **errp) pcie_cap_lnkctl_init(pci_dev); } =20 + if (proxy->flags & VIRTIO_PCI_FLAG_INIT_PM) { + /* Init Power Management Control Register */ + pci_set_word(pci_dev->wmask + pos + PCI_PM_CTRL, + PCI_PM_CTRL_STATE_MASK); + } + if (proxy->flags & VIRTIO_PCI_FLAG_ATS) { pcie_ats_init(pci_dev, 256); } @@ -1873,6 +1880,8 @@ static void virtio_pci_reset(DeviceState *qdev) if (pci_is_express(dev)) { pcie_cap_deverr_reset(dev); pcie_cap_lnkctl_reset(dev); + + pci_set_word(dev->config + dev->exp.pm_cap + PCI_PM_CTRL, 0); } } =20 @@ -1898,6 +1907,8 @@ static Property virtio_pci_properties[] =3D { VIRTIO_PCI_FLAG_INIT_DEVERR_BIT, true), DEFINE_PROP_BIT("x-pcie-lnkctl-init", VirtIOPCIProxy, flags, VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT, true), + DEFINE_PROP_BIT("x-pcie-pm-init", VirtIOPCIProxy, flags, + VIRTIO_PCI_FLAG_INIT_PM_BIT, true), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/hw/virtio/virtio-pci.h b/hw/virtio/virtio-pci.h index 9b5dd5a..b095dfc 100644 --- a/hw/virtio/virtio-pci.h +++ b/hw/virtio/virtio-pci.h @@ -75,6 +75,7 @@ enum { VIRTIO_PCI_FLAG_ATS_BIT, VIRTIO_PCI_FLAG_INIT_DEVERR_BIT, VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT, + VIRTIO_PCI_FLAG_INIT_PM_BIT, }; =20 /* Need to activate work-arounds for buggy guests at vmstate load. */ @@ -108,6 +109,9 @@ enum { /* Init Link Control register */ #define VIRTIO_PCI_FLAG_INIT_LNKCTL (1 << VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT) =20 +/* Init Power Management */ +#define VIRTIO_PCI_FLAG_INIT_PM (1 << VIRTIO_PCI_FLAG_INIT_PM_BIT) + typedef struct { MSIMessage msg; int virq; diff --git a/include/hw/compat.h b/include/hw/compat.h index 0931aa5..90606f9 100644 --- a/include/hw/compat.h +++ b/include/hw/compat.h @@ -30,6 +30,10 @@ .driver =3D "virtio-pci",\ .property =3D "x-pcie-lnkctl-init",\ .value =3D "off",\ + },{\ + .driver =3D "virtio-pci",\ + .property =3D "x-pcie-pm-init",\ + .value =3D "off",\ }, =20 #define HW_COMPAT_2_7 \ diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h index 11c6247..3d8f24b 100644 --- a/include/hw/pci/pcie.h +++ b/include/hw/pci/pcie.h @@ -63,6 +63,8 @@ typedef enum { struct PCIExpressDevice { /* Offset of express capability in config space */ uint8_t exp_cap; + /* Offset of Power Management capability in config space */ + uint8_t pm_cap; =20 /* SLOT */ bool hpev_notified; /* Logical AND of conditions for hot plug event. --=20 2.5.5