[Qemu-devel] [PATCH 0/4] arm: Fix M profile MSR/MRS

Peter Maydell posted 4 patches 142 weeks ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/1487616072-9226-1-git-send-email-peter.maydell@linaro.org
Test checkpatch passed
Test docker passed
Test s390x passed
target/arm/helper.c    | 26 ++++++++++++++++++++++----
target/arm/translate.c | 26 +++++++++++++++++++++++---
2 files changed, 45 insertions(+), 7 deletions(-)

[Qemu-devel] [PATCH 0/4] arm: Fix M profile MSR/MRS

Posted by Peter Maydell 142 weeks ago
This patchseries fixes up some deficiencies and one nasty
bug in the M profile MSR/MRS handling.

The first three patches are just cleaning up the decode
so that we UNDEF where we should in the MRS/MSR space
for M profile -- this won't have caused any problems in
practice since real world code doesn't generally execute
UNDEFfing instructions on purpose.

The fourth patch fixes a nasty bug that I introduced in
commit 58117c9bb429cd which broke APSR writes via MSR,
and brings them into line with the pseudocode by allowing
writes to the APSR GE[3:0] bits when the CPU implements
the DSP extensions.

Alex -- I should have paid closer attention to your review
comments on the patch that became commit 58117c9bb429cd;
sorry about that. I knew we didn't get the GE[3:0] stuff
right yet but I didn't spot that we'd managed to invert
the sense of the SYSm bit 2 test in that patch :-(

thanks
-- PMM

Peter Maydell (4):
  arm: HVC and SMC encodings don't exist for M profile
  arm: Don't decode MRS(banked) or MSR(banked) for M profile
  arm: Enforce should-be-1 bits in MRS decoding
  arm: Fix APSR writes via M profile MSR

 target/arm/helper.c    | 26 ++++++++++++++++++++++----
 target/arm/translate.c | 26 +++++++++++++++++++++++---
 2 files changed, 45 insertions(+), 7 deletions(-)

-- 
2.7.4


Re: [Qemu-devel] [Qemu-arm] [PATCH 0/4] arm: Fix M profile MSR/MRS

Posted by Peter Maydell 139 weeks ago
Ping for review -- since this is a bugfix it should go
into 2.9.

thanks
-- PMM

On 20 February 2017 at 19:41, Peter Maydell <peter.maydell@linaro.org> wrote:
> This patchseries fixes up some deficiencies and one nasty
> bug in the M profile MSR/MRS handling.
>
> The first three patches are just cleaning up the decode
> so that we UNDEF where we should in the MRS/MSR space
> for M profile -- this won't have caused any problems in
> practice since real world code doesn't generally execute
> UNDEFfing instructions on purpose.
>
> The fourth patch fixes a nasty bug that I introduced in
> commit 58117c9bb429cd which broke APSR writes via MSR,
> and brings them into line with the pseudocode by allowing
> writes to the APSR GE[3:0] bits when the CPU implements
> the DSP extensions.
>
> Alex -- I should have paid closer attention to your review
> comments on the patch that became commit 58117c9bb429cd;
> sorry about that. I knew we didn't get the GE[3:0] stuff
> right yet but I didn't spot that we'd managed to invert
> the sense of the SYSm bit 2 test in that patch :-(
>
> thanks
> -- PMM
>
> Peter Maydell (4):
>   arm: HVC and SMC encodings don't exist for M profile
>   arm: Don't decode MRS(banked) or MSR(banked) for M profile
>   arm: Enforce should-be-1 bits in MRS decoding
>   arm: Fix APSR writes via M profile MSR
>
>  target/arm/helper.c    | 26 ++++++++++++++++++++++----
>  target/arm/translate.c | 26 +++++++++++++++++++++++---
>  2 files changed, 45 insertions(+), 7 deletions(-)

Re: [Qemu-devel] [Qemu-arm] [PATCH 0/4] arm: Fix M profile MSR/MRS

Posted by Peter Maydell 138 weeks ago
Last ping for review; otherwise I'll put them into rc1 anyway
since it's fixing a regression.

thanks
-- PMM

On 14 March 2017 at 11:52, Peter Maydell <peter.maydell@linaro.org> wrote:
> Ping for review -- since this is a bugfix it should go
> into 2.9.
>
> thanks
> -- PMM
>
> On 20 February 2017 at 19:41, Peter Maydell <peter.maydell@linaro.org> wrote:
>> This patchseries fixes up some deficiencies and one nasty
>> bug in the M profile MSR/MRS handling.
>>
>> The first three patches are just cleaning up the decode
>> so that we UNDEF where we should in the MRS/MSR space
>> for M profile -- this won't have caused any problems in
>> practice since real world code doesn't generally execute
>> UNDEFfing instructions on purpose.
>>
>> The fourth patch fixes a nasty bug that I introduced in
>> commit 58117c9bb429cd which broke APSR writes via MSR,
>> and brings them into line with the pseudocode by allowing
>> writes to the APSR GE[3:0] bits when the CPU implements
>> the DSP extensions.
>>
>> Alex -- I should have paid closer attention to your review
>> comments on the patch that became commit 58117c9bb429cd;
>> sorry about that. I knew we didn't get the GE[3:0] stuff
>> right yet but I didn't spot that we'd managed to invert
>> the sense of the SYSm bit 2 test in that patch :-(
>>
>> thanks
>> -- PMM
>>
>> Peter Maydell (4):
>>   arm: HVC and SMC encodings don't exist for M profile
>>   arm: Don't decode MRS(banked) or MSR(banked) for M profile
>>   arm: Enforce should-be-1 bits in MRS decoding
>>   arm: Fix APSR writes via M profile MSR
>>
>>  target/arm/helper.c    | 26 ++++++++++++++++++++++----
>>  target/arm/translate.c | 26 +++++++++++++++++++++++---
>>  2 files changed, 45 insertions(+), 7 deletions(-)