From nobody Wed Feb 11 03:31:10 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1487605895028413.2203588701843; Mon, 20 Feb 2017 07:51:35 -0800 (PST) Received: from localhost ([::1]:39355 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cfqFP-0002en-CG for importer@patchew.org; Mon, 20 Feb 2017 10:51:31 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40115) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cfq0g-0006Yd-Hd for qemu-devel@nongnu.org; Mon, 20 Feb 2017 10:36:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cfq0f-0003NK-FR for qemu-devel@nongnu.org; Mon, 20 Feb 2017 10:36:18 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:48583) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cfq0c-0003Lw-RS; Mon, 20 Feb 2017 10:36:15 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1cfq0U-0005gC-LN; Mon, 20 Feb 2017 15:36:06 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 20 Feb 2017 15:35:55 +0000 Message-Id: <1487604965-23220-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1487604965-23220-1-git-send-email-peter.maydell@linaro.org> References: <1487604965-23220-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 01/11] armv7m: Abstract out the "load kernel" code X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Michael Davidsaver , =?UTF-8?q?Alex=20Benn=C3=A9e?= , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Abstract the "load kernel" code out of armv7m_init() into its own function. This includes the registration of the CPU reset function, to parallel how we handle this for A profile cores. We make the function public so that boards which choose to directly instantiate an ARMv7M device object can call it. Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/arm/arm.h | 12 ++++++++++++ hw/arm/armv7m.c | 23 ++++++++++++++++++----- 2 files changed, 30 insertions(+), 5 deletions(-) diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h index c175c0e..a3f79d3 100644 --- a/include/hw/arm/arm.h +++ b/include/hw/arm/arm.h @@ -26,6 +26,18 @@ typedef enum { /* armv7m.c */ DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int nu= m_irq, const char *kernel_filename, const char *cpu_model); +/** + * armv7m_load_kernel: + * @cpu: CPU + * @kernel_filename: file to load + * @mem_size: mem_size: maximum image size to load + * + * Load the guest image for an ARMv7M system. This must be called by + * any ARMv7M board, either directly or via armv7m_init(). (This is + * necessary to ensure that the CPU resets correctly on system reset, + * as well as for kernel loading.) + */ +void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_= size); =20 /* * struct used as a parameter of the arm_load_kernel machine init diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 0c9ca7b..b2cc6e9 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -176,10 +176,6 @@ DeviceState *armv7m_init(MemoryRegion *system_memory, = int mem_size, int num_irq, ARMCPU *cpu; CPUARMState *env; DeviceState *nvic; - int image_size; - uint64_t entry; - uint64_t lowaddr; - int big_endian; =20 if (cpu_model =3D=3D NULL) { cpu_model =3D "cortex-m3"; @@ -199,6 +195,16 @@ DeviceState *armv7m_init(MemoryRegion *system_memory, = int mem_size, int num_irq, qdev_init_nofail(nvic); sysbus_connect_irq(SYS_BUS_DEVICE(nvic), 0, qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ)); + armv7m_load_kernel(cpu, kernel_filename, mem_size); + return nvic; +} + +void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_= size) +{ + int image_size; + uint64_t entry; + uint64_t lowaddr; + int big_endian; =20 #ifdef TARGET_WORDS_BIGENDIAN big_endian =3D 1; @@ -224,8 +230,15 @@ DeviceState *armv7m_init(MemoryRegion *system_memory, = int mem_size, int num_irq, } } =20 + /* CPU objects (unlike devices) are not automatically reset on system + * reset, so we must always register a handler to do so. Unlike + * A-profile CPUs, we don't need to do anything special in the + * handler to arrange that it starts correctly. + * This is arguably the wrong place to do this, but it matches the + * way A-profile does it. Note that this means that every M profile + * board must call this function! + */ qemu_register_reset(armv7m_reset, cpu); - return nvic; } =20 static Property bitband_properties[] =3D { --=20 2.7.4